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e060f6ed28
MAARs should be initialised on each CPU (or rather, core) in the system in order to achieve consistent behaviour & performance. Previously they have only been initialised on the boot CPU which leads to performance problems if tasks are later scheduled on a secondary CPU, particularly if those tasks make use of unaligned vector accesses where some CPUs don't handle any cases in hardware for non-speculative memory regions. Fix this by recording the MAAR configuration from the boot CPU and applying it to secondary CPUs as part of their bringup. Reported-by: Doug Gilmore <doug.gilmore@imgtec.com> Signed-off-by: Paul Burton <paul.burton@imgtec.com> Cc: linux-mips@linux-mips.org Cc: Rusty Russell <rusty@rustcorp.com.au> Cc: Steven J. Hill <Steven.Hill@imgtec.com> Cc: Andrew Bresticker <abrestic@chromium.org> Cc: Bjorn Helgaas <bhelgaas@google.com> Cc: David Hildenbrand <dahi@linux.vnet.ibm.com> Cc: linux-kernel@vger.kernel.org Cc: Aaro Koskinen <aaro.koskinen@iki.fi> Cc: James Hogan <james.hogan@imgtec.com> Cc: Ingo Molnar <mingo@kernel.org> Cc: Markos Chandras <markos.chandras@imgtec.com> Cc: Hemmo Nieminen <hemmo.nieminen@iki.fi> Cc: Alex Smith <alex.smith@imgtec.com> Cc: Peter Zijlstra (Intel) <peterz@infradead.org> Patchwork: https://patchwork.linux-mips.org/patch/11239/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org> |
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| .. | ||
| c-octeon.c | ||
| c-r3k.c | ||
| c-r4k.c | ||
| c-tx39.c | ||
| cache.c | ||
| cerr-sb1.c | ||
| cex-gen.S | ||
| cex-oct.S | ||
| cex-sb1.S | ||
| dma-default.c | ||
| extable.c | ||
| fault.c | ||
| gup.c | ||
| highmem.c | ||
| hugetlbpage.c | ||
| init.c | ||
| ioremap.c | ||
| Makefile | ||
| mmap.c | ||
| page-funcs.S | ||
| page.c | ||
| pgtable-32.c | ||
| pgtable-64.c | ||
| sc-ip22.c | ||
| sc-mips.c | ||
| sc-r5k.c | ||
| sc-rm7k.c | ||
| tlb-funcs.S | ||
| tlb-r3k.c | ||
| tlb-r4k.c | ||
| tlb-r8k.c | ||
| tlbex-fault.S | ||
| tlbex.c | ||
| uasm-micromips.c | ||
| uasm-mips.c | ||
| uasm.c | ||