Philipp Zabel e0d155cadb drm/imx: ipuv3-crtc: Allow to divide DI clock from TVEv2 ... This patch allows the IPU to divide the 27 MHz input clock from the TVE by two to obtain the 13.5 MHz pixel clock needed for NTSC/PAL SD modes. Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>		2015-03-31 11:59:32 +02:00
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drm	drm/imx: ipuv3-crtc: Allow to divide DI clock from TVEv2	2015-03-31 11:59:32 +02:00
host1x
ipu-v3	gpu: ipu-v3: do not divide by zero if the pixel clock is too large	2015-02-23 17:18:59 +01:00
vga
Makefile