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e208f83a7a
Signed-off-by: Mike Frysinger <michael.frysinger@analog.com> Signed-off-by: Bryan Wu <bryan.wu@analog.com>
419 lines
6.6 KiB
ArmAsm
419 lines
6.6 KiB
ArmAsm
/*
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* File: arch/blackfin/mach-common/dpmc.S
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* Based on:
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* Author: LG Soft India
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*
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* Created: ?
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* Description: Watchdog Timer APIs
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*
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* Modified:
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* Copyright 2004-2006 Analog Devices Inc.
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*
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* Bugs: Enter bugs at http://blackfin.uclinux.org/
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, see the file COPYING, or write
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* to the Free Software Foundation, Inc.,
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* 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#include <linux/linkage.h>
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#include <asm/blackfin.h>
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#include <asm/mach/irq.h>
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.text
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ENTRY(_unmask_wdog_wakeup_evt)
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[--SP] = ( R7:0, P5:0 );
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#if defined(CONFIG_BF561)
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P0.H = hi(SICA_IWR1);
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P0.L = lo(SICA_IWR1);
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#else
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P0.h = HI(SIC_IWR);
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P0.l = LO(SIC_IWR);
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#endif
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R7 = [P0];
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#if defined(CONFIG_BF561)
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BITSET(R7, 27);
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#else
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BITSET(R7,(IRQ_WATCH - IVG7));
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#endif
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[P0] = R7;
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SSYNC;
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( R7:0, P5:0 ) = [SP++];
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RTS;
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.LWRITE_TO_STAT:
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/* When watch dog timer is enabled, a write to STAT will load the
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* contents of CNT to STAT
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*/
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R7 = 0x0000(z);
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#if defined(CONFIG_BF561)
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P0.h = HI(WDOGA_STAT);
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P0.l = LO(WDOGA_STAT);
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#else
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P0.h = HI(WDOG_STAT);
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P0.l = LO(WDOG_STAT);
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#endif
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[P0] = R7;
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SSYNC;
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JUMP .LSKIP_WRITE_TO_STAT;
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ENTRY(_program_wdog_timer)
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[--SP] = ( R7:0, P5:0 );
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#if defined(CONFIG_BF561)
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P0.h = HI(WDOGA_CNT);
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P0.l = LO(WDOGA_CNT);
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#else
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P0.h = HI(WDOG_CNT);
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P0.l = LO(WDOG_CNT);
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#endif
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[P0] = R0;
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SSYNC;
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#if defined(CONFIG_BF561)
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P0.h = HI(WDOGA_CTL);
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P0.l = LO(WDOGA_CTL);
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#else
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P0.h = HI(WDOG_CTL);
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P0.l = LO(WDOG_CTL);
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#endif
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R7 = W[P0](Z);
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CC = BITTST(R7,1);
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if !CC JUMP .LWRITE_TO_STAT;
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CC = BITTST(R7,2);
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if !CC JUMP .LWRITE_TO_STAT;
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.LSKIP_WRITE_TO_STAT:
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#if defined(CONFIG_BF561)
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P0.h = HI(WDOGA_CTL);
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P0.l = LO(WDOGA_CTL);
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#else
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P0.h = HI(WDOG_CTL);
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P0.l = LO(WDOG_CTL);
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#endif
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R7 = W[P0](Z);
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BITCLR(R7,1); /* Enable GP event */
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BITSET(R7,2);
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W[P0] = R7.L;
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SSYNC;
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NOP;
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R7 = W[P0](Z);
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BITCLR(R7,4); /* Enable the wdog counter */
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W[P0] = R7.L;
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SSYNC;
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( R7:0, P5:0 ) = [SP++];
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RTS;
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ENTRY(_clear_wdog_wakeup_evt)
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[--SP] = ( R7:0, P5:0 );
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#if defined(CONFIG_BF561)
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P0.h = HI(WDOGA_CTL);
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P0.l = LO(WDOGA_CTL);
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#else
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P0.h = HI(WDOG_CTL);
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P0.l = LO(WDOG_CTL);
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#endif
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R7 = 0x0AD6(Z);
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W[P0] = R7.L;
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SSYNC;
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R7 = W[P0](Z);
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BITSET(R7,15);
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W[P0] = R7.L;
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SSYNC;
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R7 = W[P0](Z);
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BITSET(R7,1);
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BITSET(R7,2);
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W[P0] = R7.L;
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SSYNC;
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( R7:0, P5:0 ) = [SP++];
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RTS;
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ENTRY(_disable_wdog_timer)
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[--SP] = ( R7:0, P5:0 );
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#if defined(CONFIG_BF561)
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P0.h = HI(WDOGA_CTL);
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P0.l = LO(WDOGA_CTL);
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#else
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P0.h = HI(WDOG_CTL);
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P0.l = LO(WDOG_CTL);
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#endif
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R7 = 0xAD6(Z);
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W[P0] = R7.L;
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SSYNC;
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( R7:0, P5:0 ) = [SP++];
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RTS;
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#if !defined(CONFIG_BF561)
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.section .l1.text
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ENTRY(_sleep_mode)
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[--SP] = ( R7:0, P5:0 );
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[--SP] = RETS;
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call _set_sic_iwr;
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R0 = 0xFFFF (Z);
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call _set_rtc_istat
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P0.H = hi(PLL_CTL);
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P0.L = lo(PLL_CTL);
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R1 = W[P0](z);
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BITSET (R1, 3);
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W[P0] = R1.L;
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CLI R2;
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SSYNC;
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IDLE;
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STI R2;
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call _test_pll_locked;
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R0 = IWR_ENABLE(0);
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call _set_sic_iwr;
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P0.H = hi(PLL_CTL);
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P0.L = lo(PLL_CTL);
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R7 = w[p0](z);
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BITCLR (R7, 3);
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BITCLR (R7, 5);
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w[p0] = R7.L;
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IDLE;
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call _test_pll_locked;
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RETS = [SP++];
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( R7:0, P5:0 ) = [SP++];
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RTS;
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ENTRY(_hibernate_mode)
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[--SP] = ( R7:0, P5:0 );
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[--SP] = RETS;
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call _set_sic_iwr;
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R0 = 0xFFFF (Z);
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call _set_rtc_istat
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P0.H = hi(VR_CTL);
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P0.L = lo(VR_CTL);
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R1 = W[P0](z);
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BITSET (R1, 8);
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BITCLR (R1, 0);
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BITCLR (R1, 1);
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W[P0] = R1.L;
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SSYNC;
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CLI R2;
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IDLE;
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/* Actually, adding anything may not be necessary...SDRAM contents
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* are lost
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*/
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ENTRY(_deep_sleep)
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[--SP] = ( R7:0, P5:0 );
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[--SP] = RETS;
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CLI R4;
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call _set_sic_iwr;
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call _set_sdram_srfs;
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/* Clear all the interrupts,bits sticky */
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R0 = 0xFFFF (Z);
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call _set_rtc_istat
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P0.H = hi(PLL_CTL);
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P0.L = lo(PLL_CTL);
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R0 = W[P0](z);
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BITSET (R0, 5);
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W[P0] = R0.L;
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call _test_pll_locked;
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SSYNC;
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IDLE;
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call _unset_sdram_srfs;
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call _test_pll_locked;
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R0 = IWR_ENABLE(0);
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call _set_sic_iwr;
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P0.H = hi(PLL_CTL);
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P0.L = lo(PLL_CTL);
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R0 = w[p0](z);
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BITCLR (R0, 3);
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BITCLR (R0, 5);
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BITCLR (R0, 8);
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w[p0] = R0;
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IDLE;
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call _test_pll_locked;
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STI R4;
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RETS = [SP++];
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( R7:0, P5:0 ) = [SP++];
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RTS;
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ENTRY(_sleep_deeper)
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[--SP] = ( R7:0, P5:0 );
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[--SP] = RETS;
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CLI R4;
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P3 = R0;
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R0 = IWR_ENABLE(0);
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call _set_sic_iwr;
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call _set_sdram_srfs;
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/* Clear all the interrupts,bits sticky */
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R0 = 0xFFFF (Z);
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call _set_rtc_istat
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P0.H = hi(PLL_DIV);
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P0.L = lo(PLL_DIV);
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R6 = W[P0](z);
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R0.L = 0xF;
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W[P0] = R0.l;
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P0.H = hi(PLL_CTL);
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P0.L = lo(PLL_CTL);
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R5 = W[P0](z);
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R0.L = (MIN_VC/CONFIG_CLKIN_HZ) << 9;
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W[P0] = R0.l;
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SSYNC;
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IDLE;
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call _test_pll_locked;
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P0.H = hi(VR_CTL);
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P0.L = lo(VR_CTL);
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R7 = W[P0](z);
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R1 = 0x6;
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R1 <<= 16;
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R2 = 0x0404(Z);
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R1 = R1|R2;
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R2 = DEPOSIT(R7, R1);
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W[P0] = R2;
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SSYNC;
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IDLE;
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call _test_pll_locked;
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P0.H = hi(PLL_CTL);
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P0.L = lo(PLL_CTL);
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R0 = W[P0](z);
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BITSET (R0, 3);
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W[P0] = R0.L;
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R0 = P3;
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call _set_sic_iwr;
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SSYNC;
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IDLE;
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call _test_pll_locked;
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R0 = IWR_ENABLE(0);
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call _set_sic_iwr;
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P0.H = hi(VR_CTL);
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P0.L = lo(VR_CTL);
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W[P0]= R7;
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SSYNC;
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IDLE;
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call _test_pll_locked;
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P0.H = hi(PLL_DIV);
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P0.L = lo(PLL_DIV);
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W[P0]= R6;
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P0.H = hi(PLL_CTL);
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P0.L = lo(PLL_CTL);
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w[p0] = R5;
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IDLE;
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call _test_pll_locked;
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call _unset_sdram_srfs;
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STI R4;
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RETS = [SP++];
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( R7:0, P5:0 ) = [SP++];
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RTS;
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ENTRY(_set_sdram_srfs)
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/* set the sdram to self refresh mode */
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P0.H = hi(EBIU_SDGCTL);
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P0.L = lo(EBIU_SDGCTL);
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R2 = [P0];
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R3.H = hi(SRFS);
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R3.L = lo(SRFS);
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R2 = R2|R3;
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[P0] = R2;
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ssync;
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RTS;
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ENTRY(_unset_sdram_srfs)
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/* set the sdram out of self refresh mode */
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P0.H = hi(EBIU_SDGCTL);
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P0.L = lo(EBIU_SDGCTL);
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R2 = [P0];
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R3.H = hi(SRFS);
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R3.L = lo(SRFS);
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R3 = ~R3;
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R2 = R2&R3;
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[P0] = R2;
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ssync;
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RTS;
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ENTRY(_set_sic_iwr)
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P0.H = hi(SIC_IWR);
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P0.L = lo(SIC_IWR);
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[P0] = R0;
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SSYNC;
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RTS;
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ENTRY(_set_rtc_istat)
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P0.H = hi(RTC_ISTAT);
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P0.L = lo(RTC_ISTAT);
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w[P0] = R0.L;
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SSYNC;
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RTS;
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ENTRY(_test_pll_locked)
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P0.H = hi(PLL_STAT);
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P0.L = lo(PLL_STAT);
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1:
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R0 = W[P0] (Z);
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CC = BITTST(R0,5);
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IF !CC JUMP 1b;
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RTS;
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#endif
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