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e317872ac5
Shared (platform) headers Signed-off-by: dmitry pervushin <dpervushin@embeddedalley.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
196 lines
6.6 KiB
C
196 lines
6.6 KiB
C
/*
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* Freescale STMP37XX/STMP378X SoC register access interfaces
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*
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* The SoC registers may be accessed via:
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*
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* - single 32 bit address, or
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* - four 32 bit addresses - general purpose, set, clear and toggle bits
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*
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* Multiple IP blocks (e.g. SSP, UART) provide identical register sets per
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* each module
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*
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* Embedded Alley Solutions, Inc <source@embeddedalley.com>
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*
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* Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved.
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* Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
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*/
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/*
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* The code contained herein is licensed under the GNU General Public
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* License. You may obtain a copy of the GNU General Public License
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* Version 2 or later at the following locations:
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*
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* http://www.opensource.org/licenses/gpl-license.html
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* http://www.gnu.org/copyleft/gpl.html
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*/
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#ifndef __ASM_PLAT_STMP3XXX_REGS_H
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#define __ASM_PLAT_STMP3XXX_REGS_H
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#ifndef __ASSEMBLER__
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#include <linux/io.h>
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#endif
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#include "platform.h"
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#define REGS_BASE STMP3XXX_REGS_BASE
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#define HW_STMP3xxx_SET 0x04
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#define HW_STMP3xxx_CLR 0x08
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#define HW_STMP3xxx_TOG 0x0c
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#ifndef __ASSEMBLER__
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#define HW_REGISTER_FUNCS(id, base, offset, regset, rd, wr) \
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static const u32 id##_OFFSET = offset; \
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static inline u32 id##_RD_NB(const void __iomem *regbase) { \
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if (!rd) \
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printk(KERN_ERR"%s: cannot READ at %p+%x\n", \
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#id, regbase, offset); \
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return __raw_readl(regbase + offset); \
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} \
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static inline void id##_WR_NB(void __iomem *regbase, u32 v) { \
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if (!wr) \
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printk(KERN_ERR"%s: cannot WRITE at %p+%x\n", \
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#id, regbase, offset); \
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__raw_writel(v, regbase + offset); \
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} \
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static inline void id##_SET_NB(void __iomem *regbase, u32 v) { \
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if (!wr) \
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printk(KERN_ERR"%s: cannot SET at %p+%x\n", \
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#id, regbase, offset); \
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if (regset) \
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__raw_writel(v, regbase + \
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offset + HW_STMP3xxx_SET); \
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else \
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__raw_writel(v | __raw_readl(regbase + offset), \
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regbase + offset); \
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} \
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static inline void id##_CLR_NB(void __iomem *regbase, u32 v) { \
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if (!wr) \
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printk(KERN_ERR"%s: cannot CLR at %p+%x\n", \
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#id, regbase, offset); \
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if (regset) \
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__raw_writel(v, regbase + \
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offset + HW_STMP3xxx_CLR); \
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else \
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__raw_writel( \
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~v & __raw_readl(regbase + offset), \
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regbase + offset); \
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} \
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static inline void id##_TOG_NB(void __iomem *regbase, u32 v) { \
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if (!wr) \
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printk(KERN_ERR"%s: cannot TOG at %p+%x\n", \
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#id, regbase, offset); \
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if (regset) \
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__raw_writel(v, regbase + \
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offset + HW_STMP3xxx_TOG); \
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else \
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__raw_writel(v ^ __raw_readl(regbase + offset), \
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regbase + offset); \
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} \
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static inline u32 id##_RD(void) { return id##_RD_NB(base); } \
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static inline void id##_WR(u32 v) { id##_WR_NB(base, v); } \
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static inline void id##_SET(u32 v) { id##_SET_NB(base, v); } \
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static inline void id##_CLR(u32 v) { id##_CLR_NB(base, v); } \
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static inline void id##_TOG(u32 v) { id##_TOG_NB(base, v); }
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#define HW_REGISTER_FUNCS_INDEXED(id, base, offset, regset, rd, wr, step)\
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static inline u32 id##_OFFSET(int i) { \
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return offset + i * step; \
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} \
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static inline u32 id##_RD_NB(const void __iomem *regbase, int i) {\
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if (!rd) \
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printk(KERN_ERR"%s(%d): can't READ at %p+%x\n", \
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#id, i, regbase, offset + i * step); \
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return __raw_readl(regbase + offset + i * step); \
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} \
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static inline void id##_WR_NB(void __iomem *regbase, int i, u32 v) {\
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if (!wr) \
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printk(KERN_ERR"%s(%d): can't WRITE at %p+%x\n",\
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#id, i, regbase, offset + i * step); \
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__raw_writel(v, regbase + offset + i * step); \
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} \
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static inline void id##_SET_NB(void __iomem *regbase, int i, u32 v) {\
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if (!wr) \
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printk(KERN_ERR"%s(%d): can't SET at %p+%x\n", \
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#id, i, regbase, offset + i * step); \
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if (regset) \
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__raw_writel(v, regbase + offset + \
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i * step + HW_STMP3xxx_SET); \
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else \
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__raw_writel(v | __raw_readl(regbase + \
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offset + i * step), \
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regbase + offset + i * step); \
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} \
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static inline void id##_CLR_NB(void __iomem *regbase, int i, u32 v) {\
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if (!wr) \
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printk(KERN_ERR"%s(%d): cannot CLR at %p+%x\n", \
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#id, i, regbase, offset + i * step); \
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if (regset) \
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__raw_writel(v, regbase + offset + \
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i * step + HW_STMP3xxx_CLR); \
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else \
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__raw_writel(~v & __raw_readl(regbase + \
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offset + i * step), \
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regbase + offset + i * step); \
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} \
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static inline void id##_TOG_NB(void __iomem *regbase, int i, u32 v) {\
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if (!wr) \
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printk(KERN_ERR"%s(%d): cannot TOG at %p+%x\n", \
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#id, i, regbase, offset + i * step); \
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if (regset) \
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__raw_writel(v, regbase + offset + \
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i * step + HW_STMP3xxx_TOG); \
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else \
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__raw_writel(v ^ __raw_readl(regbase + offset \
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+ i * step), \
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regbase + offset + i * step); \
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} \
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static inline u32 id##_RD(int i) \
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{ \
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return id##_RD_NB(base, i); \
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} \
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static inline void id##_WR(int i, u32 v) \
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{ \
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id##_WR_NB(base, i, v); \
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} \
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static inline void id##_SET(int i, u32 v) \
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{ \
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id##_SET_NB(base, i, v); \
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} \
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static inline void id##_CLR(int i, u32 v) \
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{ \
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id##_CLR_NB(base, i, v); \
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} \
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static inline void id##_TOG(int i, u32 v) \
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{ \
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id##_TOG_NB(base, i, v); \
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}
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#define HW_REGISTER_WO(id, base, offset)\
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HW_REGISTER_FUNCS(id, base, offset, 1, 0, 1)
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#define HW_REGISTER_RO(id, base, offset)\
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HW_REGISTER_FUNCS(id, base, offset, 1, 1, 0)
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#define HW_REGISTER(id, base, offset) \
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HW_REGISTER_FUNCS(id, base, offset, 1, 1, 1)
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#define HW_REGISTER_0(id, base, offset) \
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HW_REGISTER_FUNCS(id, base, offset, 0, 1, 1)
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#define HW_REGISTER_INDEXED(id, base, offset, step) \
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HW_REGISTER_FUNCS_INDEXED(id, base, offset, 1, 1, 1, step)
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#define HW_REGISTER_RO_INDEXED(id, base, offset, step) \
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HW_REGISTER_FUNCS_INDEXED(id, base, offset, 1, 1, 0, step)
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#define HW_REGISTER_0_INDEXED(id, base, offset, step) \
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HW_REGISTER_FUNCS_INDEXED(id, base, offset, 0, 1, 1, step)
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#else /* __ASSEMBLER__ */
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#define HW_REGISTER_FUNCS(id, base, offset, regset, rd, wr)
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#define HW_REGISTER_FUNCS_INDEXED(id, base, offset, regset, rd, wr, step)
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#define HW_REGISTER_WO(id, base, offset)
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#define HW_REGISTER_RO(id, base, offset)
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#define HW_REGISTER(id, base, offset)
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#define HW_REGISTER_0(id, base, offset)
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#define HW_REGISTER_INDEXED(id, base, offset, step)
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#define HW_REGISTER_RO_INDEXED(id, base, offset, step)
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#define HW_REGISTER_0_INDEXED(id, base, offset, step)
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#endif /* __ASSEMBLER__ */
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#endif /* __ASM_PLAT_STMP3XXX_REGS_H */
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