Dale Farnsworth e44b894190 [POWERPC] Add interrupt support for Marvell mv64x60 chips
There are 3 interrupt groups each with its own status/mask registers.
We use a separate struct irq_chip for each interrupt group and handle
interrupts in two stages or levels: level 1 selects the appropriate
struct irq_chip, and level 2 selects individual interrupts within
that irq_chip.

Signed-off-by: Dale Farnsworth <dale@farnsworth.org>
Signed-off-by: Paul Mackerras <paulus@samba.org>
2007-05-12 11:32:49 +10:00
..
2007-05-08 11:15:18 -07:00
2007-05-09 12:30:56 -07:00
2007-05-09 07:12:20 +02:00
2007-05-11 08:29:33 -07:00
2007-05-11 08:29:33 -07:00
2007-05-09 12:30:56 -07:00
2007-05-12 11:32:49 +10:00
2007-05-11 05:38:25 -04:00
2007-05-08 11:15:08 -07:00
2007-05-09 12:30:56 -07:00
2007-05-11 05:38:25 -04:00
2007-05-11 08:29:34 -07:00