Christoph Hellwig 10314e09d0 riscv: add swiotlb support ...

All RISC-V platforms today lack an IOMMU. However, legacy PCI devices
sometimes require DMA-memory to be in the low 32 bits.  To make this work,
we enable the software-based bounce buffers from swiotlb.  They only impose
overhead when the device in question cannot address the full 64-bit address
space, so a perfect fit.

This patch assumes that DMA is coherent with the processor and the PCI
bus.  It also assumes that the processor and devices share a common
address space. This is true for all RISC-V platforms so far.

[changelog stolen from an earlier patch by Palmer Dabbelt that did the
 more complicated swiotlb wireup before the recent consolidation]

Signed-off-by: Christoph Hellwig <hch@lst.de>
Reviewed-by: Palmer Dabbelt <palmer@sifive.com>

2018-05-19 08:46:26 +02:00

..

configs

RISC-V: Enable module support in defconfig

2018-04-02 20:00:56 -07:00

include

riscv: add swiotlb support

2018-05-19 08:46:26 +02:00

kernel

riscv: add swiotlb support

2018-05-19 08:46:26 +02:00

lib

RISC-V: Export some expected symbols for modules

2017-11-30 10:01:10 -08:00

mm

RISC-V changes for 4.16

2018-02-07 11:33:08 -08:00

Kconfig

riscv: add swiotlb support

2018-05-19 08:46:26 +02:00

Makefile

RISC-V: Fixes to module loading

2018-04-02 20:43:14 -07:00