Pavel Pisa b3c6b76ffb [ARM] 4255/1: i.MX/MX1 Correct MPU PLL reference clock value.
Only System PLL clock source is selectable by CSCR_SYSTEM_SEL
bit. MPU PLL is driven by 512*CLK32 for each case.

Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2007-03-12 16:49:35 +00:00
..
2007-02-20 19:13:30 +00:00
2007-01-24 11:59:57 +00:00
2007-03-05 07:57:51 -08:00
2006-11-30 12:24:47 +00:00
2007-02-20 15:28:40 +00:00