Al Cooper da4b62cd67 MIPS: perf: Add cpu feature bit for PCI (performance counter interrupt) ... The PCI (Program Counter Interrupt) bit in the "cause" register is mandatory for MIPS32R2 cores, but has also been added to some R1 cores (BMIPS5000). This change adds a cpu feature bit to make it easier to check for and use this feature. Signed-off-by: Al Cooper <alcooperx@gmail.com> Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/4106/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>		2012-10-11 11:04:34 +02:00
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asm	MIPS: perf: Add cpu feature bit for PCI (performance counter interrupt)	2012-10-11 11:04:34 +02:00
uapi/asm	UAPI: (Scripted) Set up UAPI Kbuild files	2012-10-02 18:01:35 +01:00