..
board-paz00.c
ARM: tegra: paz00: Fix __initdata placement
2017-01-25 09:09:32 +01:00
board.h
ARM: tegra: Convert PMC to a driver
2014-07-17 14:58:43 +02:00
common.h
ARM: tegra: hotplug: Include missing common.h
2016-06-10 16:17:58 +02:00
cpuidle-tegra20.c
ARM: tegra: cpuidle: Add missing cpuidle.h include
2016-06-10 16:17:59 +02:00
cpuidle-tegra30.c
ARM: tegra: cpuidle: Add missing cpuidle.h include
2016-06-10 16:17:59 +02:00
cpuidle-tegra114.c
ARM: tegra: cpuidle: Add missing cpuidle.h include
2016-06-10 16:17:59 +02:00
cpuidle.c
ARM: tegra: Use a function to get the chip ID
2014-07-17 13:36:41 +02:00
cpuidle.h
ARM: tegra: cpuidle: Add missing cpuidle.h include
2016-06-10 16:17:59 +02:00
flowctrl.c
ARM: tegra: Initialize flow controller from DT
2014-08-26 11:43:55 -06:00
flowctrl.h
ARM: tegra: Initialize flow controller from DT
2014-08-26 11:43:55 -06:00
hotplug.c
ARM: tegra: hotplug: Include missing common.h
2016-06-10 16:17:58 +02:00
io.c
ARM: tegra: Sort includes alphabetically
2014-07-17 13:29:57 +02:00
iomap.h
soc/tegra: fuse: Unify Tegra20 and Tegra30 drivers
2015-07-16 10:38:28 +02:00
irammap.h
ARM: tegra: move resume vector define to irammap.h
2013-09-17 13:44:22 -06:00
irq.c
ARM: tegra: irq: Add missing irq.h include
2016-06-10 16:18:00 +02:00
irq.h
ARM: tegra: remove old LIC support
2015-03-15 00:40:52 +00:00
Kconfig
ARM: do away with ARCH_[WANT_OPTIONAL|REQUIRE]_GPIOLIB
2016-06-03 12:18:13 -07:00
Makefile
ARM: v7 setup function should invalidate L1 cache
2015-06-01 11:30:26 +01:00
platsmp.c
soc/tegra: pmc: Wait for powergate state to change
2016-04-05 15:22:53 +02:00
pm-tegra20.c
ARM: tegra: Sort includes alphabetically
2014-07-17 13:29:57 +02:00
pm-tegra30.c
ARM: tegra: Sort includes alphabetically
2014-07-17 13:29:57 +02:00
pm.c
ARM: tegra: Convert PMC to a driver
2014-07-17 14:58:43 +02:00
pm.h
ARM: tegra: pm: Add tegra_cpu_do_idle() prototype
2016-06-10 16:18:01 +02:00
reset-handler.S
ARM: tegra20: Store CPU "resettable" status in IRAM
2015-05-04 12:58:19 +02:00
reset.c
ARM: v7 setup function should invalidate L1 cache
2015-06-01 11:30:26 +01:00
reset.h
ARM: SoC: platform support for v4.2
2015-06-26 11:34:35 -07:00
sleep-tegra20.S
ARM: tegra: Ensure entire dcache is flushed on entering LP0/1
2015-11-24 16:47:26 +01:00
sleep-tegra30.S
ARM: tegra: Ensure entire dcache is flushed on entering LP0/1
2015-11-24 16:47:26 +01:00
sleep.h
ARM: tegra20: Store CPU "resettable" status in IRAM
2015-05-04 12:58:19 +02:00
sleep.S
ARM: convert all "mov.* pc, reg" to "bx reg" for ARMv6+
2014-07-18 12:29:04 +01:00
tegra.c
ARM: SoC cleanups for v4.8
2016-08-01 18:21:13 -04:00