Chris Wilson f0a1fb10e5 drm/i915: Insert a command barrier on BLT/BSD cache flushes ... This looked like an odd regression from commit ec5cc0f9b0 Author: Chris Wilson <chris@chris-wilson.co.uk> Date: Thu Jun 12 10:28:55 2014 +0100 drm/i915: Restrict GPU boost to the RCS engine but in reality it undercovered a much older coherency bug. The issue that boosting the GPU frequency on the BCS ring was masking was that we could wake the CPU up after completion of a BCS batch and inspect memory prior to the write cache being fully evicted. In order to serialise the breadcrumb interrupt (and so ensure that the CPU's view of memory is coherent) we need to perform a post-sync operation in the MI_FLUSH_DW. v2: Fix all the MI_FLUSH_DW (bsd plus the duplication in execlists). Also fix the invalidate_domains mask in gen8_emit_flush() for ring != VCS. Testcase: gpuX-rcs-gpu-read-after-write Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Cc: stable@vger.kernel.org Acked-by: Daniel Vetter <daniel@ffwll.ch> Signed-off-by: Jani Nikula <jani.nikula@intel.com>		2015-02-09 20:03:15 +02:00
..
drm	drm/i915: Insert a command barrier on BLT/BSD cache flushes	2015-02-09 20:03:15 +02:00
host1x	gpu: host1x: mipi: Set MIPI_CAL_BIAS_PAD_CFG1 register	2014-11-13 16:11:57 +01:00
ipu-v3	gpu: ipu-di: Switch to DIV_ROUND_CLOSEST for DI clock divider calc	2015-01-07 19:15:04 +01:00
vga	Merge branch 'sched-core-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip	2014-10-13 16:23:15 +02:00
Makefile