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f428ebd184
Someone got the load and store barriers mixed up for AAAAARGH64. Turn
them the right side up.
Reported-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: Peter Zijlstra <peterz@infradead.org>
Fixes: a94d342b9c ("tools/perf: Add required memory barriers")
Cc: Ingo Molnar <mingo@kernel.org>
Cc: Will Deacon <will.deacon@arm.com>
Link: http://lkml.kernel.org/r/20140124154002.GF31570@twins.programming.kicks-ass.net
Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
283 lines
6.7 KiB
C
283 lines
6.7 KiB
C
#ifndef _PERF_PERF_H
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#define _PERF_PERF_H
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#include <asm/unistd.h>
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#if defined(__i386__)
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#define mb() asm volatile("lock; addl $0,0(%%esp)" ::: "memory")
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#define wmb() asm volatile("lock; addl $0,0(%%esp)" ::: "memory")
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#define rmb() asm volatile("lock; addl $0,0(%%esp)" ::: "memory")
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#define cpu_relax() asm volatile("rep; nop" ::: "memory");
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#define CPUINFO_PROC "model name"
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#ifndef __NR_perf_event_open
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# define __NR_perf_event_open 336
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#endif
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#endif
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#if defined(__x86_64__)
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#define mb() asm volatile("mfence" ::: "memory")
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#define wmb() asm volatile("sfence" ::: "memory")
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#define rmb() asm volatile("lfence" ::: "memory")
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#define cpu_relax() asm volatile("rep; nop" ::: "memory");
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#define CPUINFO_PROC "model name"
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#ifndef __NR_perf_event_open
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# define __NR_perf_event_open 298
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#endif
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#endif
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#ifdef __powerpc__
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#include "../../arch/powerpc/include/uapi/asm/unistd.h"
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#define mb() asm volatile ("sync" ::: "memory")
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#define wmb() asm volatile ("sync" ::: "memory")
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#define rmb() asm volatile ("sync" ::: "memory")
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#define CPUINFO_PROC "cpu"
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#endif
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#ifdef __s390__
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#define mb() asm volatile("bcr 15,0" ::: "memory")
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#define wmb() asm volatile("bcr 15,0" ::: "memory")
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#define rmb() asm volatile("bcr 15,0" ::: "memory")
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#endif
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#ifdef __sh__
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#if defined(__SH4A__) || defined(__SH5__)
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# define mb() asm volatile("synco" ::: "memory")
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# define wmb() asm volatile("synco" ::: "memory")
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# define rmb() asm volatile("synco" ::: "memory")
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#else
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# define mb() asm volatile("" ::: "memory")
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# define wmb() asm volatile("" ::: "memory")
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# define rmb() asm volatile("" ::: "memory")
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#endif
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#define CPUINFO_PROC "cpu type"
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#endif
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#ifdef __hppa__
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#define mb() asm volatile("" ::: "memory")
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#define wmb() asm volatile("" ::: "memory")
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#define rmb() asm volatile("" ::: "memory")
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#define CPUINFO_PROC "cpu"
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#endif
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#ifdef __sparc__
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#ifdef __LP64__
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#define mb() asm volatile("ba,pt %%xcc, 1f\n" \
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"membar #StoreLoad\n" \
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"1:\n":::"memory")
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#else
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#define mb() asm volatile("":::"memory")
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#endif
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#define wmb() asm volatile("":::"memory")
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#define rmb() asm volatile("":::"memory")
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#define CPUINFO_PROC "cpu"
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#endif
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#ifdef __alpha__
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#define mb() asm volatile("mb" ::: "memory")
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#define wmb() asm volatile("wmb" ::: "memory")
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#define rmb() asm volatile("mb" ::: "memory")
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#define CPUINFO_PROC "cpu model"
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#endif
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#ifdef __ia64__
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#define mb() asm volatile ("mf" ::: "memory")
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#define wmb() asm volatile ("mf" ::: "memory")
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#define rmb() asm volatile ("mf" ::: "memory")
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#define cpu_relax() asm volatile ("hint @pause" ::: "memory")
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#define CPUINFO_PROC "model name"
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#endif
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#ifdef __arm__
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/*
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* Use the __kuser_memory_barrier helper in the CPU helper page. See
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* arch/arm/kernel/entry-armv.S in the kernel source for details.
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*/
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#define mb() ((void(*)(void))0xffff0fa0)()
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#define wmb() ((void(*)(void))0xffff0fa0)()
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#define rmb() ((void(*)(void))0xffff0fa0)()
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#define CPUINFO_PROC "Processor"
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#endif
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#ifdef __aarch64__
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#define mb() asm volatile("dmb ish" ::: "memory")
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#define wmb() asm volatile("dmb ishst" ::: "memory")
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#define rmb() asm volatile("dmb ishld" ::: "memory")
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#define cpu_relax() asm volatile("yield" ::: "memory")
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#endif
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#ifdef __mips__
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#define mb() asm volatile( \
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".set mips2\n\t" \
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"sync\n\t" \
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".set mips0" \
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: /* no output */ \
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: /* no input */ \
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: "memory")
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#define wmb() mb()
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#define rmb() mb()
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#define CPUINFO_PROC "cpu model"
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#endif
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#ifdef __arc__
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#define mb() asm volatile("" ::: "memory")
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#define wmb() asm volatile("" ::: "memory")
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#define rmb() asm volatile("" ::: "memory")
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#define CPUINFO_PROC "Processor"
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#endif
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#ifdef __metag__
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#define mb() asm volatile("" ::: "memory")
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#define wmb() asm volatile("" ::: "memory")
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#define rmb() asm volatile("" ::: "memory")
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#define CPUINFO_PROC "CPU"
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#endif
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#ifdef __xtensa__
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#define mb() asm volatile("memw" ::: "memory")
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#define wmb() asm volatile("memw" ::: "memory")
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#define rmb() asm volatile("" ::: "memory")
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#define CPUINFO_PROC "core ID"
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#endif
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#define barrier() asm volatile ("" ::: "memory")
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#ifndef cpu_relax
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#define cpu_relax() barrier()
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#endif
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#define ACCESS_ONCE(x) (*(volatile typeof(x) *)&(x))
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#include <time.h>
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#include <unistd.h>
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#include <sys/types.h>
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#include <sys/syscall.h>
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#include <linux/perf_event.h>
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#include "util/types.h"
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#include <stdbool.h>
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/*
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* prctl(PR_TASK_PERF_EVENTS_DISABLE) will (cheaply) disable all
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* counters in the current task.
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*/
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#define PR_TASK_PERF_EVENTS_DISABLE 31
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#define PR_TASK_PERF_EVENTS_ENABLE 32
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#ifndef NSEC_PER_SEC
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# define NSEC_PER_SEC 1000000000ULL
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#endif
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#ifndef NSEC_PER_USEC
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# define NSEC_PER_USEC 1000ULL
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#endif
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static inline unsigned long long rdclock(void)
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{
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struct timespec ts;
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clock_gettime(CLOCK_MONOTONIC, &ts);
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return ts.tv_sec * 1000000000ULL + ts.tv_nsec;
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}
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/*
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* Pick up some kernel type conventions:
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*/
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#define __user
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#define asmlinkage
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#define unlikely(x) __builtin_expect(!!(x), 0)
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#define min(x, y) ({ \
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typeof(x) _min1 = (x); \
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typeof(y) _min2 = (y); \
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(void) (&_min1 == &_min2); \
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_min1 < _min2 ? _min1 : _min2; })
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extern bool test_attr__enabled;
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void test_attr__init(void);
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void test_attr__open(struct perf_event_attr *attr, pid_t pid, int cpu,
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int fd, int group_fd, unsigned long flags);
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static inline int
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sys_perf_event_open(struct perf_event_attr *attr,
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pid_t pid, int cpu, int group_fd,
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unsigned long flags)
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{
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int fd;
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fd = syscall(__NR_perf_event_open, attr, pid, cpu,
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group_fd, flags);
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if (unlikely(test_attr__enabled))
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test_attr__open(attr, pid, cpu, fd, group_fd, flags);
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return fd;
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}
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#define MAX_COUNTERS 256
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#define MAX_NR_CPUS 256
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struct ip_callchain {
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u64 nr;
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u64 ips[0];
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};
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struct branch_flags {
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u64 mispred:1;
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u64 predicted:1;
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u64 in_tx:1;
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u64 abort:1;
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u64 reserved:60;
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};
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struct branch_entry {
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u64 from;
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u64 to;
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struct branch_flags flags;
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};
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struct branch_stack {
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u64 nr;
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struct branch_entry entries[0];
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};
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extern const char *input_name;
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extern bool perf_host, perf_guest;
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extern const char perf_version_string[];
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void pthread__unblock_sigwinch(void);
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#include "util/target.h"
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enum perf_call_graph_mode {
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CALLCHAIN_NONE,
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CALLCHAIN_FP,
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CALLCHAIN_DWARF
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};
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struct record_opts {
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struct target target;
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int call_graph;
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bool group;
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bool inherit_stat;
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bool no_buffering;
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bool no_inherit;
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bool no_inherit_set;
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bool no_samples;
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bool raw_samples;
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bool sample_address;
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bool sample_weight;
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bool sample_time;
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bool period;
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unsigned int freq;
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unsigned int mmap_pages;
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unsigned int user_freq;
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u64 branch_stack;
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u64 default_interval;
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u64 user_interval;
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u16 stack_dump_size;
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bool sample_transaction;
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unsigned initial_delay;
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};
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#endif
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