Manuel Lauss 694b8c35e9 MIPS: Remove __init from add_wired_entry() ... For Alchemy-PCI I need to add a wired entry after resuming from RAM; remove the __init from add_wired_entry() so that this actually works. Signed-off-by: Manuel Lauss <manuel.lauss@googlemail.com> To: Linux-MIPS <linux-mips@linux-mips.org> Patchwork: https://patchwork.linux-mips.org/patch/2684/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>		2011-10-24 23:34:23 +01:00
..
c-octeon.c	MIPS: cache: Provide cache flush operations for XFS	2011-10-20 15:00:18 +01:00
c-r3k.c	MIPS: cache: Provide cache flush operations for XFS	2011-10-20 15:00:18 +01:00
c-r4k.c	MIPS: cache: Provide cache flush operations for XFS	2011-10-20 15:00:18 +01:00
c-tx39.c	MIPS: cache: Provide cache flush operations for XFS	2011-10-20 15:00:18 +01:00
cache.c	MIPS: cache: Provide cache flush operations for XFS	2011-10-20 15:00:18 +01:00
cerr-sb1.c
cex-gen.S
cex-oct.S
cex-sb1.S
dma-default.c
extable.c
fault.c
highmem.c
hugetlbpage.c
init.c
ioremap.c
Makefile
mmap.c
page.c
pgtable-32.c
pgtable-64.c
sc-ip22.c
sc-mips.c
sc-r5k.c
sc-rm7k.c
tlb-r3k.c	MIPS: Remove __init from add_wired_entry()	2011-10-24 23:34:23 +01:00
tlb-r4k.c	MIPS: Remove __init from add_wired_entry()	2011-10-24 23:34:23 +01:00
tlb-r8k.c
tlbex-fault.S
tlbex.c	MIPS: No branches in delay slots for huge pages in handle_tlbl	2011-09-21 17:54:07 +02:00
uasm.c