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The cpu compatible string we look for is "SPARC-T3". As far as memset/memcpy optimizations go, we treat this chip the same as Niagara-T2/T2+. Use cache initializing stores for memset, and use perfetch, FPU block loads, cache initializing stores, and block stores for copies. We use the Niagara-T2 perf support, since T3 is a close relative in this regard. Later we'll add support for the new events T3 can report, plus enable T3's new "sample" mode. For now I haven't added any new ELF hwcap flags. We probably need to add a couple, for example: T2 and T3 both support the population count instruction in hardware. T3 supports VIS3 instructions, including support (finally) for partitioned shift. One can also now move directly between float and integer registers. T3 supports instructions meant to help with Galois Field and other HPC calculations, such as XOR multiply. Also there are "OP and negate" instructions, for example "fnmul" which is multiply-and-negate. T3 recognizes the transactional memory opcodes, however since transactional memory isn't supported: 1) 'commit' behaves as a NOP and 2) 'chkpt' always branches 3) 'rdcps' returns all zeros and 4) 'wrcps' behaves as a NOP. So we'll need about 3 new elf capability flags in the end to represent all of these things. Signed-off-by: David S. Miller <davem@davemloft.net>
72 lines
2.5 KiB
C
72 lines
2.5 KiB
C
/*
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* include/asm/xor.h
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*
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* High speed xor_block operation for RAID4/5 utilizing the
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* UltraSparc Visual Instruction Set and Niagara block-init
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* twin-load instructions.
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*
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* Copyright (C) 1997, 1999 Jakub Jelinek (jj@ultra.linux.cz)
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* Copyright (C) 2006 David S. Miller <davem@davemloft.net>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2, or (at your option)
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* any later version.
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*
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* You should have received a copy of the GNU General Public License
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* (for example /usr/src/linux/COPYING); if not, write to the Free
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* Software Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
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*/
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#include <asm/spitfire.h>
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extern void xor_vis_2(unsigned long, unsigned long *, unsigned long *);
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extern void xor_vis_3(unsigned long, unsigned long *, unsigned long *,
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unsigned long *);
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extern void xor_vis_4(unsigned long, unsigned long *, unsigned long *,
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unsigned long *, unsigned long *);
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extern void xor_vis_5(unsigned long, unsigned long *, unsigned long *,
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unsigned long *, unsigned long *, unsigned long *);
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/* XXX Ugh, write cheetah versions... -DaveM */
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static struct xor_block_template xor_block_VIS = {
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.name = "VIS",
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.do_2 = xor_vis_2,
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.do_3 = xor_vis_3,
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.do_4 = xor_vis_4,
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.do_5 = xor_vis_5,
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};
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extern void xor_niagara_2(unsigned long, unsigned long *, unsigned long *);
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extern void xor_niagara_3(unsigned long, unsigned long *, unsigned long *,
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unsigned long *);
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extern void xor_niagara_4(unsigned long, unsigned long *, unsigned long *,
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unsigned long *, unsigned long *);
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extern void xor_niagara_5(unsigned long, unsigned long *, unsigned long *,
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unsigned long *, unsigned long *, unsigned long *);
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static struct xor_block_template xor_block_niagara = {
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.name = "Niagara",
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.do_2 = xor_niagara_2,
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.do_3 = xor_niagara_3,
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.do_4 = xor_niagara_4,
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.do_5 = xor_niagara_5,
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};
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#undef XOR_TRY_TEMPLATES
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#define XOR_TRY_TEMPLATES \
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do { \
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xor_speed(&xor_block_VIS); \
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xor_speed(&xor_block_niagara); \
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} while (0)
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/* For VIS for everything except Niagara. */
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#define XOR_SELECT_TEMPLATE(FASTEST) \
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((tlb_type == hypervisor && \
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(sun4v_chip_type == SUN4V_CHIP_NIAGARA1 || \
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sun4v_chip_type == SUN4V_CHIP_NIAGARA2 || \
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sun4v_chip_type == SUN4V_CHIP_NIAGARA3)) ? \
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&xor_block_niagara : \
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&xor_block_VIS)
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