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f6b3b7a9fa
write{b,w,l,q}_relaxed are implemented by some architectures in order to permit memory-mapped I/O accesses with weaker barrier semantics than the non-relaxed variants. This patch adds dummy macros for the write accessors to ia64, which may be able to be optimised in a similar manner to the relaxed read accessors at a later date. Cc: Tony Luck <tony.luck@intel.com> Signed-off-by: Will Deacon <will.deacon@arm.com> |
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uapi/asm |