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f6f52baf26
Impact: cleanup Most subarchitectures want to disable the APIC ESR (Error Status Register), because they generally have hardware hacks that wrap standard CPUs into a bigger system and hence the APIC bus is quite non-standard and weirdnesses (lockups) have been seen with ESR reporting. Remove the esr_disable macros and put the desired flag into each subarchitecture's genapic template directly. Signed-off-by: Ingo Molnar <mingo@elte.hu> |
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alpha | ||
arm | ||
avr32 | ||
blackfin | ||
cris | ||
frv | ||
h8300 | ||
ia64 | ||
m32r | ||
m68k | ||
m68knommu | ||
mips | ||
mn10300 | ||
parisc | ||
powerpc | ||
s390 | ||
sh | ||
sparc | ||
um | ||
x86 | ||
xtensa | ||
.gitignore | ||
Kconfig |