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05e152c76a
OMAP5430 is Texas Instrument's SOC based on ARM Cortex-A15 SMP architecture. It's a dual core SOC with GIC used for interrupt handling and with an integrated L2 cache controller. OMAP5432 is another variant of OMAP5430, with a memory controller supporting DDR3 and SATA. Patch includes: - The machine specific headers and sources updates. - Platform header updates. - Minimum initialisation support for serial. - IO table init Signed-off-by: R Sricharan <r.sricharan@ti.com> Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
33 lines
1.0 KiB
C
33 lines
1.0 KiB
C
/*:
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* Address mappings and base address for OMAP5 interconnects
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* and peripherals.
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*
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* Copyright (C) 2012 Texas Instruments
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* Santosh Shilimkar <santosh.shilimkar@ti.com>
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* Sricharan <r.sricharan@ti.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#ifndef __ASM_SOC_OMAP54XX_H
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#define __ASM_SOC_OMAP54XX_H
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/*
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* Please place only base defines here and put the rest in device
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* specific headers.
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*/
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#define L4_54XX_BASE 0x4a000000
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#define L4_WK_54XX_BASE 0x4ae00000
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#define L4_PER_54XX_BASE 0x48000000
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#define L3_54XX_BASE 0x44000000
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#define OMAP54XX_32KSYNCT_BASE 0x4ae04000
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#define OMAP54XX_CM_CORE_AON_BASE 0x4a004000
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#define OMAP54XX_CM_CORE_BASE 0x4a008000
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#define OMAP54XX_PRM_BASE 0x4ae06000
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#define OMAP54XX_PRCM_MPU_BASE 0x48243000
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#define OMAP54XX_SCM_BASE 0x4a002000
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#define OMAP54XX_CTRL_BASE 0x4a002800
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#endif /* __ASM_SOC_OMAP555554XX_H */
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