Jianqun fc69ed70c1 clk: rockchip: rk3288: i2s_frac adds flag to set parent's rate ... The relation of i2s nodes as follows: i2s_src 0 0 594000000 0 i2s_frac 0 0 11289600 0 i2s_pre 0 0 11289600 0 sclk_i2s0 0 0 11289600 0 i2s0_clkout 0 0 11289600 0 hclk_i2s0 1 1 99000000 0 sclk_i2s0 is the master clock, when to set rate of sclk_i2s0, should allow to set its parent's rate, by add flag CLK_SET_RATE_PARENT for "i2s_frac", "i2s_pre", "i2s0_clkout" and "sclk_i2s0". Tested on rk3288 board using max98090, with command "aplay <music.wav>" Change-Id: I12faad082566532b65a7de8c0a6845e1c17870e6 Signed-off-by: Jianqun <jay.xu@rock-chips.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>		2014-10-01 10:55:13 +02:00
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clk-cpu.c	clk: rockchip: add new clock-type for the cpuclk	2014-09-27 17:57:41 +02:00
clk-pll.c	clk: rockchip: change pll rate without a clk-notifier	2014-09-27 17:57:04 +02:00
clk-rk3188.c	clk: rockchip: switch to using the new cpuclk type for armclk	2014-09-27 17:57:46 +02:00
clk-rk3288.c	clk: rockchip: rk3288: i2s_frac adds flag to set parent's rate	2014-10-01 10:55:13 +02:00
clk-rockchip.c
clk.c	clk: rockchip: add new clock-type for the cpuclk	2014-09-27 17:57:41 +02:00
clk.h	clk: rockchip: add new clock-type for the cpuclk	2014-09-27 17:57:41 +02:00
Makefile	clk: rockchip: add new clock-type for the cpuclk	2014-09-27 17:57:41 +02:00
softrst.c	clk: rockchip: add reset controller	2014-07-13 12:17:07 -07:00