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Every architecture using the GIC has a gic_cpu_base_addr pointer for GIC 0 for their entry assembly code to use to decode the cause of the current interrupt. Move this into the common GIC code. Reviewed-by: Catalin Marinas <catalin.marinas@arm.com> Tested-by: Abhijeet Dharmapurikar <adharmap@codeaurora.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
33 lines
826 B
C
33 lines
826 B
C
/*
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* omap4-common.h: OMAP4 specific common header file
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*
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* Copyright (C) 2010 Texas Instruments, Inc.
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*
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* Author:
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* Santosh Shilimkar <santosh.shilimkar@ti.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#ifndef OMAP_ARCH_OMAP4_COMMON_H
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#define OMAP_ARCH_OMAP4_COMMON_H
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/*
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* wfi used in low power code. Directly opcode is used instead
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* of instruction to avoid mulit-omap build break
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*/
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#define do_wfi() \
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__asm__ __volatile__ (".word 0xe320f003" : : : "memory")
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#ifdef CONFIG_CACHE_L2X0
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extern void __iomem *l2cache_base;
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#endif
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extern void __iomem *gic_dist_base_addr;
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extern void __init gic_init_irq(void);
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extern void omap_smc1(u32 fn, u32 arg);
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#endif
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