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Introduce architecture specific guards for the simulator

Browse Source 
This patch makes the VIXL_INCLUDE_SIMULATOR and
VIXL_GENERATE_SIMULATOR_CODE header guards specific to either AArch64 or
AArch32. Even though the simulator only support AArch64. The build
system was updated accordingly, the "simulator" variable now takes
"aarch64" or "none" as possible values instead of "on" and "off".

This fixes issues we have when we want to build VIXL natively on
AArch64 without a simulator, but still include the AArch32
macro-assembler. The later would check for VIXL_GENERATE_SIMULATOR_CODE
and then generate calls to native code, which breaks.

Change-Id: I2850782558d4cc37f37c1644f0efbd70a3123057
This commit is contained in:
Pierre Langlois 2016-08-05 14:20:36 +01:00 committed by Alexandre Rames
parent 3e1b899f48
commit 1e85b7f2e8
86 changed files with 397 additions and 390 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
.ycm_extra_conf.py
View File

@ -27,7 +27,7 @@ flags = [
]
if platform.machine() != 'aarch64':
flags.append('-DVIXL_INCLUDE_SIMULATOR')
flags.append('-DVIXL_INCLUDE_SIMULATOR_AARCH64')
def FlagsForFile(filename, **kwargs):

2
SConstruct
View File

@ -93,7 +93,7 @@ options = {
'CCFLAGS' : ['-O3'],
},
'simulator:on' : {
'CCFLAGS' : ['-DVIXL_INCLUDE_SIMULATOR'],
'CCFLAGS' : ['-DVIXL_INCLUDE_SIMULATOR_AARCH64'],
},
'symbols:on' : {
'CCFLAGS' : ['-g'],

2
examples/aarch32/abs.cc
View File

@ -48,7 +48,7 @@ int main() {
masm.Bind(&abs);
GenerateAbs(&masm);
masm.FinalizeCode();
#ifdef VIXL_INCLUDE_SIMULATOR
#ifdef VIXL_INCLUDE_SIMULATOR_AARCH32
// There is no simulator defined for VIXL AArch32.
printf("This example cannot be simulated\n");
#else

4
examples/aarch32/examples.h
View File

@ -29,7 +29,7 @@
extern "C" {
#include <stdint.h>
#ifndef VIXL_INCLUDE_SIMULATOR
#ifndef VIXL_INCLUDE_SIMULATOR_AARCH32
#include <sys/mman.h>
#endif
}
@ -44,7 +44,7 @@ extern "C" {
using namespace vixl;
using namespace vixl::aarch32;
#ifndef VIXL_INCLUDE_SIMULATOR
#ifndef VIXL_INCLUDE_SIMULATOR_AARCH32
class ExecutableMemory {
public:
ExecutableMemory(const byte* code_start, size_t size)

2
examples/aarch32/getting-started.cc
View File

@ -50,7 +50,7 @@ int main() {
// Ensure that everything is generated and that the generated buffer is
// ready to use.
masm.FinalizeCode();
#ifdef VIXL_INCLUDE_SIMULATOR
#ifdef VIXL_INCLUDE_SIMULATOR_AARCH32
// There is no simulator defined for VIXL AArch32.
#else
byte* code = masm.GetBuffer().GetBuffer();

2
examples/aarch32/pi.cc
View File

@ -87,7 +87,7 @@ int main() {
masm.Bind(&pi_approx);
GenerateApproximatePi(&masm);
masm.FinalizeCode();
#ifdef VIXL_INCLUDE_SIMULATOR
#ifdef VIXL_INCLUDE_SIMULATOR_AARCH32
// There is no simulator defined for VIXL AArch32.
printf("This example cannot be simulated\n");
#else

2
examples/aarch32/switch.cc
View File

@ -81,7 +81,7 @@ int main() {
masm.Bind(&entry_point);
GenerateGradeComment(&masm);
masm.FinalizeCode();
#ifdef VIXL_INCLUDE_SIMULATOR
#ifdef VIXL_INCLUDE_SIMULATOR_AARCH32
// There is no simulator defined for VIXL AArch32.
printf("This example cannot be simulated\n");
#else

4
examples/aarch64/abs.cc
View File

@ -42,7 +42,7 @@ void GenerateAbs(MacroAssembler* masm) {
#ifndef TEST_EXAMPLES
#ifdef VIXL_INCLUDE_SIMULATOR
#ifdef VIXL_INCLUDE_SIMULATOR_AARCH64
int main(void) {
MacroAssembler masm;
Decoder decoder;
@ -67,5 +67,5 @@ int main(void) {
#else
// Without the simulator there is nothing to test.
int main(void) { return 0; }
#endif // VIXL_INCLUDE_SIMULATOR
#endif // VIXL_INCLUDE_SIMULATOR_AARCH64
#endif // TEST_EXAMPLES

4
examples/aarch64/add2-vectors.cc
View File

@ -123,7 +123,7 @@ int main(void) {
vecC[i] = vecA[i] + vecB[i];
}
#ifdef VIXL_INCLUDE_SIMULATOR
#ifdef VIXL_INCLUDE_SIMULATOR_AARCH64
uintptr_t vecA_addr = reinterpret_cast<uintptr_t>(vecA);
uintptr_t vecB_addr = reinterpret_cast<uintptr_t>(vecB);
@ -145,7 +145,7 @@ int main(void) {
// Placeholder to run test natively.
printf("Running tests natively is not supported yet.\n");
return 0;
#endif // VIXL_INCLUDE_SIMULATOR
#endif // VIXL_INCLUDE_SIMULATOR_AARCH64
// Check that the computed value in NEON matches the C version.
for (unsigned i = 0; i < ARRAY_SIZE(vecA); i++) {
assert(vecC[i] == vecA[i]);

4
examples/aarch64/add3-double.cc
View File

@ -43,7 +43,7 @@ void GenerateAdd3Double(MacroAssembler* masm) {
#ifndef TEST_EXAMPLES
#ifdef VIXL_INCLUDE_SIMULATOR
#ifdef VIXL_INCLUDE_SIMULATOR_AARCH64
int main(void) {
MacroAssembler masm;
Decoder decoder;
@ -70,5 +70,5 @@ int main(void) {
#else
// Without the simulator there is nothing to test.
int main(void) { return 0; }
#endif // VIXL_INCLUDE_SIMULATOR
#endif // VIXL_INCLUDE_SIMULATOR_AARCH64
#endif // TEST_EXAMPLES

4
examples/aarch64/add4-double.cc
View File

@ -51,7 +51,7 @@ void GenerateAdd4Double(MacroAssembler* masm) {
#ifndef TEST_EXAMPLES
#ifdef VIXL_INCLUDE_SIMULATOR
#ifdef VIXL_INCLUDE_SIMULATOR_AARCH64
int main(void) {
MacroAssembler masm;
Decoder decoder;
@ -83,5 +83,5 @@ int main(void) {
#else
// Without the simulator there is nothing to test.
int main(void) { return 0; }
#endif // VIXL_INCLUDE_SIMULATOR
#endif // VIXL_INCLUDE_SIMULATOR_AARCH64
#endif // TEST_EXAMPLES

4
examples/aarch64/check-bounds.cc
View File

@ -57,7 +57,7 @@ void GenerateCheckBounds(MacroAssembler* masm) {
#ifndef TEST_EXAMPLES
#ifdef VIXL_INCLUDE_SIMULATOR
#ifdef VIXL_INCLUDE_SIMULATOR_AARCH64
void run_function(Simulator* simulator,
Instruction* function,
uint64_t value,
@ -99,5 +99,5 @@ int main(void) {
#else
// Without the simulator there is nothing to test.
int main(void) { return 0; }
#endif // VIXL_INCLUDE_SIMULATOR
#endif // VIXL_INCLUDE_SIMULATOR_AARCH64
#endif // TEST_EXAMPLES

4
examples/aarch64/crc-checksums.cc
View File

@ -74,7 +74,7 @@ void runExample(const char* msg) {
GenerateCrc32(&masm);
masm.FinalizeCode();
#ifdef VIXL_INCLUDE_SIMULATOR
#ifdef VIXL_INCLUDE_SIMULATOR_AARCH64
// Run example function in the simulator.
uintptr_t msg_addr = reinterpret_cast<uintptr_t>(msg);
size_t msg_size = strlen(msg);
@ -88,7 +88,7 @@ void runExample(const char* msg) {
// Run example function natively.
printf("Not yet implemented.\n");
USE(msg);
#endif // VIXL_INCLUDE_SIMULATOR
#endif // VIXL_INCLUDE_SIMULATOR_AARCH64
}

4
examples/aarch64/debugger.cc
View File

@ -48,7 +48,7 @@ void GenerateBreak(MacroAssembler* masm) {
}
#ifdef VIXL_INCLUDE_SIMULATOR
#ifdef VIXL_INCLUDE_SIMULATOR_AARCH64
int main(void) {
MacroAssembler masm;
Decoder decoder;
@ -69,5 +69,5 @@ int main(void) {
#else
// Without the simulator there is nothing to test.
int main(void) { return 0; }
#endif // VIXL_INCLUDE_SIMULATOR
#endif // VIXL_INCLUDE_SIMULATOR_AARCH64
#endif // TEST_EXAMPLES

4
examples/aarch64/factorial-rec.cc
View File

@ -54,7 +54,7 @@ void GenerateFactorialRec(MacroAssembler* masm) {
#ifndef TEST_EXAMPLES
#ifdef VIXL_INCLUDE_SIMULATOR
#ifdef VIXL_INCLUDE_SIMULATOR_AARCH64
int main(void) {
MacroAssembler masm;
Decoder decoder;
@ -79,5 +79,5 @@ int main(void) {
#else
// Without the simulator there is nothing to test.
int main(void) { return 0; }
#endif // VIXL_INCLUDE_SIMULATOR
#endif // VIXL_INCLUDE_SIMULATOR_AARCH64
#endif // TEST_EXAMPLES

4
examples/aarch64/factorial.cc
View File

@ -52,7 +52,7 @@ void GenerateFactorial(MacroAssembler* masm) {
#ifndef TEST_EXAMPLES
#ifdef VIXL_INCLUDE_SIMULATOR
#ifdef VIXL_INCLUDE_SIMULATOR_AARCH64
int main(void) {
MacroAssembler masm;
Decoder decoder;
@ -77,5 +77,5 @@ int main(void) {
#else
// Without the simulator there is nothing to test.
int main(void) { return 0; }
#endif // VIXL_INCLUDE_SIMULATOR
#endif // VIXL_INCLUDE_SIMULATOR_AARCH64
#endif // TEST_EXAMPLES

4
examples/aarch64/getting-started.cc
View File

@ -40,7 +40,7 @@ void GenerateDemoFunction(MacroAssembler *masm) {
#ifndef TEST_EXAMPLES
#ifdef VIXL_INCLUDE_SIMULATOR
#ifdef VIXL_INCLUDE_SIMULATOR_AARCH64
int main() {
MacroAssembler masm;
Decoder decoder;
@ -60,5 +60,5 @@ int main() {
#else
// Without the simulator there is nothing to test.
int main(void) { return 0; }
#endif // VIXL_INCLUDE_SIMULATOR
#endif // VIXL_INCLUDE_SIMULATOR_AARCH64
#endif // TEST_EXAMPLES

6
examples/aarch64/literal.cc
View File

@ -28,7 +28,7 @@
#define __ masm.
#ifdef VIXL_INCLUDE_SIMULATOR
#ifdef VIXL_INCLUDE_SIMULATOR_AARCH64
int64_t LiteralExample(int64_t a, int64_t b) {
// Create and initialize the macro-assembler and the simulator.
MacroAssembler masm;
@ -87,7 +87,7 @@ int64_t LiteralExample(int64_t a, int64_t b) {
#endif
#ifndef TEST_EXAMPLES
#ifdef VIXL_INCLUDE_SIMULATOR
#ifdef VIXL_INCLUDE_SIMULATOR_AARCH64
int main(void) {
VIXL_CHECK(LiteralExample(1, 2) == 3);
return 0;
@ -95,5 +95,5 @@ int main(void) {
#else
// Without the simulator there is nothing to test.
int main(void) { return 0; }
#endif // VIXL_INCLUDE_SIMULATOR
#endif // VIXL_INCLUDE_SIMULATOR_AARCH64
#endif // TEST_EXAMPLES

4
examples/aarch64/neon-matrix-multiply.cc
View File

@ -94,7 +94,7 @@ void GenerateNEONMatrixMultiply(MacroAssembler* masm) {
#ifndef TEST_EXAMPLES
#ifdef VIXL_INCLUDE_SIMULATOR
#ifdef VIXL_INCLUDE_SIMULATOR_AARCH64
int main(void) {
MacroAssembler masm;
Decoder decoder;
@ -197,5 +197,5 @@ int main(void) {
#else
// Without the simulator there is nothing to test.
int main(void) { return 0; }
#endif // VIXL_INCLUDE_SIMULATOR
#endif // VIXL_INCLUDE_SIMULATOR_AARCH64
#endif // TEST_EXAMPLES

6
examples/aarch64/non-const-visitor.cc
View File

@ -42,7 +42,7 @@ void GenerateNonConstVisitorTestCode(MacroAssembler* masm) {
int64_t RunNonConstVisitorTestGeneratedCode(const Instruction* start_instr) {
#ifdef VIXL_INCLUDE_SIMULATOR
#ifdef VIXL_INCLUDE_SIMULATOR_AARCH64
Decoder simulator_decoder;
Simulator simulator(&simulator_decoder);
@ -64,7 +64,7 @@ int64_t RunNonConstVisitorTestGeneratedCode(const Instruction* start_instr) {
#ifndef TEST_EXAMPLES
#ifdef VIXL_INCLUDE_SIMULATOR
#ifdef VIXL_INCLUDE_SIMULATOR_AARCH64
int main(void) {
MacroAssembler masm;
@ -107,7 +107,7 @@ int main(void) {
#else
// Without the simulator there is nothing to test.
int main(void) { return 0; }
#endif // VIXL_INCLUDE_SIMULATOR
#endif // VIXL_INCLUDE_SIMULATOR_AARCH64
#endif // TEST_EXAMPLES

4
examples/aarch64/simulated-runtime-calls.cc
View File

@ -77,7 +77,7 @@ void GenerateRuntimeCallExamples(MacroAssembler* masm) {
#ifndef TEST_EXAMPLES
#ifdef VIXL_INCLUDE_SIMULATOR
#ifdef VIXL_INCLUDE_SIMULATOR_AARCH64
int main(void) {
MacroAssembler masm;
@ -110,7 +110,7 @@ int main(void) {
#else
// TODO: Support running natively.
int main(void) { return 0; }
#endif // VIXL_INCLUDE_SIMULATOR
#endif // VIXL_INCLUDE_SIMULATOR_AARCH64
#endif // TEST_EXAMPLES
#else
#ifndef TEST_EXAMPLES

4
examples/aarch64/sum-array.cc
View File

@ -58,7 +58,7 @@ void GenerateSumArray(MacroAssembler* masm) {
#ifndef TEST_EXAMPLES
#ifdef VIXL_INCLUDE_SIMULATOR
#ifdef VIXL_INCLUDE_SIMULATOR_AARCH64
int main(void) {
MacroAssembler masm;
Decoder decoder;
@ -88,5 +88,5 @@ int main(void) {
#else
// Without the simulator there is nothing to test.
int main(void) { return 0; }
#endif // VIXL_INCLUDE_SIMULATOR
#endif // VIXL_INCLUDE_SIMULATOR_AARCH64
#endif // TEST_EXAMPLES

4
examples/aarch64/swap-int32.cc
View File

@ -60,7 +60,7 @@ void GenerateSwapInt32(MacroAssembler* masm) {
#ifndef TEST_EXAMPLES
#ifdef VIXL_INCLUDE_SIMULATOR
#ifdef VIXL_INCLUDE_SIMULATOR_AARCH64
int main(void) {
MacroAssembler masm;
Decoder decoder;
@ -97,5 +97,5 @@ int main(void) {
#else
// Without the simulator there is nothing to test.
int main(void) { return 0; }
#endif // VIXL_INCLUDE_SIMULATOR
#endif // VIXL_INCLUDE_SIMULATOR_AARCH64
#endif // TEST_EXAMPLES

4
examples/aarch64/swap4.cc
View File

@ -46,7 +46,7 @@ void GenerateSwap4(MacroAssembler* masm) {
#ifndef TEST_EXAMPLES
#ifdef VIXL_INCLUDE_SIMULATOR
#ifdef VIXL_INCLUDE_SIMULATOR_AARCH64
int main(void) {
MacroAssembler masm;
Decoder decoder;
@ -91,5 +91,5 @@ int main(void) {
#else
// Without the simulator there is nothing to test.
int main(void) { return 0; }
#endif // VIXL_INCLUDE_SIMULATOR
#endif // VIXL_INCLUDE_SIMULATOR_AARCH64
#endif // TEST_EXAMPLES

10
src/aarch32/assembler-aarch32.h
View File

@ -37,7 +37,6 @@ class Assembler : public Instructions {
InstructionSet isa_;
Condition first_condition_;
uint16_t it_mask_;
bool generate_for_simulator_;
bool has_32_dregs_;
protected:
@ -62,23 +61,17 @@ class Assembler : public Instructions {
public:
explicit Assembler(InstructionSet isa = A32)
: isa_(isa),
first_condition_(al),
it_mask_(0),
generate_for_simulator_(VIXL_GENERATE_SIMULATOR_CODE),
has_32_dregs_(true) {}
: isa_(isa), first_condition_(al), it_mask_(0), has_32_dregs_(true) {}
explicit Assembler(size_t size, InstructionSet isa = A32)
: isa_(isa),
first_condition_(al),
it_mask_(0),
generate_for_simulator_(VIXL_GENERATE_SIMULATOR_CODE),
has_32_dregs_(true),
buffer_(size) {}
Assembler(void* buffer, size_t size, InstructionSet isa = A32)
: isa_(isa),
first_condition_(al),
it_mask_(0),
generate_for_simulator_(VIXL_GENERATE_SIMULATOR_CODE),
has_32_dregs_(true),
buffer_(buffer, size) {}
virtual ~Assembler() {}
@ -107,7 +100,6 @@ class Assembler : public Instructions {
return ((it_mask_ == 0) && cond.Is(al)) || (it_mask_ == 0x8);
}
void CheckNotIT() { VIXL_ASSERT(it_mask_ == 0); }
bool GenerateForSimulator() const { return generate_for_simulator_; }
bool Has32DRegs() const { return has_32_dregs_; }
void SetHas32DRegs(bool has_32_dregs) { has_32_dregs_ = has_32_dregs; }

289
src/aarch32/macro-assembler-aarch32.cc
View File

@ -539,151 +539,152 @@ void MacroAssembler::Printf(const char* format,
CPURegister reg2,
CPURegister reg3,
CPURegister reg4) {
#if VIXL_GENERATE_SIMULATOR_CODE
PushRegister(reg4);
PushRegister(reg3);
PushRegister(reg2);
PushRegister(reg1);
Push(RegisterList(r0, r1));
Ldr(r0, format);
uint32_t args = (reg4.GetType() << 12) | (reg3.GetType() << 8) |
(reg2.GetType() << 4) | reg1.GetType();
Mov(r1, args);
Hvc(kPrintfCode);
Pop(RegisterList(r0, r1));
int size = reg4.GetRegSizeInBytes() + reg3.GetRegSizeInBytes() +
reg2.GetRegSizeInBytes() + reg1.GetRegSizeInBytes();
Drop(size);
#else
// Generate on a native platform => 32 bit environment.
// Preserve core registers r0-r3, r12, r14
const uint32_t saved_registers_mask =
kCallerSavedRegistersMask | (1 << r5.GetCode());
Push(RegisterList(saved_registers_mask));
// Push VFP registers.
Vpush(Untyped64, DRegisterList(d0, d7));
if (Has32DRegs()) Vpush(Untyped64, DRegisterList(d16, d31));
// Search one register which has been saved and which doesn't need to be
// printed.
RegisterList available_registers(kCallerSavedRegistersMask);
if (reg1.GetType() == CPURegister::kRRegister) {
available_registers.Remove(Register(reg1.GetCode()));
}
if (reg2.GetType() == CPURegister::kRRegister) {
available_registers.Remove(Register(reg2.GetCode()));
}
if (reg3.GetType() == CPURegister::kRRegister) {
available_registers.Remove(Register(reg3.GetCode()));
}
if (reg4.GetType() == CPURegister::kRRegister) {
available_registers.Remove(Register(reg4.GetCode()));
}
Register tmp = available_registers.GetFirstAvailableRegister();
VIXL_ASSERT(tmp.GetType() == CPURegister::kRRegister);
// Push the flags.
Mrs(tmp, APSR);
Push(tmp);
Vmrs(RegisterOrAPSR_nzcv(tmp.GetCode()), FPSCR);
Push(tmp);
// Push the registers to print on the stack.
PushRegister(reg4);
PushRegister(reg3);
PushRegister(reg2);
PushRegister(reg1);
int core_count = 1;
int vfp_count = 0;
uint32_t printf_type = 0;
// Pop the registers to print and store them into r1-r3 and/or d0-d3.
// Reg4 may stay into the stack if all the register to print are core
// registers.
PreparePrintfArgument(reg1, &core_count, &vfp_count, &printf_type);
PreparePrintfArgument(reg2, &core_count, &vfp_count, &printf_type);
PreparePrintfArgument(reg3, &core_count, &vfp_count, &printf_type);
PreparePrintfArgument(reg4, &core_count, &vfp_count, &printf_type);
// Ensure that the stack is aligned on 8 bytes.
And(r5, sp, 0x7);
if (core_count == 5) {
// One 32 bit argument (reg4) has been left on the stack => align the stack
// before the argument.
Pop(r0);
Sub(sp, sp, r5);
Push(r0);
if (generate_simulator_code_) {
PushRegister(reg4);
PushRegister(reg3);
PushRegister(reg2);
PushRegister(reg1);
Push(RegisterList(r0, r1));
Ldr(r0, format);
uint32_t args = (reg4.GetType() << 12) | (reg3.GetType() << 8) |
(reg2.GetType() << 4) | reg1.GetType();
Mov(r1, args);
Hvc(kPrintfCode);
Pop(RegisterList(r0, r1));
int size = reg4.GetRegSizeInBytes() + reg3.GetRegSizeInBytes() +
reg2.GetRegSizeInBytes() + reg1.GetRegSizeInBytes();
Drop(size);
} else {
Sub(sp, sp, r5);
// Generate on a native platform => 32 bit environment.
// Preserve core registers r0-r3, r12, r14
const uint32_t saved_registers_mask =
kCallerSavedRegistersMask | (1 << r5.GetCode());
Push(RegisterList(saved_registers_mask));
// Push VFP registers.
Vpush(Untyped64, DRegisterList(d0, d7));
if (Has32DRegs()) Vpush(Untyped64, DRegisterList(d16, d31));
// Search one register which has been saved and which doesn't need to be
// printed.
RegisterList available_registers(kCallerSavedRegistersMask);
if (reg1.GetType() == CPURegister::kRRegister) {
available_registers.Remove(Register(reg1.GetCode()));
}
if (reg2.GetType() == CPURegister::kRRegister) {
available_registers.Remove(Register(reg2.GetCode()));
}
if (reg3.GetType() == CPURegister::kRRegister) {
available_registers.Remove(Register(reg3.GetCode()));
}
if (reg4.GetType() == CPURegister::kRRegister) {
available_registers.Remove(Register(reg4.GetCode()));
}
Register tmp = available_registers.GetFirstAvailableRegister();
VIXL_ASSERT(tmp.GetType() == CPURegister::kRRegister);
// Push the flags.
Mrs(tmp, APSR);
Push(tmp);
Vmrs(RegisterOrAPSR_nzcv(tmp.GetCode()), FPSCR);
Push(tmp);
// Push the registers to print on the stack.
PushRegister(reg4);
PushRegister(reg3);
PushRegister(reg2);
PushRegister(reg1);
int core_count = 1;
int vfp_count = 0;
uint32_t printf_type = 0;
// Pop the registers to print and store them into r1-r3 and/or d0-d3.
// Reg4 may stay into the stack if all the register to print are core
// registers.
PreparePrintfArgument(reg1, &core_count, &vfp_count, &printf_type);
PreparePrintfArgument(reg2, &core_count, &vfp_count, &printf_type);
PreparePrintfArgument(reg3, &core_count, &vfp_count, &printf_type);
PreparePrintfArgument(reg4, &core_count, &vfp_count, &printf_type);
// Ensure that the stack is aligned on 8 bytes.
And(r5, sp, 0x7);
if (core_count == 5) {
// One 32 bit argument (reg4) has been left on the stack => align the
// stack
// before the argument.
Pop(r0);
Sub(sp, sp, r5);
Push(r0);
} else {
Sub(sp, sp, r5);
}
// Select the right trampoline depending on the arguments.
uintptr_t address;
switch (printf_type) {
case 0:
address = reinterpret_cast<uintptr_t>(PrintfTrampolineRRRR);
break;
case 1:
address = reinterpret_cast<uintptr_t>(PrintfTrampolineDRRR);
break;
case 2:
address = reinterpret_cast<uintptr_t>(PrintfTrampolineRDRR);
break;
case 3:
address = reinterpret_cast<uintptr_t>(PrintfTrampolineDDRR);
break;
case 4:
address = reinterpret_cast<uintptr_t>(PrintfTrampolineRRDR);
break;
case 5:
address = reinterpret_cast<uintptr_t>(PrintfTrampolineDRDR);
break;
case 6:
address = reinterpret_cast<uintptr_t>(PrintfTrampolineRDDR);
break;
case 7:
address = reinterpret_cast<uintptr_t>(PrintfTrampolineDDDR);
break;
case 8:
address = reinterpret_cast<uintptr_t>(PrintfTrampolineRRRD);
break;
case 9:
address = reinterpret_cast<uintptr_t>(PrintfTrampolineDRRD);
break;
case 10:
address = reinterpret_cast<uintptr_t>(PrintfTrampolineRDRD);
break;
case 11:
address = reinterpret_cast<uintptr_t>(PrintfTrampolineDDRD);
break;
case 12:
address = reinterpret_cast<uintptr_t>(PrintfTrampolineRRDD);
break;
case 13:
address = reinterpret_cast<uintptr_t>(PrintfTrampolineDRDD);
break;
case 14:
address = reinterpret_cast<uintptr_t>(PrintfTrampolineRDDD);
break;
case 15:
address = reinterpret_cast<uintptr_t>(PrintfTrampolineDDDD);
break;
default:
VIXL_UNREACHABLE();
address = reinterpret_cast<uintptr_t>(PrintfTrampolineRRRR);
break;
}
Ldr(r0, format);
Mov(ip, address);
Blx(ip);
// If register reg4 was left on the stack => skip it.
if (core_count == 5) Drop(kRegSizeInBytes);
// Restore the stack as it was before alignment.
Add(sp, sp, r5);
// Restore the flags.
Pop(tmp);
Vmsr(FPSCR, tmp);
Pop(tmp);
Msr(APSR_nzcvqg, tmp);
// Restore the regsisters.
if (Has32DRegs()) Vpop(Untyped64, DRegisterList(d16, d31));
Vpop(Untyped64, DRegisterList(d0, d7));
Pop(RegisterList(saved_registers_mask));
}
// Select the right trampoline depending on the arguments.
uintptr_t address;
switch (printf_type) {
case 0:
address = reinterpret_cast<uintptr_t>(PrintfTrampolineRRRR);
break;
case 1:
address = reinterpret_cast<uintptr_t>(PrintfTrampolineDRRR);
break;
case 2:
address = reinterpret_cast<uintptr_t>(PrintfTrampolineRDRR);
break;
case 3:
address = reinterpret_cast<uintptr_t>(PrintfTrampolineDDRR);
break;
case 4:
address = reinterpret_cast<uintptr_t>(PrintfTrampolineRRDR);
break;
case 5:
address = reinterpret_cast<uintptr_t>(PrintfTrampolineDRDR);
break;
case 6:
address = reinterpret_cast<uintptr_t>(PrintfTrampolineRDDR);
break;
case 7:
address = reinterpret_cast<uintptr_t>(PrintfTrampolineDDDR);
break;
case 8:
address = reinterpret_cast<uintptr_t>(PrintfTrampolineRRRD);
break;
case 9:
address = reinterpret_cast<uintptr_t>(PrintfTrampolineDRRD);
break;
case 10:
address = reinterpret_cast<uintptr_t>(PrintfTrampolineRDRD);
break;
case 11:
address = reinterpret_cast<uintptr_t>(PrintfTrampolineDDRD);
break;
case 12:
address = reinterpret_cast<uintptr_t>(PrintfTrampolineRRDD);
break;
case 13:
address = reinterpret_cast<uintptr_t>(PrintfTrampolineDRDD);
break;
case 14:
address = reinterpret_cast<uintptr_t>(PrintfTrampolineRDDD);
break;
case 15:
address = reinterpret_cast<uintptr_t>(PrintfTrampolineDDDD);
break;
default:
VIXL_UNREACHABLE();
address = reinterpret_cast<uintptr_t>(PrintfTrampolineRRRR);
break;
}
Ldr(r0, format);
Mov(ip, address);
Blx(ip);
// If register reg4 was left on the stack => skip it.
if (core_count == 5) Drop(kRegSizeInBytes);
// Restore the stack as it was before alignment.
Add(sp, sp, r5);
// Restore the flags.
Pop(tmp);
Vmsr(FPSCR, tmp);
Pop(tmp);
Msr(APSR_nzcvqg, tmp);
// Restore the regsisters.
if (Has32DRegs()) Vpop(Untyped64, DRegisterList(d16, d31));
Vpop(Untyped64, DRegisterList(d0, d7));
Pop(RegisterList(saved_registers_mask));
#endif
}
@ -707,7 +708,6 @@ void MacroAssembler::PushRegister(CPURegister reg) {
}
#if !VIXL_GENERATE_SIMULATOR_CODE
void MacroAssembler::PreparePrintfArgument(CPURegister reg,
int* core_count,
int* vfp_count,
@ -738,7 +738,6 @@ void MacroAssembler::PreparePrintfArgument(CPURegister reg,
break;
}
}
#endif
void MacroAssembler::Delegate(InstructionType type,

14
src/aarch32/macro-assembler-aarch32.h
View File

@ -368,7 +368,8 @@ class MacroAssembler : public Assembler {
available_(r12),
checkpoint_(Label::kMaxOffset),
literal_pool_manager_(this),
veneer_pool_manager_(this) {
veneer_pool_manager_(this),
generate_simulator_code_(VIXL_AARCH32_GENERATE_SIMULATOR_CODE) {
#ifdef VIXL_DEBUG
SetAllowMacroInstructions(true);
#else
@ -382,7 +383,8 @@ class MacroAssembler : public Assembler {
available_(r12),
checkpoint_(Label::kMaxOffset),
literal_pool_manager_(this),
veneer_pool_manager_(this) {
veneer_pool_manager_(this),
generate_simulator_code_(VIXL_AARCH32_GENERATE_SIMULATOR_CODE) {
#ifdef VIXL_DEBUG
SetAllowMacroInstructions(true);
#endif
@ -393,13 +395,16 @@ class MacroAssembler : public Assembler {
available_(r12),
checkpoint_(Label::kMaxOffset),
literal_pool_manager_(this),
veneer_pool_manager_(this) {
veneer_pool_manager_(this),
generate_simulator_code_(VIXL_AARCH32_GENERATE_SIMULATOR_CODE) {
#ifdef VIXL_DEBUG
SetAllowMacroInstructions(true);
#endif
ComputeCheckpoint();
}
bool GenerateSimulatorCode() const { return generate_simulator_code_; }
#ifdef VIXL_DEBUG
// Tell whether any of the macro instruction can be used. When false the
// MacroAssembler will assert if a method which can emit a variable number
@ -604,12 +609,10 @@ class MacroAssembler : public Assembler {
CPURegister reg4 = NoReg);
// Functions used by Printf for generation.
void PushRegister(CPURegister reg);
#if !VIXL_GENERATE_SIMULATOR_CODE
void PreparePrintfArgument(CPURegister reg,
int* core_count,
int* vfp_count,
uint32_t* printf_type);
#endif
// Handlers for cases not handled by the assembler.
virtual void Delegate(InstructionType type,
InstructionCondROp instruction,
@ -8091,6 +8094,7 @@ class MacroAssembler : public Assembler {
Label::Offset checkpoint_;
LiteralPoolManager literal_pool_manager_;
VeneerPoolManager veneer_pool_manager_;
bool generate_simulator_code_;
bool allow_macro_instructions_;
};

4
src/aarch64/debugger-aarch64.cc
View File

@ -24,7 +24,7 @@
// NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
// EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
#ifdef VIXL_INCLUDE_SIMULATOR
#ifdef VIXL_INCLUDE_SIMULATOR_AARCH64
#include "aarch64/debugger-aarch64.h"
@ -1625,4 +1625,4 @@ bool InvalidCommand::Run(Debugger* debugger) {
} // namespace aarch64
} // namespace vixl
#endif // VIXL_INCLUDE_SIMULATOR
#endif // VIXL_INCLUDE_SIMULATOR_AARCH64

4
src/aarch64/debugger-aarch64.h
View File

@ -24,7 +24,7 @@
// OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
#ifdef VIXL_INCLUDE_SIMULATOR
#ifdef VIXL_INCLUDE_SIMULATOR_AARCH64
#ifndef VIXL_AARCH64_DEBUGGER_AARCH64_H_
#define VIXL_AARCH64_DEBUGGER_AARCH64_H_
@ -106,4 +106,4 @@ class Debugger : public Simulator {
#endif // VIXL_AARCH64_DEBUGGER_AARCH64_H_
#endif // VIXL_INCLUDE_SIMULATOR
#endif // VIXL_INCLUDE_SIMULATOR_AARCH64

4
src/aarch64/logic-aarch64.cc
View File

@ -24,7 +24,7 @@
// OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
#ifdef VIXL_INCLUDE_SIMULATOR
#ifdef VIXL_INCLUDE_SIMULATOR_AARCH64
#include <cmath>
@ -4966,4 +4966,4 @@ LogicVRegister Simulator::ucvtf(VectorFormat vform,
} // namespace aarch64
} // namespace vixl
#endif // VIXL_INCLUDE_SIMULATOR
#endif // VIXL_INCLUDE_SIMULATOR_AARCH64

6
src/aarch64/macro-assembler-aarch64.cc
View File

@ -359,7 +359,7 @@ MacroAssembler::MacroAssembler(PositionIndependentCodeOption pic)
#ifdef VIXL_DEBUG
allow_macro_instructions_(true),
#endif
generate_simulator_code_(VIXL_GENERATE_SIMULATOR_CODE),
generate_simulator_code_(VIXL_AARCH64_GENERATE_SIMULATOR_CODE),
sp_(sp),
tmp_list_(ip0, ip1),
fptmp_list_(d31),
@ -379,7 +379,7 @@ MacroAssembler::MacroAssembler(size_t capacity,
#ifdef VIXL_DEBUG
allow_macro_instructions_(true),
#endif
generate_simulator_code_(VIXL_GENERATE_SIMULATOR_CODE),
generate_simulator_code_(VIXL_AARCH64_GENERATE_SIMULATOR_CODE),
sp_(sp),
tmp_list_(ip0, ip1),
fptmp_list_(d31),
@ -397,7 +397,7 @@ MacroAssembler::MacroAssembler(byte* buffer,
#ifdef VIXL_DEBUG
allow_macro_instructions_(true),
#endif
generate_simulator_code_(VIXL_GENERATE_SIMULATOR_CODE),
generate_simulator_code_(VIXL_AARCH64_GENERATE_SIMULATOR_CODE),
sp_(sp),
tmp_list_(ip0, ip1),
fptmp_list_(d31),

4
src/aarch64/simulator-aarch64.cc
View File

@ -24,7 +24,7 @@
// OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
#ifdef VIXL_INCLUDE_SIMULATOR
#ifdef VIXL_INCLUDE_SIMULATOR_AARCH64
#include <cstring>
#include <cmath>
@ -5340,4 +5340,4 @@ void Simulator::DoRuntimeCall(const Instruction* instr) {
} // namespace aarch64
} // namespace vixl
#endif // VIXL_INCLUDE_SIMULATOR
#endif // VIXL_INCLUDE_SIMULATOR_AARCH64

25
src/globals-vixl.h
View File

@ -175,19 +175,32 @@ inline void USE(const T1&, const T2&, const T3&, const T4&) {}
#define VIXL_DEBUG_NO_RETURN
#endif
#ifdef VIXL_INCLUDE_SIMULATOR
#ifndef VIXL_GENERATE_SIMULATOR_CODE
#define VIXL_GENERATE_SIMULATOR_CODE 1
#ifdef VIXL_INCLUDE_SIMULATOR_AARCH64
#ifndef VIXL_AARCH64_GENERATE_SIMULATOR_CODE
#define VIXL_AARCH64_GENERATE_SIMULATOR_CODE 1
#endif
#else
#ifndef VIXL_GENERATE_SIMULATOR_CODE
#define VIXL_GENERATE_SIMULATOR_CODE 0
#ifndef VIXL_AARCH64_GENERATE_SIMULATOR_CODE
#define VIXL_AARCH64_GENERATE_SIMULATOR_CODE 0
#endif
#if VIXL_GENERATE_SIMULATOR_CODE
#if VIXL_AARCH64_GENERATE_SIMULATOR_CODE
#warning "Generating Simulator instructions without Simulator support."
#endif
#endif
// We do not have a simulator for AArch32, although we can pretend we do so that
// tests that require running natively can be skipped.
#ifndef __arm__
#define VIXL_INCLUDE_SIMULATOR_AARCH32
#ifndef VIXL_AARCH32_GENERATE_SIMULATOR_CODE
#define VIXL_AARCH32_GENERATE_SIMULATOR_CODE 1
#endif
#else
#ifndef VIXL_AARCH32_GENERATE_SIMULATOR_CODE
#define VIXL_AARCH32_GENERATE_SIMULATOR_CODE 0
#endif
#endif
#ifdef USE_SIMULATOR
#error "Please see the release notes for USE_SIMULATOR."
#endif

6
test/aarch32/config/template-simulator-aarch32.cc.in
View File

@ -43,7 +43,7 @@ ${do_not_edit_comment}
#define __ masm.
#define BUF_SIZE (4096)
#ifdef VIXL_INCLUDE_SIMULATOR
#ifdef VIXL_INCLUDE_SIMULATOR_AARCH32
// Run tests with the simulator.
#define SETUP() MacroAssembler masm(BUF_SIZE)
@ -59,7 +59,7 @@ ${do_not_edit_comment}
#define TEARDOWN()
#else // ifdef VIXL_INCLUDE_SIMULATOR.
#else // ifdef VIXL_INCLUDE_SIMULATOR_AARCH32.
#define SETUP() \
MacroAssembler masm(BUF_SIZE);
@ -104,7 +104,7 @@ ${do_not_edit_comment}
#define TEARDOWN()
#endif // ifdef VIXL_INCLUDE_SIMULATOR
#endif // ifdef VIXL_INCLUDE_SIMULATOR_AARCH32
namespace vixl {
namespace aarch32 {

8
test/aarch32/test-assembler-aarch32.cc
View File

@ -46,7 +46,7 @@ namespace aarch32 {
#define ASSERT_LITERAL_POOL_SIZE(size) \
do { assert(__ GetLiteralPoolSize() == size); } while (false)
#ifdef VIXL_INCLUDE_SIMULATOR
#ifdef VIXL_INCLUDE_SIMULATOR_AARCH32
// No simulator yet.
#define SETUP() \
@ -63,7 +63,7 @@ namespace aarch32 {
#define TEARDOWN()
#else // ifdef VIXL_INCLUDE_SIMULATOR.
#else // ifdef VIXL_INCLUDE_SIMULATOR_AARCH32.
#define SETUP() \
RegisterDump core; \
@ -112,13 +112,13 @@ namespace aarch32 {
#define TEARDOWN()
#endif // ifdef VIXL_INCLUDE_SIMULATOR
#endif // ifdef VIXL_INCLUDE_SIMULATOR_AARCH32
#define START_T32() \
__ UseT32(); \
START();
#ifdef VIXL_INCLUDE_SIMULATOR
#ifdef VIXL_INCLUDE_SIMULATOR_AARCH32
// No simulator yet. We can't test the results.
#define ASSERT_EQUAL_32(expected, result)

6
test/aarch32/test-simulator-cond-rd-memop-immediate-512-a32.cc
View File

@ -46,7 +46,7 @@
#define __ masm.
#define BUF_SIZE (4096)
#ifdef VIXL_INCLUDE_SIMULATOR
#ifdef VIXL_INCLUDE_SIMULATOR_AARCH32
// Run tests with the simulator.
#define SETUP() MacroAssembler masm(BUF_SIZE)
@ -62,7 +62,7 @@
#define TEARDOWN()
#else // ifdef VIXL_INCLUDE_SIMULATOR.
#else // ifdef VIXL_INCLUDE_SIMULATOR_AARCH32.
#define SETUP() MacroAssembler masm(BUF_SIZE);
@ -106,7 +106,7 @@
#define TEARDOWN()
#endif // ifdef VIXL_INCLUDE_SIMULATOR
#endif // ifdef VIXL_INCLUDE_SIMULATOR_AARCH32
namespace vixl {
namespace aarch32 {

6
test/aarch32/test-simulator-cond-rd-memop-immediate-8192-a32.cc
View File

@ -46,7 +46,7 @@
#define __ masm.
#define BUF_SIZE (4096)
#ifdef VIXL_INCLUDE_SIMULATOR
#ifdef VIXL_INCLUDE_SIMULATOR_AARCH32
// Run tests with the simulator.
#define SETUP() MacroAssembler masm(BUF_SIZE)
@ -62,7 +62,7 @@
#define TEARDOWN()
#else // ifdef VIXL_INCLUDE_SIMULATOR.
#else // ifdef VIXL_INCLUDE_SIMULATOR_AARCH32.
#define SETUP() MacroAssembler masm(BUF_SIZE);
@ -106,7 +106,7 @@
#define TEARDOWN()
#endif // ifdef VIXL_INCLUDE_SIMULATOR
#endif // ifdef VIXL_INCLUDE_SIMULATOR_AARCH32
namespace vixl {
namespace aarch32 {

6
test/aarch32/test-simulator-cond-rd-memop-rs-a32.cc
View File

@ -46,7 +46,7 @@
#define __ masm.
#define BUF_SIZE (4096)
#ifdef VIXL_INCLUDE_SIMULATOR
#ifdef VIXL_INCLUDE_SIMULATOR_AARCH32
// Run tests with the simulator.
#define SETUP() MacroAssembler masm(BUF_SIZE)
@ -62,7 +62,7 @@
#define TEARDOWN()
#else // ifdef VIXL_INCLUDE_SIMULATOR.
#else // ifdef VIXL_INCLUDE_SIMULATOR_AARCH32.
#define SETUP() MacroAssembler masm(BUF_SIZE);
@ -106,7 +106,7 @@
#define TEARDOWN()
#endif // ifdef VIXL_INCLUDE_SIMULATOR
#endif // ifdef VIXL_INCLUDE_SIMULATOR_AARCH32
namespace vixl {
namespace aarch32 {

6
test/aarch32/test-simulator-cond-rd-memop-rs-shift-amount-1to31-a32.cc
View File

@ -46,7 +46,7 @@
#define __ masm.
#define BUF_SIZE (4096)
#ifdef VIXL_INCLUDE_SIMULATOR
#ifdef VIXL_INCLUDE_SIMULATOR_AARCH32
// Run tests with the simulator.
#define SETUP() MacroAssembler masm(BUF_SIZE)
@ -62,7 +62,7 @@
#define TEARDOWN()
#else // ifdef VIXL_INCLUDE_SIMULATOR.
#else // ifdef VIXL_INCLUDE_SIMULATOR_AARCH32.
#define SETUP() MacroAssembler masm(BUF_SIZE);
@ -106,7 +106,7 @@
#define TEARDOWN()
#endif // ifdef VIXL_INCLUDE_SIMULATOR
#endif // ifdef VIXL_INCLUDE_SIMULATOR_AARCH32
namespace vixl {
namespace aarch32 {

6
test/aarch32/test-simulator-cond-rd-memop-rs-shift-amount-1to32-a32.cc
View File

@ -46,7 +46,7 @@
#define __ masm.
#define BUF_SIZE (4096)
#ifdef VIXL_INCLUDE_SIMULATOR
#ifdef VIXL_INCLUDE_SIMULATOR_AARCH32
// Run tests with the simulator.
#define SETUP() MacroAssembler masm(BUF_SIZE)
@ -62,7 +62,7 @@
#define TEARDOWN()
#else // ifdef VIXL_INCLUDE_SIMULATOR.
#else // ifdef VIXL_INCLUDE_SIMULATOR_AARCH32.
#define SETUP() MacroAssembler masm(BUF_SIZE);
@ -106,7 +106,7 @@
#define TEARDOWN()
#endif // ifdef VIXL_INCLUDE_SIMULATOR
#endif // ifdef VIXL_INCLUDE_SIMULATOR_AARCH32
namespace vixl {
namespace aarch32 {

6
test/aarch32/test-simulator-cond-rd-operand-const-a32.cc
View File

@ -46,7 +46,7 @@
#define __ masm.
#define BUF_SIZE (4096)
#ifdef VIXL_INCLUDE_SIMULATOR
#ifdef VIXL_INCLUDE_SIMULATOR_AARCH32
// Run tests with the simulator.
#define SETUP() MacroAssembler masm(BUF_SIZE)
@ -62,7 +62,7 @@
#define TEARDOWN()
#else // ifdef VIXL_INCLUDE_SIMULATOR.
#else // ifdef VIXL_INCLUDE_SIMULATOR_AARCH32.
#define SETUP() MacroAssembler masm(BUF_SIZE);
@ -106,7 +106,7 @@
#define TEARDOWN()
#endif // ifdef VIXL_INCLUDE_SIMULATOR
#endif // ifdef VIXL_INCLUDE_SIMULATOR_AARCH32
namespace vixl {
namespace aarch32 {

6
test/aarch32/test-simulator-cond-rd-operand-const-t32.cc
View File

@ -46,7 +46,7 @@
#define __ masm.
#define BUF_SIZE (4096)
#ifdef VIXL_INCLUDE_SIMULATOR
#ifdef VIXL_INCLUDE_SIMULATOR_AARCH32
// Run tests with the simulator.
#define SETUP() MacroAssembler masm(BUF_SIZE)
@ -62,7 +62,7 @@
#define TEARDOWN()
#else // ifdef VIXL_INCLUDE_SIMULATOR.
#else // ifdef VIXL_INCLUDE_SIMULATOR_AARCH32.
#define SETUP() MacroAssembler masm(BUF_SIZE);
@ -106,7 +106,7 @@
#define TEARDOWN()
#endif // ifdef VIXL_INCLUDE_SIMULATOR
#endif // ifdef VIXL_INCLUDE_SIMULATOR_AARCH32
namespace vixl {
namespace aarch32 {

6
test/aarch32/test-simulator-cond-rd-operand-imm16-t32.cc
View File

@ -46,7 +46,7 @@
#define __ masm.
#define BUF_SIZE (4096)
#ifdef VIXL_INCLUDE_SIMULATOR
#ifdef VIXL_INCLUDE_SIMULATOR_AARCH32
// Run tests with the simulator.
#define SETUP() MacroAssembler masm(BUF_SIZE)
@ -62,7 +62,7 @@
#define TEARDOWN()
#else // ifdef VIXL_INCLUDE_SIMULATOR.
#else // ifdef VIXL_INCLUDE_SIMULATOR_AARCH32.
#define SETUP() MacroAssembler masm(BUF_SIZE);
@ -106,7 +106,7 @@
#define TEARDOWN()
#endif // ifdef VIXL_INCLUDE_SIMULATOR
#endif // ifdef VIXL_INCLUDE_SIMULATOR_AARCH32
namespace vixl {
namespace aarch32 {

6
test/aarch32/test-simulator-cond-rd-operand-rn-a32.cc
View File

@ -46,7 +46,7 @@
#define __ masm.
#define BUF_SIZE (4096)
#ifdef VIXL_INCLUDE_SIMULATOR
#ifdef VIXL_INCLUDE_SIMULATOR_AARCH32
// Run tests with the simulator.
#define SETUP() MacroAssembler masm(BUF_SIZE)
@ -62,7 +62,7 @@
#define TEARDOWN()
#else // ifdef VIXL_INCLUDE_SIMULATOR.
#else // ifdef VIXL_INCLUDE_SIMULATOR_AARCH32.
#define SETUP() MacroAssembler masm(BUF_SIZE);
@ -106,7 +106,7 @@
#define TEARDOWN()
#endif // ifdef VIXL_INCLUDE_SIMULATOR
#endif // ifdef VIXL_INCLUDE_SIMULATOR_AARCH32
namespace vixl {
namespace aarch32 {

6
test/aarch32/test-simulator-cond-rd-operand-rn-ror-amount-a32.cc
View File

@ -46,7 +46,7 @@
#define __ masm.
#define BUF_SIZE (4096)
#ifdef VIXL_INCLUDE_SIMULATOR
#ifdef VIXL_INCLUDE_SIMULATOR_AARCH32
// Run tests with the simulator.
#define SETUP() MacroAssembler masm(BUF_SIZE)
@ -62,7 +62,7 @@
#define TEARDOWN()
#else // ifdef VIXL_INCLUDE_SIMULATOR.
#else // ifdef VIXL_INCLUDE_SIMULATOR_AARCH32.
#define SETUP() MacroAssembler masm(BUF_SIZE);
@ -106,7 +106,7 @@
#define TEARDOWN()
#endif // ifdef VIXL_INCLUDE_SIMULATOR
#endif // ifdef VIXL_INCLUDE_SIMULATOR_AARCH32
namespace vixl {
namespace aarch32 {

6
test/aarch32/test-simulator-cond-rd-operand-rn-ror-amount-t32.cc
View File

@ -46,7 +46,7 @@
#define __ masm.
#define BUF_SIZE (4096)
#ifdef VIXL_INCLUDE_SIMULATOR
#ifdef VIXL_INCLUDE_SIMULATOR_AARCH32
// Run tests with the simulator.
#define SETUP() MacroAssembler masm(BUF_SIZE)
@ -62,7 +62,7 @@
#define TEARDOWN()
#else // ifdef VIXL_INCLUDE_SIMULATOR.
#else // ifdef VIXL_INCLUDE_SIMULATOR_AARCH32.
#define SETUP() MacroAssembler masm(BUF_SIZE);
@ -106,7 +106,7 @@
#define TEARDOWN()
#endif // ifdef VIXL_INCLUDE_SIMULATOR
#endif // ifdef VIXL_INCLUDE_SIMULATOR_AARCH32
namespace vixl {
namespace aarch32 {

6
test/aarch32/test-simulator-cond-rd-operand-rn-shift-amount-1to31-a32.cc
View File

@ -46,7 +46,7 @@
#define __ masm.
#define BUF_SIZE (4096)
#ifdef VIXL_INCLUDE_SIMULATOR
#ifdef VIXL_INCLUDE_SIMULATOR_AARCH32
// Run tests with the simulator.
#define SETUP() MacroAssembler masm(BUF_SIZE)
@ -62,7 +62,7 @@
#define TEARDOWN()
#else // ifdef VIXL_INCLUDE_SIMULATOR.
#else // ifdef VIXL_INCLUDE_SIMULATOR_AARCH32.
#define SETUP() MacroAssembler masm(BUF_SIZE);
@ -106,7 +106,7 @@
#define TEARDOWN()
#endif // ifdef VIXL_INCLUDE_SIMULATOR
#endif // ifdef VIXL_INCLUDE_SIMULATOR_AARCH32
namespace vixl {
namespace aarch32 {

6
test/aarch32/test-simulator-cond-rd-operand-rn-shift-amount-1to31-t32.cc
View File

@ -46,7 +46,7 @@
#define __ masm.
#define BUF_SIZE (4096)
#ifdef VIXL_INCLUDE_SIMULATOR
#ifdef VIXL_INCLUDE_SIMULATOR_AARCH32
// Run tests with the simulator.
#define SETUP() MacroAssembler masm(BUF_SIZE)
@ -62,7 +62,7 @@
#define TEARDOWN()
#else // ifdef VIXL_INCLUDE_SIMULATOR.
#else // ifdef VIXL_INCLUDE_SIMULATOR_AARCH32.
#define SETUP() MacroAssembler masm(BUF_SIZE);
@ -106,7 +106,7 @@
#define TEARDOWN()
#endif // ifdef VIXL_INCLUDE_SIMULATOR
#endif // ifdef VIXL_INCLUDE_SIMULATOR_AARCH32
namespace vixl {
namespace aarch32 {

6
test/aarch32/test-simulator-cond-rd-operand-rn-shift-amount-1to32-a32.cc
View File

@ -46,7 +46,7 @@
#define __ masm.
#define BUF_SIZE (4096)
#ifdef VIXL_INCLUDE_SIMULATOR
#ifdef VIXL_INCLUDE_SIMULATOR_AARCH32
// Run tests with the simulator.
#define SETUP() MacroAssembler masm(BUF_SIZE)
@ -62,7 +62,7 @@
#define TEARDOWN()
#else // ifdef VIXL_INCLUDE_SIMULATOR.
#else // ifdef VIXL_INCLUDE_SIMULATOR_AARCH32.
#define SETUP() MacroAssembler masm(BUF_SIZE);
@ -106,7 +106,7 @@
#define TEARDOWN()
#endif // ifdef VIXL_INCLUDE_SIMULATOR
#endif // ifdef VIXL_INCLUDE_SIMULATOR_AARCH32
namespace vixl {
namespace aarch32 {

6
test/aarch32/test-simulator-cond-rd-operand-rn-shift-amount-1to32-t32.cc
View File

@ -46,7 +46,7 @@
#define __ masm.
#define BUF_SIZE (4096)
#ifdef VIXL_INCLUDE_SIMULATOR
#ifdef VIXL_INCLUDE_SIMULATOR_AARCH32
// Run tests with the simulator.
#define SETUP() MacroAssembler masm(BUF_SIZE)
@ -62,7 +62,7 @@
#define TEARDOWN()
#else // ifdef VIXL_INCLUDE_SIMULATOR.
#else // ifdef VIXL_INCLUDE_SIMULATOR_AARCH32.
#define SETUP() MacroAssembler masm(BUF_SIZE);
@ -106,7 +106,7 @@
#define TEARDOWN()
#endif // ifdef VIXL_INCLUDE_SIMULATOR
#endif // ifdef VIXL_INCLUDE_SIMULATOR_AARCH32
namespace vixl {
namespace aarch32 {

6
test/aarch32/test-simulator-cond-rd-operand-rn-shift-rs-a32.cc
View File

@ -46,7 +46,7 @@
#define __ masm.
#define BUF_SIZE (4096)
#ifdef VIXL_INCLUDE_SIMULATOR
#ifdef VIXL_INCLUDE_SIMULATOR_AARCH32
// Run tests with the simulator.
#define SETUP() MacroAssembler masm(BUF_SIZE)
@ -62,7 +62,7 @@
#define TEARDOWN()
#else // ifdef VIXL_INCLUDE_SIMULATOR.
#else // ifdef VIXL_INCLUDE_SIMULATOR_AARCH32.
#define SETUP() MacroAssembler masm(BUF_SIZE);
@ -106,7 +106,7 @@
#define TEARDOWN()
#endif // ifdef VIXL_INCLUDE_SIMULATOR
#endif // ifdef VIXL_INCLUDE_SIMULATOR_AARCH32
namespace vixl {
namespace aarch32 {

6
test/aarch32/test-simulator-cond-rd-operand-rn-shift-rs-t32.cc
View File

@ -46,7 +46,7 @@
#define __ masm.
#define BUF_SIZE (4096)
#ifdef VIXL_INCLUDE_SIMULATOR
#ifdef VIXL_INCLUDE_SIMULATOR_AARCH32
// Run tests with the simulator.
#define SETUP() MacroAssembler masm(BUF_SIZE)
@ -62,7 +62,7 @@
#define TEARDOWN()
#else // ifdef VIXL_INCLUDE_SIMULATOR.
#else // ifdef VIXL_INCLUDE_SIMULATOR_AARCH32.
#define SETUP() MacroAssembler masm(BUF_SIZE);
@ -106,7 +106,7 @@
#define TEARDOWN()
#endif // ifdef VIXL_INCLUDE_SIMULATOR
#endif // ifdef VIXL_INCLUDE_SIMULATOR_AARCH32
namespace vixl {
namespace aarch32 {

6
test/aarch32/test-simulator-cond-rd-operand-rn-t32.cc
View File

@ -46,7 +46,7 @@
#define __ masm.
#define BUF_SIZE (4096)
#ifdef VIXL_INCLUDE_SIMULATOR
#ifdef VIXL_INCLUDE_SIMULATOR_AARCH32
// Run tests with the simulator.
#define SETUP() MacroAssembler masm(BUF_SIZE)
@ -62,7 +62,7 @@
#define TEARDOWN()
#else // ifdef VIXL_INCLUDE_SIMULATOR.
#else // ifdef VIXL_INCLUDE_SIMULATOR_AARCH32.
#define SETUP() MacroAssembler masm(BUF_SIZE);
@ -106,7 +106,7 @@
#define TEARDOWN()
#endif // ifdef VIXL_INCLUDE_SIMULATOR
#endif // ifdef VIXL_INCLUDE_SIMULATOR_AARCH32
namespace vixl {
namespace aarch32 {

6
test/aarch32/test-simulator-cond-rd-rn-a32.cc
View File

@ -46,7 +46,7 @@
#define __ masm.
#define BUF_SIZE (4096)
#ifdef VIXL_INCLUDE_SIMULATOR
#ifdef VIXL_INCLUDE_SIMULATOR_AARCH32
// Run tests with the simulator.
#define SETUP() MacroAssembler masm(BUF_SIZE)
@ -62,7 +62,7 @@
#define TEARDOWN()
#else // ifdef VIXL_INCLUDE_SIMULATOR.
#else // ifdef VIXL_INCLUDE_SIMULATOR_AARCH32.
#define SETUP() MacroAssembler masm(BUF_SIZE);
@ -106,7 +106,7 @@
#define TEARDOWN()
#endif // ifdef VIXL_INCLUDE_SIMULATOR
#endif // ifdef VIXL_INCLUDE_SIMULATOR_AARCH32
namespace vixl {
namespace aarch32 {

6
test/aarch32/test-simulator-cond-rd-rn-operand-const-a32.cc
View File

@ -46,7 +46,7 @@
#define __ masm.
#define BUF_SIZE (4096)
#ifdef VIXL_INCLUDE_SIMULATOR
#ifdef VIXL_INCLUDE_SIMULATOR_AARCH32
// Run tests with the simulator.
#define SETUP() MacroAssembler masm(BUF_SIZE)
@ -62,7 +62,7 @@
#define TEARDOWN()
#else // ifdef VIXL_INCLUDE_SIMULATOR.
#else // ifdef VIXL_INCLUDE_SIMULATOR_AARCH32.
#define SETUP() MacroAssembler masm(BUF_SIZE);
@ -106,7 +106,7 @@
#define TEARDOWN()
#endif // ifdef VIXL_INCLUDE_SIMULATOR
#endif // ifdef VIXL_INCLUDE_SIMULATOR_AARCH32
namespace vixl {
namespace aarch32 {

6
test/aarch32/test-simulator-cond-rd-rn-operand-const-t32.cc
View File

@ -46,7 +46,7 @@
#define __ masm.
#define BUF_SIZE (4096)
#ifdef VIXL_INCLUDE_SIMULATOR
#ifdef VIXL_INCLUDE_SIMULATOR_AARCH32
// Run tests with the simulator.
#define SETUP() MacroAssembler masm(BUF_SIZE)
@ -62,7 +62,7 @@
#define TEARDOWN()
#else // ifdef VIXL_INCLUDE_SIMULATOR.
#else // ifdef VIXL_INCLUDE_SIMULATOR_AARCH32.
#define SETUP() MacroAssembler masm(BUF_SIZE);
@ -106,7 +106,7 @@
#define TEARDOWN()
#endif // ifdef VIXL_INCLUDE_SIMULATOR
#endif // ifdef VIXL_INCLUDE_SIMULATOR_AARCH32
namespace vixl {
namespace aarch32 {

6
test/aarch32/test-simulator-cond-rd-rn-operand-imm12-t32.cc
View File

@ -46,7 +46,7 @@
#define __ masm.
#define BUF_SIZE (4096)
#ifdef VIXL_INCLUDE_SIMULATOR
#ifdef VIXL_INCLUDE_SIMULATOR_AARCH32
// Run tests with the simulator.
#define SETUP() MacroAssembler masm(BUF_SIZE)
@ -62,7 +62,7 @@
#define TEARDOWN()
#else // ifdef VIXL_INCLUDE_SIMULATOR.
#else // ifdef VIXL_INCLUDE_SIMULATOR_AARCH32.
#define SETUP() MacroAssembler masm(BUF_SIZE);
@ -106,7 +106,7 @@
#define TEARDOWN()
#endif // ifdef VIXL_INCLUDE_SIMULATOR
#endif // ifdef VIXL_INCLUDE_SIMULATOR_AARCH32
namespace vixl {
namespace aarch32 {

6
test/aarch32/test-simulator-cond-rd-rn-operand-rm-a32.cc
View File

@ -46,7 +46,7 @@
#define __ masm.
#define BUF_SIZE (4096)
#ifdef VIXL_INCLUDE_SIMULATOR
#ifdef VIXL_INCLUDE_SIMULATOR_AARCH32
// Run tests with the simulator.
#define SETUP() MacroAssembler masm(BUF_SIZE)
@ -62,7 +62,7 @@
#define TEARDOWN()
#else // ifdef VIXL_INCLUDE_SIMULATOR.
#else // ifdef VIXL_INCLUDE_SIMULATOR_AARCH32.
#define SETUP() MacroAssembler masm(BUF_SIZE);
@ -106,7 +106,7 @@
#define TEARDOWN()
#endif // ifdef VIXL_INCLUDE_SIMULATOR
#endif // ifdef VIXL_INCLUDE_SIMULATOR_AARCH32
namespace vixl {
namespace aarch32 {

6
test/aarch32/test-simulator-cond-rd-rn-operand-rm-ror-amount-a32.cc
View File

@ -46,7 +46,7 @@
#define __ masm.
#define BUF_SIZE (4096)
#ifdef VIXL_INCLUDE_SIMULATOR
#ifdef VIXL_INCLUDE_SIMULATOR_AARCH32
// Run tests with the simulator.
#define SETUP() MacroAssembler masm(BUF_SIZE)
@ -62,7 +62,7 @@
#define TEARDOWN()
#else // ifdef VIXL_INCLUDE_SIMULATOR.
#else // ifdef VIXL_INCLUDE_SIMULATOR_AARCH32.
#define SETUP() MacroAssembler masm(BUF_SIZE);
@ -106,7 +106,7 @@
#define TEARDOWN()
#endif // ifdef VIXL_INCLUDE_SIMULATOR
#endif // ifdef VIXL_INCLUDE_SIMULATOR_AARCH32
namespace vixl {
namespace aarch32 {

6
test/aarch32/test-simulator-cond-rd-rn-operand-rm-ror-amount-t32.cc
View File

@ -46,7 +46,7 @@
#define __ masm.
#define BUF_SIZE (4096)
#ifdef VIXL_INCLUDE_SIMULATOR
#ifdef VIXL_INCLUDE_SIMULATOR_AARCH32
// Run tests with the simulator.
#define SETUP() MacroAssembler masm(BUF_SIZE)
@ -62,7 +62,7 @@
#define TEARDOWN()
#else // ifdef VIXL_INCLUDE_SIMULATOR.
#else // ifdef VIXL_INCLUDE_SIMULATOR_AARCH32.
#define SETUP() MacroAssembler masm(BUF_SIZE);
@ -106,7 +106,7 @@
#define TEARDOWN()
#endif // ifdef VIXL_INCLUDE_SIMULATOR
#endif // ifdef VIXL_INCLUDE_SIMULATOR_AARCH32
namespace vixl {
namespace aarch32 {

6
test/aarch32/test-simulator-cond-rd-rn-operand-rm-shift-amount-1to31-a32.cc
View File

@ -46,7 +46,7 @@
#define __ masm.
#define BUF_SIZE (4096)
#ifdef VIXL_INCLUDE_SIMULATOR
#ifdef VIXL_INCLUDE_SIMULATOR_AARCH32
// Run tests with the simulator.
#define SETUP() MacroAssembler masm(BUF_SIZE)
@ -62,7 +62,7 @@
#define TEARDOWN()
#else // ifdef VIXL_INCLUDE_SIMULATOR.
#else // ifdef VIXL_INCLUDE_SIMULATOR_AARCH32.
#define SETUP() MacroAssembler masm(BUF_SIZE);
@ -106,7 +106,7 @@
#define TEARDOWN()
#endif // ifdef VIXL_INCLUDE_SIMULATOR
#endif // ifdef VIXL_INCLUDE_SIMULATOR_AARCH32
namespace vixl {
namespace aarch32 {

6
test/aarch32/test-simulator-cond-rd-rn-operand-rm-shift-amount-1to31-t32.cc
View File

@ -46,7 +46,7 @@
#define __ masm.
#define BUF_SIZE (4096)
#ifdef VIXL_INCLUDE_SIMULATOR
#ifdef VIXL_INCLUDE_SIMULATOR_AARCH32
// Run tests with the simulator.
#define SETUP() MacroAssembler masm(BUF_SIZE)
@ -62,7 +62,7 @@
#define TEARDOWN()
#else // ifdef VIXL_INCLUDE_SIMULATOR.
#else // ifdef VIXL_INCLUDE_SIMULATOR_AARCH32.
#define SETUP() MacroAssembler masm(BUF_SIZE);
@ -106,7 +106,7 @@
#define TEARDOWN()
#endif // ifdef VIXL_INCLUDE_SIMULATOR
#endif // ifdef VIXL_INCLUDE_SIMULATOR_AARCH32
namespace vixl {
namespace aarch32 {

6
test/aarch32/test-simulator-cond-rd-rn-operand-rm-shift-amount-1to32-a32.cc
View File

@ -46,7 +46,7 @@
#define __ masm.
#define BUF_SIZE (4096)
#ifdef VIXL_INCLUDE_SIMULATOR
#ifdef VIXL_INCLUDE_SIMULATOR_AARCH32
// Run tests with the simulator.
#define SETUP() MacroAssembler masm(BUF_SIZE)
@ -62,7 +62,7 @@
#define TEARDOWN()
#else // ifdef VIXL_INCLUDE_SIMULATOR.
#else // ifdef VIXL_INCLUDE_SIMULATOR_AARCH32.
#define SETUP() MacroAssembler masm(BUF_SIZE);
@ -106,7 +106,7 @@
#define TEARDOWN()
#endif // ifdef VIXL_INCLUDE_SIMULATOR
#endif // ifdef VIXL_INCLUDE_SIMULATOR_AARCH32
namespace vixl {
namespace aarch32 {

6
test/aarch32/test-simulator-cond-rd-rn-operand-rm-shift-amount-1to32-t32.cc
View File

@ -46,7 +46,7 @@
#define __ masm.
#define BUF_SIZE (4096)
#ifdef VIXL_INCLUDE_SIMULATOR
#ifdef VIXL_INCLUDE_SIMULATOR_AARCH32
// Run tests with the simulator.
#define SETUP() MacroAssembler masm(BUF_SIZE)
@ -62,7 +62,7 @@
#define TEARDOWN()
#else // ifdef VIXL_INCLUDE_SIMULATOR.
#else // ifdef VIXL_INCLUDE_SIMULATOR_AARCH32.
#define SETUP() MacroAssembler masm(BUF_SIZE);
@ -106,7 +106,7 @@
#define TEARDOWN()
#endif // ifdef VIXL_INCLUDE_SIMULATOR
#endif // ifdef VIXL_INCLUDE_SIMULATOR_AARCH32
namespace vixl {
namespace aarch32 {

6
test/aarch32/test-simulator-cond-rd-rn-operand-rm-shift-rs-a32.cc
View File

@ -46,7 +46,7 @@
#define __ masm.
#define BUF_SIZE (4096)
#ifdef VIXL_INCLUDE_SIMULATOR
#ifdef VIXL_INCLUDE_SIMULATOR_AARCH32
// Run tests with the simulator.
#define SETUP() MacroAssembler masm(BUF_SIZE)
@ -62,7 +62,7 @@
#define TEARDOWN()
#else // ifdef VIXL_INCLUDE_SIMULATOR.
#else // ifdef VIXL_INCLUDE_SIMULATOR_AARCH32.
#define SETUP() MacroAssembler masm(BUF_SIZE);
@ -106,7 +106,7 @@
#define TEARDOWN()
#endif // ifdef VIXL_INCLUDE_SIMULATOR
#endif // ifdef VIXL_INCLUDE_SIMULATOR_AARCH32
namespace vixl {
namespace aarch32 {

6
test/aarch32/test-simulator-cond-rd-rn-operand-rm-t32.cc
View File

@ -46,7 +46,7 @@
#define __ masm.
#define BUF_SIZE (4096)
#ifdef VIXL_INCLUDE_SIMULATOR
#ifdef VIXL_INCLUDE_SIMULATOR_AARCH32
// Run tests with the simulator.
#define SETUP() MacroAssembler masm(BUF_SIZE)
@ -62,7 +62,7 @@
#define TEARDOWN()
#else // ifdef VIXL_INCLUDE_SIMULATOR.
#else // ifdef VIXL_INCLUDE_SIMULATOR_AARCH32.
#define SETUP() MacroAssembler masm(BUF_SIZE);
@ -106,7 +106,7 @@
#define TEARDOWN()
#endif // ifdef VIXL_INCLUDE_SIMULATOR
#endif // ifdef VIXL_INCLUDE_SIMULATOR_AARCH32
namespace vixl {
namespace aarch32 {

6
test/aarch32/test-simulator-cond-rd-rn-rm-a32-ge.cc
View File

@ -46,7 +46,7 @@
#define __ masm.
#define BUF_SIZE (4096)
#ifdef VIXL_INCLUDE_SIMULATOR
#ifdef VIXL_INCLUDE_SIMULATOR_AARCH32
// Run tests with the simulator.
#define SETUP() MacroAssembler masm(BUF_SIZE)
@ -62,7 +62,7 @@
#define TEARDOWN()
#else // ifdef VIXL_INCLUDE_SIMULATOR.
#else // ifdef VIXL_INCLUDE_SIMULATOR_AARCH32.
#define SETUP() MacroAssembler masm(BUF_SIZE);
@ -106,7 +106,7 @@
#define TEARDOWN()
#endif // ifdef VIXL_INCLUDE_SIMULATOR
#endif // ifdef VIXL_INCLUDE_SIMULATOR_AARCH32
namespace vixl {
namespace aarch32 {

6
test/aarch32/test-simulator-cond-rd-rn-rm-a32-q.cc
View File

@ -46,7 +46,7 @@
#define __ masm.
#define BUF_SIZE (4096)
#ifdef VIXL_INCLUDE_SIMULATOR
#ifdef VIXL_INCLUDE_SIMULATOR_AARCH32
// Run tests with the simulator.
#define SETUP() MacroAssembler masm(BUF_SIZE)
@ -62,7 +62,7 @@
#define TEARDOWN()
#else // ifdef VIXL_INCLUDE_SIMULATOR.
#else // ifdef VIXL_INCLUDE_SIMULATOR_AARCH32.
#define SETUP() MacroAssembler masm(BUF_SIZE);
@ -106,7 +106,7 @@
#define TEARDOWN()
#endif // ifdef VIXL_INCLUDE_SIMULATOR
#endif // ifdef VIXL_INCLUDE_SIMULATOR_AARCH32
namespace vixl {
namespace aarch32 {

6
test/aarch32/test-simulator-cond-rd-rn-rm-a32-sel.cc
View File

@ -46,7 +46,7 @@
#define __ masm.
#define BUF_SIZE (4096)
#ifdef VIXL_INCLUDE_SIMULATOR
#ifdef VIXL_INCLUDE_SIMULATOR_AARCH32
// Run tests with the simulator.
#define SETUP() MacroAssembler masm(BUF_SIZE)
@ -62,7 +62,7 @@
#define TEARDOWN()
#else // ifdef VIXL_INCLUDE_SIMULATOR.
#else // ifdef VIXL_INCLUDE_SIMULATOR_AARCH32.
#define SETUP() MacroAssembler masm(BUF_SIZE);
@ -106,7 +106,7 @@
#define TEARDOWN()
#endif // ifdef VIXL_INCLUDE_SIMULATOR
#endif // ifdef VIXL_INCLUDE_SIMULATOR_AARCH32
namespace vixl {
namespace aarch32 {

6
test/aarch32/test-simulator-cond-rd-rn-rm-a32.cc
View File

@ -46,7 +46,7 @@
#define __ masm.
#define BUF_SIZE (4096)
#ifdef VIXL_INCLUDE_SIMULATOR
#ifdef VIXL_INCLUDE_SIMULATOR_AARCH32
// Run tests with the simulator.
#define SETUP() MacroAssembler masm(BUF_SIZE)
@ -62,7 +62,7 @@
#define TEARDOWN()
#else // ifdef VIXL_INCLUDE_SIMULATOR.
#else // ifdef VIXL_INCLUDE_SIMULATOR_AARCH32.
#define SETUP() MacroAssembler masm(BUF_SIZE);
@ -106,7 +106,7 @@
#define TEARDOWN()
#endif // ifdef VIXL_INCLUDE_SIMULATOR
#endif // ifdef VIXL_INCLUDE_SIMULATOR_AARCH32
namespace vixl {
namespace aarch32 {

6
test/aarch32/test-simulator-cond-rd-rn-rm-t32-ge.cc
View File

@ -46,7 +46,7 @@
#define __ masm.
#define BUF_SIZE (4096)
#ifdef VIXL_INCLUDE_SIMULATOR
#ifdef VIXL_INCLUDE_SIMULATOR_AARCH32
// Run tests with the simulator.
#define SETUP() MacroAssembler masm(BUF_SIZE)
@ -62,7 +62,7 @@
#define TEARDOWN()
#else // ifdef VIXL_INCLUDE_SIMULATOR.
#else // ifdef VIXL_INCLUDE_SIMULATOR_AARCH32.
#define SETUP() MacroAssembler masm(BUF_SIZE);
@ -106,7 +106,7 @@
#define TEARDOWN()
#endif // ifdef VIXL_INCLUDE_SIMULATOR
#endif // ifdef VIXL_INCLUDE_SIMULATOR_AARCH32
namespace vixl {
namespace aarch32 {

6
test/aarch32/test-simulator-cond-rd-rn-rm-t32-q.cc
View File

@ -46,7 +46,7 @@
#define __ masm.
#define BUF_SIZE (4096)
#ifdef VIXL_INCLUDE_SIMULATOR
#ifdef VIXL_INCLUDE_SIMULATOR_AARCH32
// Run tests with the simulator.
#define SETUP() MacroAssembler masm(BUF_SIZE)
@ -62,7 +62,7 @@
#define TEARDOWN()
#else // ifdef VIXL_INCLUDE_SIMULATOR.
#else // ifdef VIXL_INCLUDE_SIMULATOR_AARCH32.
#define SETUP() MacroAssembler masm(BUF_SIZE);
@ -106,7 +106,7 @@
#define TEARDOWN()
#endif // ifdef VIXL_INCLUDE_SIMULATOR
#endif // ifdef VIXL_INCLUDE_SIMULATOR_AARCH32
namespace vixl {
namespace aarch32 {

6
test/aarch32/test-simulator-cond-rd-rn-rm-t32-sel.cc
View File

@ -46,7 +46,7 @@
#define __ masm.
#define BUF_SIZE (4096)
#ifdef VIXL_INCLUDE_SIMULATOR
#ifdef VIXL_INCLUDE_SIMULATOR_AARCH32
// Run tests with the simulator.
#define SETUP() MacroAssembler masm(BUF_SIZE)
@ -62,7 +62,7 @@
#define TEARDOWN()
#else // ifdef VIXL_INCLUDE_SIMULATOR.
#else // ifdef VIXL_INCLUDE_SIMULATOR_AARCH32.
#define SETUP() MacroAssembler masm(BUF_SIZE);
@ -106,7 +106,7 @@
#define TEARDOWN()
#endif // ifdef VIXL_INCLUDE_SIMULATOR
#endif // ifdef VIXL_INCLUDE_SIMULATOR_AARCH32
namespace vixl {
namespace aarch32 {

6
test/aarch32/test-simulator-cond-rd-rn-rm-t32.cc
View File

@ -46,7 +46,7 @@
#define __ masm.
#define BUF_SIZE (4096)
#ifdef VIXL_INCLUDE_SIMULATOR
#ifdef VIXL_INCLUDE_SIMULATOR_AARCH32
// Run tests with the simulator.
#define SETUP() MacroAssembler masm(BUF_SIZE)
@ -62,7 +62,7 @@
#define TEARDOWN()
#else // ifdef VIXL_INCLUDE_SIMULATOR.
#else // ifdef VIXL_INCLUDE_SIMULATOR_AARCH32.
#define SETUP() MacroAssembler masm(BUF_SIZE);
@ -106,7 +106,7 @@
#define TEARDOWN()
#endif // ifdef VIXL_INCLUDE_SIMULATOR
#endif // ifdef VIXL_INCLUDE_SIMULATOR_AARCH32
namespace vixl {
namespace aarch32 {

6
test/aarch32/test-simulator-cond-rd-rn-t32.cc
View File

@ -46,7 +46,7 @@
#define __ masm.
#define BUF_SIZE (4096)
#ifdef VIXL_INCLUDE_SIMULATOR
#ifdef VIXL_INCLUDE_SIMULATOR_AARCH32
// Run tests with the simulator.
#define SETUP() MacroAssembler masm(BUF_SIZE)
@ -62,7 +62,7 @@
#define TEARDOWN()
#else // ifdef VIXL_INCLUDE_SIMULATOR.
#else // ifdef VIXL_INCLUDE_SIMULATOR_AARCH32.
#define SETUP() MacroAssembler masm(BUF_SIZE);
@ -106,7 +106,7 @@
#define TEARDOWN()
#endif // ifdef VIXL_INCLUDE_SIMULATOR
#endif // ifdef VIXL_INCLUDE_SIMULATOR_AARCH32
namespace vixl {
namespace aarch32 {

6
test/aarch32/test-simulator-cond-rdlow-operand-imm8-t32.cc
View File

@ -46,7 +46,7 @@
#define __ masm.
#define BUF_SIZE (4096)
#ifdef VIXL_INCLUDE_SIMULATOR
#ifdef VIXL_INCLUDE_SIMULATOR_AARCH32
// Run tests with the simulator.
#define SETUP() MacroAssembler masm(BUF_SIZE)
@ -62,7 +62,7 @@
#define TEARDOWN()
#else // ifdef VIXL_INCLUDE_SIMULATOR.
#else // ifdef VIXL_INCLUDE_SIMULATOR_AARCH32.
#define SETUP() MacroAssembler masm(BUF_SIZE);
@ -106,7 +106,7 @@
#define TEARDOWN()
#endif // ifdef VIXL_INCLUDE_SIMULATOR
#endif // ifdef VIXL_INCLUDE_SIMULATOR_AARCH32
namespace vixl {
namespace aarch32 {

6
test/aarch32/test-simulator-cond-rdlow-rnlow-operand-immediate-t32.cc
View File

@ -46,7 +46,7 @@
#define __ masm.
#define BUF_SIZE (4096)
#ifdef VIXL_INCLUDE_SIMULATOR
#ifdef VIXL_INCLUDE_SIMULATOR_AARCH32
// Run tests with the simulator.
#define SETUP() MacroAssembler masm(BUF_SIZE)
@ -62,7 +62,7 @@
#define TEARDOWN()
#else // ifdef VIXL_INCLUDE_SIMULATOR.
#else // ifdef VIXL_INCLUDE_SIMULATOR_AARCH32.
#define SETUP() MacroAssembler masm(BUF_SIZE);
@ -106,7 +106,7 @@
#define TEARDOWN()
#endif // ifdef VIXL_INCLUDE_SIMULATOR
#endif // ifdef VIXL_INCLUDE_SIMULATOR_AARCH32
namespace vixl {
namespace aarch32 {

6
test/aarch32/test-simulator-cond-rdlow-rnlow-rmlow-t32.cc
View File

@ -46,7 +46,7 @@
#define __ masm.
#define BUF_SIZE (4096)
#ifdef VIXL_INCLUDE_SIMULATOR
#ifdef VIXL_INCLUDE_SIMULATOR_AARCH32
// Run tests with the simulator.
#define SETUP() MacroAssembler masm(BUF_SIZE)
@ -62,7 +62,7 @@
#define TEARDOWN()
#else // ifdef VIXL_INCLUDE_SIMULATOR.
#else // ifdef VIXL_INCLUDE_SIMULATOR_AARCH32.
#define SETUP() MacroAssembler masm(BUF_SIZE);
@ -106,7 +106,7 @@
#define TEARDOWN()
#endif // ifdef VIXL_INCLUDE_SIMULATOR
#endif // ifdef VIXL_INCLUDE_SIMULATOR_AARCH32
namespace vixl {
namespace aarch32 {

6
test/aarch32/test-simulator-rd-rn-rm-a32.cc
View File

@ -46,7 +46,7 @@
#define __ masm.
#define BUF_SIZE (4096)
#ifdef VIXL_INCLUDE_SIMULATOR
#ifdef VIXL_INCLUDE_SIMULATOR_AARCH32
// Run tests with the simulator.
#define SETUP() MacroAssembler masm(BUF_SIZE)
@ -62,7 +62,7 @@
#define TEARDOWN()
#else // ifdef VIXL_INCLUDE_SIMULATOR.
#else // ifdef VIXL_INCLUDE_SIMULATOR_AARCH32.
#define SETUP() MacroAssembler masm(BUF_SIZE);
@ -106,7 +106,7 @@
#define TEARDOWN()
#endif // ifdef VIXL_INCLUDE_SIMULATOR
#endif // ifdef VIXL_INCLUDE_SIMULATOR_AARCH32
namespace vixl {
namespace aarch32 {

6
test/aarch32/test-simulator-rd-rn-rm-t32.cc
View File

@ -46,7 +46,7 @@
#define __ masm.
#define BUF_SIZE (4096)
#ifdef VIXL_INCLUDE_SIMULATOR
#ifdef VIXL_INCLUDE_SIMULATOR_AARCH32
// Run tests with the simulator.
#define SETUP() MacroAssembler masm(BUF_SIZE)
@ -62,7 +62,7 @@
#define TEARDOWN()
#else // ifdef VIXL_INCLUDE_SIMULATOR.
#else // ifdef VIXL_INCLUDE_SIMULATOR_AARCH32.
#define SETUP() MacroAssembler masm(BUF_SIZE);
@ -106,7 +106,7 @@
#define TEARDOWN()
#endif // ifdef VIXL_INCLUDE_SIMULATOR
#endif // ifdef VIXL_INCLUDE_SIMULATOR_AARCH32
namespace vixl {
namespace aarch32 {

4
test/aarch64/examples/test-examples.cc
View File

@ -45,7 +45,7 @@ TEST(custom_disassembler) {
// The tests below only work with the simulator.
#ifdef VIXL_INCLUDE_SIMULATOR
#ifdef VIXL_INCLUDE_SIMULATOR_AARCH64
#define __ masm->
@ -597,4 +597,4 @@ TEST(runtime_calls) {
RUNTIME_CALLS_DOTEST(123, 456);
}
#endif // VIXL_INCLUDE_SIMULATOR
#endif // VIXL_INCLUDE_SIMULATOR_AARCH64

15
test/aarch64/test-assembler-aarch64.cc
View File

@ -95,7 +95,7 @@ namespace aarch64 {
#define __ masm.
#define TEST(name) TEST_(AARCH64_ASM_##name)
#ifdef VIXL_INCLUDE_SIMULATOR
#ifdef VIXL_INCLUDE_SIMULATOR_AARCH64
// Run tests with the simulator.
#define SETUP() \
@ -162,7 +162,7 @@ namespace aarch64 {
#define TEARDOWN_COMMON() \
delete simulator;
#else // ifdef VIXL_INCLUDE_SIMULATOR.
#else // ifdef VIXL_INCLUDE_SIMULATOR_AARCH64.
// Run the test on real hardware or models.
#define SETUP() \
MacroAssembler masm; \
@ -211,7 +211,7 @@ namespace aarch64 {
#define TEARDOWN_CUSTOM()
#endif // ifdef VIXL_INCLUDE_SIMULATOR.
#endif // ifdef VIXL_INCLUDE_SIMULATOR_AARCH64.
#define ASSERT_EQUAL_NZCV(expected) \
assert(EqualNzcv(expected, core.flags_nzcv()))
@ -14369,7 +14369,7 @@ TEST(printf_no_preserve) {
}
#ifndef VIXL_INCLUDE_SIMULATOR
#ifndef VIXL_INCLUDE_SIMULATOR_AARCH64
TEST(trace) {
// The Trace helper should not generate any code unless the simulator (or
// debugger) is being used.
@ -14388,7 +14388,7 @@ TEST(trace) {
#endif
#ifndef VIXL_INCLUDE_SIMULATOR
#ifndef VIXL_INCLUDE_SIMULATOR_AARCH64
TEST(log) {
// The Log helper should not generate any code unless the simulator (or
// debugger) is being used.
@ -15463,7 +15463,7 @@ TEST(clrex) {
}
#ifdef VIXL_INCLUDE_SIMULATOR
#ifdef VIXL_INCLUDE_SIMULATOR_AARCH64
// Check that the simulator occasionally makes store-exclusive fail.
TEST(ldxr_stxr_fail) {
uint64_t data[] = {0, 0, 0};
@ -15547,7 +15547,7 @@ TEST(ldxr_stxr_fail) {
#endif
#ifdef VIXL_INCLUDE_SIMULATOR
#ifdef VIXL_INCLUDE_SIMULATOR_AARCH64
// Check that the simulator occasionally makes store-exclusive fail.
TEST(ldaxr_stlxr_fail) {
uint64_t data[] = {0, 0, 0};
@ -22256,7 +22256,6 @@ void runtime_call_store_at_address(int64_t* address) {
#error "C++11 should be sufficient to provide support for `MacroAssembler::CallRuntime()`."
#endif // #if (__cplusplus >= 201103L) && ...
#ifdef VIXL_HAS_MACROASSEMBLER_RUNTIME_CALL_SUPPORT
TEST(runtime_calls) {
SETUP();

12
test/aarch64/test-disasm-aarch64.cc
View File

@ -45,18 +45,18 @@
#define SETUP() SETUP_CLASS(Assembler)
#ifdef VIXL_INCLUDE_SIMULATOR
#ifdef VIXL_INCLUDE_SIMULATOR_AARCH64
// Run tests with the simulator.
#define SETUP_MACRO() \
SETUP_CLASS(MacroAssembler); \
masm.SetGenerateSimulatorCode(true)
#else // ifdef VIXL_INCLUDE_SIMULATOR.
#else // ifdef VIXL_INCLUDE_SIMULATOR_AARCH64.
#define SETUP_MACRO() \
SETUP_CLASS(MacroAssembler); \
masm.SetGenerateSimulatorCode(false)
#endif // ifdef VIXL_INCLUDE_SIMULATOR.
#endif // ifdef VIXL_INCLUDE_SIMULATOR_AARCH64.
// A conservative limit for the size of the code that we generate in these
// tests.
@ -2826,7 +2826,7 @@ TEST(system_nop) {
TEST(unreachable) {
SETUP_MACRO();
#ifdef VIXL_INCLUDE_SIMULATOR
#ifdef VIXL_INCLUDE_SIMULATOR_AARCH64
VIXL_ASSERT(kUnreachableOpcode == 0xdeb0);
COMPARE(Unreachable(), "hlt #0xdeb0");
#else
@ -2837,7 +2837,7 @@ TEST(unreachable) {
}
#ifdef VIXL_INCLUDE_SIMULATOR
#ifdef VIXL_INCLUDE_SIMULATOR_AARCH64
TEST(trace) {
SETUP_MACRO();
@ -2852,7 +2852,7 @@ TEST(trace) {
#endif
#ifdef VIXL_INCLUDE_SIMULATOR
#ifdef VIXL_INCLUDE_SIMULATOR_AARCH64
TEST(log) {
SETUP_MACRO();

6
test/aarch64/test-simulator-aarch64.cc
View File

@ -53,7 +53,7 @@ namespace aarch64 {
#define __ masm.
#define TEST(name) TEST_(AARCH64_SIM_##name)
#ifdef VIXL_INCLUDE_SIMULATOR
#ifdef VIXL_INCLUDE_SIMULATOR_AARCH64
#define SETUP() \
MacroAssembler masm; \
@ -95,7 +95,7 @@ namespace aarch64 {
#define TEARDOWN() \
delete simulator;
#else // VIXL_INCLUDE_SIMULATOR
#else // VIXL_INCLUDE_SIMULATOR_AARCH64
#define SETUP() \
MacroAssembler masm; \
@ -124,7 +124,7 @@ namespace aarch64 {
#define TEARDOWN()
#endif // VIXL_INCLUDE_SIMULATOR
#endif // VIXL_INCLUDE_SIMULATOR_AARCH64
// The maximum number of errors to report in detail for each test.

4
test/aarch64/test-trace-aarch64.cc
View File

@ -42,7 +42,7 @@
namespace vixl {
namespace aarch64 {
// Trace tests can only work with the simulator.
#ifdef VIXL_INCLUDE_SIMULATOR
#ifdef VIXL_INCLUDE_SIMULATOR_AARCH64
#define __ masm->
#define TEST(name) TEST_(TRACE_##name)
@ -2717,6 +2717,6 @@ TEST(all_colour) {
}
#endif // VIXL_INCLUDE_SIMULATOR
#endif // VIXL_INCLUDE_SIMULATOR_AARCH64
} // namespace aarch64
} // namespace vixl

14
third_party/android/Android.mk.template vendored
View File

@ -112,7 +112,7 @@ endif
include $(CLEAR_VARS)
LOCAL_CLANG := true
LOCAL_CPP_EXTENSION := .cc
LOCAL_CPPFLAGS := $(vixl_cpp_flags_release) -DVIXL_INCLUDE_SIMULATOR
LOCAL_CPPFLAGS := $(vixl_cpp_flags_release) -DVIXL_INCLUDE_SIMULATOR_AARCH64
LOCAL_CLANG_CFLAGS := -Wimplicit-fallthrough
LOCAL_C_INCLUDES := $(vixl_src_include_path)
LOCAL_SRC_FILES := $(vixl_common_files) $(vixl_src_files_arm64)
@ -126,7 +126,7 @@ include $(BUILD_SHARED_LIBRARY)
include $(CLEAR_VARS)
LOCAL_CLANG := true
LOCAL_CPP_EXTENSION := .cc
LOCAL_CPPFLAGS := $(vixl_cpp_flags_debug) -DVIXL_INCLUDE_SIMULATOR
LOCAL_CPPFLAGS := $(vixl_cpp_flags_debug) -DVIXL_INCLUDE_SIMULATOR_AARCH64
LOCAL_CLANG_CFLAGS := -Wimplicit-fallthrough
LOCAL_C_INCLUDES := $(vixl_src_include_path)
LOCAL_SRC_FILES := $(vixl_common_files) $(vixl_src_files_arm64)
@ -141,7 +141,7 @@ include $(BUILD_SHARED_LIBRARY)
include $(CLEAR_VARS)
LOCAL_CLANG := true
LOCAL_CPP_EXTENSION := .cc
LOCAL_CPPFLAGS := $(vixl_cpp_flags_release) -DVIXL_INCLUDE_SIMULATOR
LOCAL_CPPFLAGS := $(vixl_cpp_flags_release) -DVIXL_INCLUDE_SIMULATOR_AARCH64
LOCAL_CLANG_CFLAGS := -Wimplicit-fallthrough
LOCAL_NATIVE_COVERAGE := $(VIXL_COVERAGE)
LOCAL_C_INCLUDES := $(vixl_src_include_path)
@ -157,7 +157,7 @@ include $(BUILD_HOST_SHARED_LIBRARY)
include $(CLEAR_VARS)
LOCAL_CLANG := true
LOCAL_CPP_EXTENSION := .cc
LOCAL_CPPFLAGS := $(vixl_cpp_flags_debug) -DVIXL_INCLUDE_SIMULATOR
LOCAL_CPPFLAGS := $(vixl_cpp_flags_debug) -DVIXL_INCLUDE_SIMULATOR_AARCH64
LOCAL_CLANG_CFLAGS := -Wimplicit-fallthrough
LOCAL_NATIVE_COVERAGE := $(VIXL_COVERAGE)
LOCAL_C_INCLUDES := $(vixl_src_include_path)
@ -174,7 +174,7 @@ include $(BUILD_HOST_SHARED_LIBRARY)
include $(CLEAR_VARS)
LOCAL_CLANG := true
LOCAL_CPP_EXTENSION := .cc
LOCAL_CPPFLAGS := $(vixl_cpp_flags_release) -DVIXL_INCLUDE_SIMULATOR
LOCAL_CPPFLAGS := $(vixl_cpp_flags_release) -DVIXL_INCLUDE_SIMULATOR_AARCH64
LOCAL_CLANG_CFLAGS := -Wimplicit-fallthrough
LOCAL_NATIVE_COVERAGE := $(VIXL_COVERAGE)
LOCAL_C_INCLUDES := $(vixl_src_include_path)
@ -190,7 +190,7 @@ include $(BUILD_HOST_STATIC_LIBRARY)
include $(CLEAR_VARS)
LOCAL_CLANG := true
LOCAL_CPP_EXTENSION := .cc
LOCAL_CPPFLAGS := $(vixl_cpp_flags_debug) -DVIXL_INCLUDE_SIMULATOR
LOCAL_CPPFLAGS := $(vixl_cpp_flags_debug) -DVIXL_INCLUDE_SIMULATOR_AARCH64
LOCAL_CLANG_CFLAGS := -Wimplicit-fallthrough
LOCAL_NATIVE_COVERAGE := $(VIXL_COVERAGE)
LOCAL_C_INCLUDES := $(vixl_src_include_path)
@ -307,7 +307,7 @@ include $(BUILD_HOST_STATIC_LIBRARY)
include $(CLEAR_VARS)
LOCAL_CLANG := true
LOCAL_CPP_EXTENSION := .cc
LOCAL_CPPFLAGS := $(vixl_cpp_flags_debug) -DVIXL_INCLUDE_SIMULATOR
LOCAL_CPPFLAGS := $(vixl_cpp_flags_debug) -DVIXL_INCLUDE_SIMULATOR_AARCH64
LOCAL_CLANG_CFLAGS := -Wimplicit-fallthrough
LOCAL_NATIVE_COVERAGE := $(VIXL_COVERAGE)
LOCAL_C_INCLUDES := $(vixl_test_include_path)