FEX-Emu/vixl
1
0
Fork 0
mirror of https://github.com/FEX-Emu/vixl.git synced 2024-11-27 08:40:54 +00:00
Code Issues Actions Packages Projects Releases Wiki Activity

Aarch64: Rename allow_simulator_instructions_ to generate_simulator_code_.

Browse Source 
Change-Id: I72956db90ab3380b5ad62b37d2ed203ec4045931
This commit is contained in:
Alexandre Rames 2016-07-11 16:31:52 +01:00
parent b2746629e8
commit 703ff06a08
8 changed files with 27 additions and 29 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

6
src/aarch32/assembler-aarch32.h
View File

@ -65,20 +65,20 @@ class Assembler : public Instructions {
: t32_(false),
first_condition_(al),
it_mask_(0),
generate_for_simulator_(VIXL_GENERATE_SIMULATOR_INSTRUCTIONS_VALUE),
generate_for_simulator_(VIXL_GENERATE_SIMULATOR_CODE),
has_32_dregs_(true) {}
explicit Assembler(size_t size)
: t32_(false),
first_condition_(al),
it_mask_(0),
generate_for_simulator_(VIXL_GENERATE_SIMULATOR_INSTRUCTIONS_VALUE),
generate_for_simulator_(VIXL_GENERATE_SIMULATOR_CODE),
has_32_dregs_(true),
buffer_(size) {}
Assembler(void* buffer, size_t size)
: t32_(false),
first_condition_(al),
it_mask_(0),
generate_for_simulator_(VIXL_GENERATE_SIMULATOR_INSTRUCTIONS_VALUE),
generate_for_simulator_(VIXL_GENERATE_SIMULATOR_CODE),
has_32_dregs_(true),
buffer_(buffer, size) {}
virtual ~Assembler() {}

4
src/aarch32/macro-assembler-aarch32.cc
View File

@ -539,7 +539,7 @@ void MacroAssembler::Printf(const char* format,
CPURegister reg2,
CPURegister reg3,
CPURegister reg4) {
#if VIXL_GENERATE_SIMULATOR_INSTRUCTIONS_VALUE
#if VIXL_GENERATE_SIMULATOR_CODE
PushRegister(reg4);
PushRegister(reg3);
PushRegister(reg2);
@ -707,7 +707,7 @@ void MacroAssembler::PushRegister(CPURegister reg) {
}
#if !VIXL_GENERATE_SIMULATOR_INSTRUCTIONS_VALUE
#if !VIXL_GENERATE_SIMULATOR_CODE
void MacroAssembler::PreparePrintfArgument(CPURegister reg,
int* core_count,
int* vfp_count,

2
src/aarch32/macro-assembler-aarch32.h
View File

@ -601,7 +601,7 @@ class MacroAssembler : public Assembler {
CPURegister reg4 = NoReg);
// Functions used by Printf for generation.
void PushRegister(CPURegister reg);
#if !VIXL_GENERATE_SIMULATOR_INSTRUCTIONS_VALUE
#if !VIXL_GENERATE_SIMULATOR_CODE
void PreparePrintfArgument(CPURegister reg,
int* core_count,
int* vfp_count,

12
src/aarch64/macro-assembler-aarch64.cc
View File

@ -301,7 +301,7 @@ MacroAssembler::MacroAssembler(PositionIndependentCodeOption pic)
#ifdef VIXL_DEBUG
allow_macro_instructions_(true),
#endif
allow_simulator_instructions_(VIXL_GENERATE_SIMULATOR_INSTRUCTIONS_VALUE),
generate_simulator_code_(VIXL_GENERATE_SIMULATOR_CODE),
sp_(sp),
tmp_list_(ip0, ip1),
fptmp_list_(d31),
@ -318,7 +318,7 @@ MacroAssembler::MacroAssembler(size_t capacity,
#ifdef VIXL_DEBUG
allow_macro_instructions_(true),
#endif
allow_simulator_instructions_(VIXL_GENERATE_SIMULATOR_INSTRUCTIONS_VALUE),
generate_simulator_code_(VIXL_GENERATE_SIMULATOR_CODE),
sp_(sp),
tmp_list_(ip0, ip1),
fptmp_list_(d31),
@ -336,7 +336,7 @@ MacroAssembler::MacroAssembler(byte* buffer,
#ifdef VIXL_DEBUG
allow_macro_instructions_(true),
#endif
allow_simulator_instructions_(VIXL_GENERATE_SIMULATOR_INSTRUCTIONS_VALUE),
generate_simulator_code_(VIXL_GENERATE_SIMULATOR_CODE),
sp_(sp),
tmp_list_(ip0, ip1),
fptmp_list_(d31),
@ -2418,7 +2418,7 @@ void MacroAssembler::PrintfNoPreserve(const char* format,
// Actually call printf. This part needs special handling for the simulator,
// since the system printf function will use a different instruction set and
// the procedure-call standard will not be compatible.
if (allow_simulator_instructions_) {
if (generate_simulator_code_) {
InstructionAccurateScope scope(this, kPrintfLength / kInstructionSize);
hlt(kPrintfOpcode);
dc32(arg_count); // kPrintfArgCountOffset
@ -2519,7 +2519,7 @@ void MacroAssembler::Printf(const char* format,
void MacroAssembler::Trace(TraceParameters parameters, TraceCommand command) {
VIXL_ASSERT(allow_macro_instructions_);
if (allow_simulator_instructions_) {
if (generate_simulator_code_) {
// The arguments to the trace pseudo instruction need to be contiguous in
// memory, so make sure we don't try to emit a literal pool.
InstructionAccurateScope scope(this, kTraceLength / kInstructionSize);
@ -2546,7 +2546,7 @@ void MacroAssembler::Trace(TraceParameters parameters, TraceCommand command) {
void MacroAssembler::Log(TraceParameters parameters) {
VIXL_ASSERT(allow_macro_instructions_);
if (allow_simulator_instructions_) {
if (generate_simulator_code_) {
// The arguments to the log pseudo instruction need to be contiguous in
// memory, so make sure we don't try to emit a literal pool.
InstructionAccurateScope scope(this, kLogLength / kInstructionSize);

14
src/aarch64/macro-assembler-aarch64.h
View File

@ -2077,7 +2077,7 @@ class MacroAssembler : public Assembler {
void Unreachable() {
VIXL_ASSERT(allow_macro_instructions_);
SingleEmissionCheckScope guard(this);
if (allow_simulator_instructions_) {
if (generate_simulator_code_) {
hlt(kUnreachableOpcode);
} else {
// Branch to 0 to generate a segfault.
@ -2836,13 +2836,11 @@ class MacroAssembler : public Assembler {
bool AllowMacroInstructions() const { return allow_macro_instructions_; }
#endif
void SetAllowSimulatorInstructions(bool value) {
allow_simulator_instructions_ = value;
void SetGenerateSimulatorCode(bool value) {
generate_simulator_code_ = value;
}
bool AllowSimulatorInstructions() const {
return allow_simulator_instructions_;
}
bool GenerateSimulatorCode() const { return generate_simulator_code_; }
void BlockLiteralPool() { literal_pool_.Block(); }
void ReleaseLiteralPool() { literal_pool_.Release(); }
@ -3098,8 +3096,8 @@ class MacroAssembler : public Assembler {
bool allow_macro_instructions_;
#endif
// Tell whether we should generate code that will run on the simulator or not.
bool allow_simulator_instructions_;
// Indicates whether we should generate simulator or native code.
bool generate_simulator_code_;
// The register to use as a stack pointer for stack operations.
Register sp_;

10
src/globals-vixl.h
View File

@ -158,14 +158,14 @@ inline void USE(T1, T2, T3, T4) {}
#endif
#ifdef VIXL_INCLUDE_SIMULATOR
#ifndef VIXL_GENERATE_SIMULATOR_INSTRUCTIONS_VALUE
#define VIXL_GENERATE_SIMULATOR_INSTRUCTIONS_VALUE 1
#ifndef VIXL_GENERATE_SIMULATOR_CODE
#define VIXL_GENERATE_SIMULATOR_CODE 1
#endif
#else
#ifndef VIXL_GENERATE_SIMULATOR_INSTRUCTIONS_VALUE
#define VIXL_GENERATE_SIMULATOR_INSTRUCTIONS_VALUE 0
#ifndef VIXL_GENERATE_SIMULATOR_CODE
#define VIXL_GENERATE_SIMULATOR_CODE 0
#endif
#if VIXL_GENERATE_SIMULATOR_INSTRUCTIONS_VALUE
#if VIXL_GENERATE_SIMULATOR_CODE
#warning "Generating Simulator instructions without Simulator support."
#endif
#endif

4
test/aarch64/test-assembler-aarch64.cc
View File

@ -109,7 +109,7 @@ namespace aarch64 {
SETUP_COMMON()
#define SETUP_COMMON() \
masm.SetAllowSimulatorInstructions(true); \
masm.SetGenerateSimulatorCode(true); \
Decoder decoder; \
Simulator* simulator = Test::run_debugger() ? new Debugger(&decoder) \
: new Simulator(&decoder); \
@ -176,7 +176,7 @@ namespace aarch64 {
SETUP_COMMON()
#define SETUP_COMMON() \
masm.SetAllowSimulatorInstructions(false); \
masm.SetGenerateSimulatorCode(false); \
RegisterDump core; \
CPU::SetUp()

4
test/aarch64/test-disasm-aarch64.cc
View File

@ -52,12 +52,12 @@
// Run tests with the simulator.
#define SETUP_MACRO() \
SETUP_CLASS(MacroAssembler); \
masm->SetAllowSimulatorInstructions(true)
masm->SetGenerateSimulatorCode(true)
#else // ifdef VIXL_INCLUDE_SIMULATOR.
#define SETUP_MACRO() \
SETUP_CLASS(MacroAssembler); \
masm->SetAllowSimulatorInstructions(false)
masm->SetGenerateSimulatorCode(false)
#endif // ifdef VIXL_INCLUDE_SIMULATOR.