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Aarch64: Introduce MemOperand::IsValid()
and MemOperand::Equals()
.
Change-Id: I716ce507b398b4a86048d9346a1233b67baef99e
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parent
61e54cf693
commit
8edbcac915
@ -365,7 +365,12 @@ Operand Operand::ToExtendedRegister() const {
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// MemOperand
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MemOperand::MemOperand(Register base, int64_t offset, AddrMode addrmode)
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: base_(base), regoffset_(NoReg), offset_(offset), addrmode_(addrmode) {
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: base_(base),
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regoffset_(NoReg),
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offset_(offset),
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addrmode_(addrmode),
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shift_(NO_SHIFT),
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extend_(NO_EXTEND) {
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VIXL_ASSERT(base.Is64Bits() && !base.IsZero());
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}
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@ -408,7 +413,11 @@ MemOperand::MemOperand(Register base,
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MemOperand::MemOperand(Register base, const Operand& offset, AddrMode addrmode)
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: base_(base), regoffset_(NoReg), addrmode_(addrmode) {
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: base_(base),
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regoffset_(NoReg),
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addrmode_(addrmode),
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shift_(NO_SHIFT),
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extend_(NO_EXTEND) {
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VIXL_ASSERT(base.Is64Bits() && !base.IsZero());
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if (offset.IsImmediate()) {
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@ -827,6 +827,21 @@ class MemOperand {
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void AddOffset(int64_t offset);
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bool IsValid() const {
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return base_.IsValid() &&
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((addrmode_ == Offset) || (addrmode_ == PreIndex) ||
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(addrmode_ == PostIndex)) &&
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((shift_ == NO_SHIFT) || (extend_ == NO_EXTEND)) &&
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((offset_ == 0) || !regoffset_.IsValid());
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}
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bool Equals(const MemOperand& other) const {
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return base_.Is(other.base_) && regoffset_.Is(other.regoffset_) &&
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(offset_ == other.offset_) && (addrmode_ == other.addrmode_) &&
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(shift_ == other.shift_) && (extend_ == other.extend_) &&
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(shift_amount_ == other.shift_amount_);
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}
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private:
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Register base_;
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Register regoffset_;
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