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Fix section header in supported instructions document (#15)
The Markdown to HTML generator Github uses appears to want a newline after HTML in order to recognise Markdown tags. Fix the document and generator to do this.
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@ -24,6 +24,7 @@ AArch64 integer instructions
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----------------------------
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<a id="integer-a">
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### ADC ###
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Add with carry bit.
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@ -214,6 +215,7 @@ Convert floating-point condition flags from Arm format to alternative format _(A
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<a id="integer-b">
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### B ###
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Conditional branch to PC offset.
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@ -392,6 +394,7 @@ Branch target identification.
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<a id="integer-c">
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### CAS ###
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Compare and Swap word or doubleword in memory _(Armv8.1)_.
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@ -749,6 +752,7 @@ Conditional select negation: rd = cond ? rn : -rm.
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<a id="integer-d">
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### DC ###
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System data cache operation.
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@ -771,6 +775,7 @@ Data synchronization barrier.
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<a id="integer-e">
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### EON ###
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Bitwise enor/xnor (A ^ ~B).
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@ -803,6 +808,7 @@ Extract.
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<a id="integer-h">
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### HINT ###
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System hint (named type).
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@ -825,6 +831,7 @@ Halting debug-mode breakpoint.
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<a id="integer-i">
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### IC ###
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System instruction cache operation.
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@ -840,6 +847,7 @@ Instruction synchronization barrier.
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<a id="integer-l">
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### LDADD ###
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Atomic add on word or doubleword in memory _(Armv8.1)_
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@ -1877,6 +1885,7 @@ Logical shift right by variable.
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<a id="integer-m">
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### MADD ###
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Multiply and accumulate.
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@ -1968,6 +1977,7 @@ Move inverted operand to register.
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<a id="integer-n">
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### NEG ###
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Negate.
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@ -2004,6 +2014,7 @@ No-op.
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<a id="integer-o">
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### ORN ###
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Bitwise nor (A | ~B).
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@ -2019,6 +2030,7 @@ Bitwise or (A | B).
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<a id="integer-p">
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### PACDA ###
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Pointer Authentication Code for Data address, using key A _(Armv8.3)_.
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@ -2189,6 +2201,7 @@ Prefetch memory (with unscaled offset, allowing unallocated hints).
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<a id="integer-r">
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### RBIT ###
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Bit reverse.
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@ -2267,6 +2280,7 @@ Rotate right by variable.
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<a id="integer-s">
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### SBC ###
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Subtract with carry bit.
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@ -3040,6 +3054,7 @@ System instruction.
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<a id="integer-t">
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### TBNZ ###
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Test bit and branch to PC offset if not zero.
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@ -3076,6 +3091,7 @@ Bit test and set flags.
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<a id="integer-u">
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### UBFIZ ###
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Unsigned bitfield insert with zero at right.
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@ -3176,6 +3192,7 @@ Unsigned extend word.
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<a id="integer-x">
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### XAFLAG ###
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Convert floating-point condition flags from alternative format to Arm format _(Armv8.5)_.
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@ -3209,6 +3226,7 @@ AArch64 floating point and NEON instructions
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--------------------------------------------
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<a id="float-a">
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### ABS ###
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Absolute value.
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@ -3266,6 +3284,7 @@ Bitwise and.
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<a id="float-b">
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### BIC ###
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Bit clear immediate.
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@ -3302,6 +3321,7 @@ Bitwise select.
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<a id="float-c">
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### CLS ###
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Count leading sign bits.
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@ -3401,6 +3421,7 @@ Population count per byte.
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<a id="float-d">
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### DUP ###
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Duplicate general-purpose register to vector.
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@ -3416,6 +3437,7 @@ Duplicate vector element to vector or scalar.
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<a id="float-e">
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### EOR ###
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Bitwise eor.
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@ -3434,6 +3456,7 @@ Extract vector from pair of vectors.
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<a id="float-f">
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### FABD ###
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FP absolute difference.
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@ -4316,6 +4339,7 @@ FP subtract.
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<a id="float-i">
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### INS ###
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Insert vector element from another vector element.
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@ -4334,6 +4358,7 @@ Insert vector element from general-purpose register.
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<a id="float-l">
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### LD1 ###
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One-element single structure load to one lane.
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@ -4473,6 +4498,7 @@ Four-element single structure load to all lanes.
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<a id="float-m">
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### MLA ###
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Multiply-add by scalar element.
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@ -4590,6 +4616,7 @@ Vector move inverted immediate.
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<a id="float-n">
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### NEG ###
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Negate.
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@ -4605,6 +4632,7 @@ Bitwise not.
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<a id="float-o">
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### ORN ###
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Bitwise orn.
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@ -4627,6 +4655,7 @@ Bitwise or.
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<a id="float-p">
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### PMUL ###
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Polynomial multiply.
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@ -4649,6 +4678,7 @@ Polynomial multiply long (second part).
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<a id="float-r">
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### RADDHN ###
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Rounding add narrow returning high half.
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@ -4720,6 +4750,7 @@ Rounding subtract narrow returning high half (second part).
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<a id="float-s">
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### SABA ###
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Signed absolute difference and accumulate.
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@ -5620,6 +5651,7 @@ Signed extend long (second part).
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<a id="float-t">
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### TBL ###
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Table lookup from four registers.
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@ -5715,6 +5747,7 @@ Transpose vectors (secondary).
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<a id="float-u">
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### UABA ###
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Unsigned absolute difference and accumulate.
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@ -6251,6 +6284,7 @@ Unzip vectors (secondary).
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<a id="float-x">
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### XTN ###
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Extract narrow.
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@ -6266,6 +6300,7 @@ Extract narrow (second part).
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<a id="float-z">
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### ZIP1 ###
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Zip vectors (primary).
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@ -6285,6 +6320,7 @@ AArch64 Scalable Vector Extension (SVE) instructions
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----------------------------------------------------
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<a id="sve-a">
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### ABS ###
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Absolute value (predicated).
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@ -6481,6 +6517,7 @@ Reversed arithmetic shift right by vector (predicated).
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<a id="sve-b">
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### BCAX ###
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Bitwise clear and exclusive OR.
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@ -6683,6 +6720,7 @@ Bitwise select with second input inverted.
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<a id="sve-c">
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### CADD ###
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Complex integer add with rotate.
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@ -7114,6 +7152,7 @@ Compare and terminate loop.
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<a id="sve-d">
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### DECB ###
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Decrement scalar by multiple of predicate constraint element count.
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@ -7206,6 +7245,7 @@ Broadcast logical bitmask immediate to vector (unpredicated).
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<a id="sve-e">
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### EON ###
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Bitwise exclusive OR with inverted immediate (unpredicated).
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@ -7299,6 +7339,7 @@ Extract vector from pair of vectors.
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<a id="sve-f">
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### FABD ###
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Floating-point absolute difference (predicated).
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@ -8208,6 +8249,7 @@ Floating-point trigonometric select coefficient.
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<a id="sve-h">
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### HISTCNT ###
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Count matching elements in vector.
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@ -8226,6 +8268,7 @@ Count matching elements in vector segments.
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<a id="sve-i">
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### INCB ###
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Increment scalar by multiple of predicate constraint element count.
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@ -8332,6 +8375,7 @@ Insert general-purpose register in shifted vector.
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<a id="sve-l">
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### LASTA ###
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Extract element after last to SIMD&FP scalar register.
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@ -9115,6 +9159,7 @@ Reversed logical shift right by vector (predicated).
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<a id="sve-m">
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### MAD ###
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Multiply-add vectors (predicated), writing multiplicand [Zdn = Za + Zdn * Zm].
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@ -9345,6 +9390,7 @@ Multiply vectors (unpredicated).
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<a id="sve-n">
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### NAND ###
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Bitwise NAND predicates.
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@ -9438,6 +9484,7 @@ Bitwise invert predicate, setting the condition flags.
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<a id="sve-o">
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### ORN ###
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Bitwise OR inverted predicate.
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@ -9517,6 +9564,7 @@ Bitwise OR reduction to scalar.
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<a id="sve-p">
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### PFALSE ###
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Set all predicate elements to false.
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@ -9637,6 +9685,7 @@ Unpack and widen half of predicate.
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<a id="sve-r">
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### RADDHNB ###
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Rounding add narrow high part (bottom).
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@ -9750,6 +9799,7 @@ Rounding subtract narrow high part (top).
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<a id="sve-s">
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### SABA ###
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Signed absolute difference and accumulate.
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@ -11288,6 +11338,7 @@ Signed word extend (predicated).
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<a id="sve-t">
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### TBL ###
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Programmable table lookup in one or two vector table (zeroing).
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@ -11345,6 +11396,7 @@ Interleave even or odd elements from two vectors.
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<a id="sve-u">
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### UABA ###
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Unsigned absolute difference and accumulate.
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@ -12194,6 +12246,7 @@ Concatenate even or odd elements from two vectors.
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<a id="sve-w">
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### WHILEGE ###
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While decrementing signed scalar greater than or equal to scalar.
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@ -12292,6 +12345,7 @@ Write the first-fault register.
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<a id="sve-x">
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### XAR ###
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Bitwise exclusive OR and rotate right by immediate.
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@ -12303,6 +12357,7 @@ Bitwise exclusive OR and rotate right by immediate.
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<a id="sve-z">
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### ZIP1 ###
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Interleave elements from two half predicates.
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@ -12340,6 +12395,7 @@ Additional or pseudo instructions
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---------------------------------
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<a id="pseudo-b">
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### BIND ###
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Bind a label to the current PC.
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@ -12348,6 +12404,7 @@ Bind a label to the current PC.
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<a id="pseudo-d">
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### DC ###
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Emit data in the instruction stream.
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@ -12377,6 +12434,7 @@ Emit raw instructions into the instruction stream.
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<a id="pseudo-p">
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### PLACE ###
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Place a literal at the current PC.
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@ -176,7 +176,7 @@ sub describe_insts
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next if($inst{$i}->{'type'} ne $type);
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unless ($last_initial eq $inst{$i}->{'initial'}) {
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$last_initial = $inst{$i}->{'initial'};
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$result .= sprintf("<a id=\"%s-%s\">\n", lc($type), $last_initial);
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$result .= sprintf("<a id=\"%s-%s\">\n\n", lc($type), $last_initial);
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}
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$result .= sprintf("### %s ###\n\n%s\n\n",
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uc($inst{$i}->{'mnemonic'}),
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