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Author SHA1 Message Date
Scott Wakeling
294e6f426d AArch32: Add GetSizeOfCodeGenerated() const accessor to Assembler. 
Change-Id: I84877dd2c6aa6d0c5755c9dab6235e618bec26b6
 2016-07-22 10:22:48 +00:00
Scott Wakeling
5f916f4f8d AArch32: Add shared target libraries to Android.mk.template. 
Change-Id: I588d59135b124a15edc7f2a5c74c034e5fc9a8f3
 2016-07-22 09:47:52 +01:00
Alexandre Rames
0d68001a97 AArch64: update the behaviour of breakpoint in the debugger. 
When hitting a breakpoint, the debugger now stops with the PC pointing *after*
the breakpoint.

Before:

  vixl> disasm 6
  0x0000000002271c58  d2800021        mov x1, #0x1
  0x0000000002271c5c  d2800042        mov x2, #0x2
  0x0000000002271c60  d2800063        mov x3, #0x3
  0x0000000002271c64  d2800084        mov x4, #0x4
  0x0000000002271c68  d4200020        brk #0x1
  0x0000000002271c6c  d28000a5        mov x5, #0x5
  vixl> c
  Hit breakpoint at pc=0x2271c68.
  Next: 0x0000000002271c68  d4200020  brk #0x1
  vixl>

After:

  vixl> disasm 6
  0x000000000118dc58  d2800021        mov x1, #0x1
  0x000000000118dc5c  d2800042        mov x2, #0x2
  0x000000000118dc60  d2800063        mov x3, #0x3
  0x000000000118dc64  d2800084        mov x4, #0x4
  0x000000000118dc68  d4200020        brk #0x1
  0x000000000118dc6c  d28000a5        mov x5, #0x5
  vixl> c
  Hit breakpoint at pc=0x118dc68.
  Next: 0x000000000118dc6c  d28000a5  mov x5, #0x5

Change-Id: Ia14e030cd1fa4ab73e49ec0782c91c04fc4fcc5e
 2016-07-21 14:15:49 +00:00
Alexandre Rames
86af869710 Fix a formatting error. 
Change-Id: I84e4b137904a89b62b931c5d8e16a0d7620d6ab9
 2016-07-21 11:29:32 +01:00
Alexandre Rames
80497ed4c9 Add a skip command to the AArch64 debugger. 
Here is an example of user interaction:

    Hit breakpoint at pc=0xb3cc50.
    Next: 0x0000000000b3cc50  d4200000		brk #0x0
    vixl> disasm
    0x0000000000b3cc50  d4200000		brk #0x0
    0x0000000000b3cc54  d2800000		mov x0, #0x0
    0x0000000000b3cc58  d2800021		mov x1, #0x1
    0x0000000000b3cc5c  d2800042		mov x2, #0x2
    0x0000000000b3cc60  d2800063		mov x3, #0x3
    0x0000000000b3cc64  d2800084		mov x4, #0x4
    0x0000000000b3cc68  d28000a5		mov x5, #0x5
    0x0000000000b3cc6c  f100001f		cmp x0, #0x0 (0)
    0x0000000000b3cc70  da805400		cneg x0, x0, mi
    0x0000000000b3cc74  d65f03c0		ret
    vixl> stepi
    Next: 0x0000000000b3cc58  d2800021		mov x1, #0x1
    vixl> skip 3
    Skipping over 3 instructions:
    Skip: 0x0000000000b3cc58  d2800021		mov x1, #0x1
    Skip: 0x0000000000b3cc5c  d2800042		mov x2, #0x2
    Skip: 0x0000000000b3cc60  d2800063		mov x3, #0x3
    Next: 0x0000000000b3cc64  d2800084		mov x4, #0x4
    vixl>

Change-Id: I833cf6381edf94423f1e54dae636d206a93fed9f
 2016-07-20 16:47:16 +01:00
Alexandre Rames
384fe09960 Fix the AArch64 debugger breaking mechanism. 
The PC was not correctly incremented when trying to execute past a
breakpoint after the debugger shell had run.

Change-Id: I836ace501a4b32e62b7a1014a57480d3fdf54f8c
 2016-07-20 15:46:02 +00:00
Alexandre Rames
4886a72530 Fix the AArch64 debugger's stepi command. 
Change-Id: I5e16d72760e0b288ef1e86f13997d1d5e7d6f2eb
 2016-07-20 15:45:18 +00:00
Alexandre Rames
6c0406d676 Add a default argument for the aarch32::PrintDisassembler constructor. 
Change-Id: If59c0fb16e4ea4ae72a7aeaa670ea8b54b218aca
 2016-07-20 12:19:26 +00:00
Alexandre Rames
81c76e6133 Print relative real paths when running tests. 
For example, on my setup, this changes:

    ./tools/test.py --fast
    [...]
    /work/vixl/vixl/obj/mode_debug/symbols_on/CXX_clang++/std_c++98/simulator_on/benchmarks/aarch64/bench-branch-link-masm
    [...]

to

    ./tools/test.py --fast
    [...]
    obj/mode_debug/symbols_on/CXX_clang++/std_c++98/simulator_on/benchmarks/aarch64/bench-branch-link-masm
    [...]


Change-Id: I369e49fe0ef65d4ce313a0bfb8e3ed99bf4dbd61
 2016-07-20 10:39:38 +01:00
Alexandre Rames
bf499cc386 Improve processing in tools/lint.py. 
This makes `tools/lint.py --uncached` faster again. The text output
is also updated more regularly.

Change-Id: I24fe29881e154e0abb686d7ad68fd5be94b41852
 2016-07-13 09:16:40 +01:00
Alexandre Rames
8edbcac915 Aarch64: Introduce MemOperand::IsValid() and MemOperand::Equals(). 
Change-Id: I716ce507b398b4a86048d9346a1233b67baef99e
 2016-07-12 16:50:42 +01:00
Alexandre Rames
61e54cf693 Avoid spawning tasks to lint test traces header files. 
Although the CPPLINT.cfg files exclude those, simply starting
the linting tasks is expensive.
Number of linting tasks started:
before: 2670
after: 201

Change-Id: I4ebcf1e27d4ff388e0b2d5f15645c52fd4927db4
 2016-07-12 16:27:17 +01:00
Alexandre Rames
703ff06a08 Aarch64: Rename allow_simulator_instructions_ to generate_simulator_code_. 
Change-Id: I72956db90ab3380b5ad62b37d2ed203ec4045931
 2016-07-12 15:26:02 +00:00
Alexandre Rames
b2746629e8 Cache tools/lint.py results. 
Change-Id: Id9ca69583796e202f68dad847ef640824146fd59
 2016-07-12 14:52:20 +00:00
Alexandre Rames
9aded35530 Aarch64: Clean a few more usage of the MacroAssembler constructor. 
Change-Id: Ibc1ed87b7105c9b2c6e710f15347e7023e8f8a98
 2016-07-11 17:11:03 +01:00
Alexandre Rames
dd7de86797 Tweak configuration of tools/test.py's fast mode. 
Change-Id: Idbf424da0ddeb817aa089cf78814ab9dfb542ebf
 2016-07-11 10:31:58 +01:00
Alexandre Rames
73064a2fd9 Introduce the --fail-early option for tools/test.py. 
Exit the test with the appropriate exit code as soon as the
first test or building stage fails.

Change-Id: I727aeef0afaf4d0b23d1d25911a08f24bfc28a7f
Signed-off-by: Daniel Díaz <daniel.diaz@linaro.org>
 2016-07-11 10:19:17 +01:00
Alexandre Rames
def50a5485 Aarch64: Extract registers and operands in separate files. 
Also clean `#include` directives of `assembler-aarch64.h`.

Change-Id: Ic269216eba1c8c09318a92465365b5cf4a8dbd68
 2016-07-06 09:33:10 +01:00
Alexandre Rames
d3832965c6 Update naming to aarch32 and aarch64. 
Change-Id: I40a929b1095ee3e1b2ca5ef879c7006d8b59acc9
 2016-07-04 15:03:43 +01:00
Alexandre Rames
b78f13911b Add an AUTHORS file and update copyright notices. 
Change-Id: Ifb505e5664996c1af41e38376e58ba49864213a3
 2016-07-04 08:44:15 +01:00
Alexandre Rames
9d9901810c Improve VIXL static assertion macros. 
Change-Id: I346c6ac316ad9939038ae4541d25031429df5d5d
 2016-07-01 14:43:01 +00:00
Alexandre Rames
f2f550c0bf Use the default vixl::aarch64::MacroAssembler constructor where sensible. 
Change-Id: If5d07577778a61f07f95f305a286e0215161334a
 2016-07-01 14:52:47 +01:00
Alexandre Rames
89dabc88e9 Fix the YCM configuration for the simulator. 
Change-Id: Ib83b3e53eedf8425813eeb45cb931a583e61a30d
 2016-07-01 14:00:44 +01:00
Anton Kirilov
6a46bf3b4e Ensure stricter alignment when loading and storing register pairs. 
The impetus for this change is the fact that loads that cross a
64 byte boundary and stores that cross a 16 byte boundary are a
performance issue on Cortex-A57 and A72.

Change-Id: I69b81a9c3218772b02fd10be7ebf16122bb0b83c
 2016-06-21 11:45:09 +01:00
Pierre Langlois
dcd672d4b9 Merge "Include 32 bit sources in Android.mk generator" 2016-06-20 09:27:54 +00:00
Pierre Langlois
f849f80efe Include 32 bit sources in Android.mk generator 
It seems there was a merge issue when including the AArch32 port of VIXL
and the port of `generate_android.mk.py` was incorrectly added.

Change-Id: Id99d81c4dd6e40684d069b32eee4a8891bcdb209
 2016-06-17 13:45:56 +01:00
Alexandre Rames
715f99ab62 Update comments in the a32 literal pool design document. 
Change-Id: I5c3a89df8563e3fb15639d357ae4346db1c69585
 2016-06-17 10:44:52 +01:00
Alexandre Rames
6d3f773e31 Remove the unused a32 enum FlagsUpdate. 
Change-Id: Ide240462fab01b5993f23091015b123c821584a4
 2016-06-17 10:41:13 +01:00
Alexandre Rames
da58c695fb Remove the unused default paramater for aarch32::MacroAssembler::EnsureEmitFor. 
Change-Id: I9ffab42a047fc0e051d133a28ef13f60b13809f0
 2016-06-17 10:38:14 +01:00
Alexandre Rames
b0d7672aa9 Introduce a default MacroAssembler constructor. 
Change-Id: I3b1f892ce413301ded32887e58d4c0a277e877fe
 2016-06-09 13:53:29 +01:00
Alexandre Rames
1f708eecf2 Add a missing typename. 
This was observed using VIXL as a separate library with (at least):

    clang++ --version
    Apple LLVM version 7.3.0 (clang-703.0.29)
    Target: x86_64-apple-darwin15.5.0
    Thread model: posix

Change-Id: I8fedc210232f454539c0ee07f9dffd3759ad42ac
 2016-06-08 21:56:14 +01:00
Alexandre Rames
4e2419325b Correctly remove obj/latest when it is a directory. 
Change-Id: I435bf61633433a80647b58eeeb22d7de6de44227
 2016-06-08 21:39:20 +01:00
Alexandre Rames
dd47fed5e4 Fix a bug in the MacroAssembler CSEL helpers. 
This also introduces regression tests.

Change-Id: Ic0966c369acfaa4017c874926c86ba3b46ff2e9b
 2016-06-07 09:08:40 +01:00
Pierre Langlois
88c46b84df Add assembler, macro-assembler and disassembler support for AArch32 
Add support for the A32 and T32 instruction set architectures in
seperate a32 directories.

Note that this commit introduces aarch32 and aarch64 namespaces so
existing client code will need to be adjusted.

Refer to doc/getting-started-a32.md for an introduction.

Change-Id: Iaf3e5f496ec4e19d77d304128e6920daa4549e78
 2016-06-03 10:33:51 +01:00
Jacob Bramley
5bc98e5bed Work around a clang-format bug. 
Change-Id: Iae451d3f1afa7cf9a44caa1eebf098a0ce9da58e
 2016-06-02 15:40:58 +01:00
Alexandre Rames
7a520b3749 Disable clang-format for comments containing NOLINT. 
Change-Id: I523efd715ec47ab661d1ceebce86a2a0f72d926b
 2016-06-02 10:49:09 +01:00
Alex Light
95372fcd05 Fix the Android makefile. 
This is a cherry-pick of https://android-review.googlesource.com/#/c/232680.

Change-Id: If4f6627c08edc7ae6f72177fa9721687fcbc05ec
 2016-05-25 17:24:51 +01:00
Alexandre Rames
b68bacb75c Sort and fix #include directives. 
Includes are sorted into groups, each sorted alphabetically and separated by a
blank line. The groups are, in order, C headers, C++ headers, VIXL (non-backend)
headers, and VIXL backend headers.

Change-Id: I9a71430bffeaf77389a089487ce264db8d1d9ddc
 2016-05-25 13:26:11 +01:00
Alexandre Rames
1f9074de15 Suffix source files in src/ with -vixl. 
This is required to keep VIXL building within Android: its build system copies
files across assuming that there will be no naming conflicts.

Change-Id: I9475c8833dd2f74f814004b7572ccc61337046fb
 2016-05-25 13:26:11 +01:00
Alexandre Rames
39c32a63e0 Move source files from src/vixl/ to src/. 
This commit only moves files and updates the `#include` paths appropriately.

Change-Id: I9d430bd34af617c943a6c6570c9a3c27169eaf1b
 2016-05-23 15:53:50 +01:00
Alexandre Rames
fc81d9b819 Do not use $ANDROID_BUILD_TOP in Android.mk. 
It causes `make -j20 test-art-host-vixl` to fail when running without
sourcing `build/envsetup.sh` and running lunch.

Change-Id: Ie9028ca69c357e586e899f3f24a561fb311ed814
 2016-05-18 15:35:55 +01:00
Alexandre Rames
7c0ea8b64c Set the exit code in tools/test.py to indicate success or failure. 
Change-Id: If7ad98423ed2a58ad201c7c71c93b95781739e5a
 2016-05-18 13:47:42 +01:00
Alexandre Rames
ba1832c903 Fix the Android.mk.template. 
The test-runner must be run from the vixl root.

Change-Id: I6ef4bb8cfcb939fee34662a85cae286b253c9ca8
 2016-05-16 10:26:57 +01:00
Jacob Bramley
838e379d79 Add a .gitreview for Linaro's server. 
Change-Id: Ia23a784928704c8ab33e1a2eb91cd96fd0b313c6
 2016-05-13 16:14:28 +01:00
John Pulford
85a01e7807 Fix for undefined uint64_t to int64_t conversion. 
Change-Id: Ibaad452aafbc4679751a2227e09884cb4d3b5d0e
 2016-05-13 15:52:24 +01:00
armvixl
0f35e36b7f VIXL Release 1.13 
Refer to the README.md and LICENCE files for details.

Change-Id: I922914f4e7da7cb939a8054cded11feb9ea51a86
 2016-05-13 15:06:20 +01:00
armvixl
788c84fd2c VIXL Release 1.12 
Refer to the README.md and LICENCE files for details.
 2015-12-08 17:05:23 +00:00
armvixl
684cd2a7f5 VIXL Release 1.11 
Refer to the README.md and LICENCE files for details.
 2015-10-23 13:38:33 +01:00
armvixl
db64434993 VIXL Release 1.10 
Refer to the README.md and LICENCE files for details.
 2015-07-21 11:37:10 +01:00
armvixl
6e2c8275d5 VIXL Release 1.9 
Refer to the README.md and LICENCE files for details.
 2015-03-31 11:04:14 +01:00