Add missing registers to AArch64 sigreturn frame, and update test

This commit is contained in:
Zach Riggle committed 2017-02-10 22:54:24 -05:00
1 parent 6c1b882b40
commit 189b1fb3c2
3 files changed
+13 -7

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+1 -3
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@@ -2,9 +2,7 @@ from pwn import *
context.arch='aarch64'
frame = SigreturnFrame()
registers = ['x%i' % i for i in range(0, 19)]
# registers 19-26 are not included
registers += ['x%i' % i for i in range(27, 31)]
registers = ['x%i' % i for i in range(0, 31)]
registers += ['sp', 'pc']
+3
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@@ -534,6 +534,9 @@ class Corefile(ELF):
if mapping.stop == self.stack:
mapping.name = '[stack]'
self.stack = mapping
else:
log.warn('Could not find the stack!')
self.stack = None
with context.local(bytes=self.bytes, log_level='error'):
try:
+9 -4
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@@ -204,10 +204,15 @@ registers = {
144: 't5', 152: 't6', 160: 't7', 168: 's0', 176: 's1', 184: 's2', 192: 's3', 200: 's4',
208: 's5', 216: 's6', 224: 's7', 232: 't8', 240: 't9', 248: 'k0', 256: 'k1', 264: 'gp',
272: 'sp', 280: 's8', 288: 'ra'},
'aarch64': {312: 'x0', 320: 'x1', 328: 'x2', 336: 'x3', 344: 'x4', 352: 'x5', 360: 'x6',
368: 'x7', 376: 'x8', 384: 'x9', 392: 'x10', 400: 'x11', 408: 'x12', 416: 'x13',
424: 'x14', 432: 'x15', 440: 'x16', 448: 'x17', 456: 'x18', 528: 'x27', 536: 'x28',
544: 'x29', 552: 'x30', 560: 'sp', 568: 'pc', 592: 'magic'}
'aarch64': {312: 'x0', 320: 'x1', 328: 'x2', 336: 'x3',
344: 'x4', 352: 'x5', 360: 'x6', 368: 'x7',
376: 'x8', 384: 'x9', 392: 'x10', 400: 'x11',
408: 'x12', 416: 'x13', 424: 'x14', 432: 'x15',
440: 'x16', 448: 'x17', 456: 'x18', 464: 'x19',
472: 'x20', 480: 'x21', 488: 'x22', 496: 'x23',
504: 'x24', 512: 'x25', 520: 'x26', 528: 'x27',
536: 'x28', 544: 'x29', 552: 'x30', 560: 'sp',
568: 'pc', 592: 'magic'}
}
defaults = {