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Add missing registers to AArch64 sigreturn frame, and update test
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+13
-7
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@@ -2,9 +2,7 @@ from pwn import *
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context.arch='aarch64'
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frame = SigreturnFrame()
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registers = ['x%i' % i for i in range(0, 19)]
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# registers 19-26 are not included
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registers += ['x%i' % i for i in range(27, 31)]
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registers = ['x%i' % i for i in range(0, 31)]
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registers += ['sp', 'pc']
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@@ -534,6 +534,9 @@ class Corefile(ELF):
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if mapping.stop == self.stack:
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mapping.name = '[stack]'
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self.stack = mapping
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else:
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log.warn('Could not find the stack!')
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self.stack = None
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with context.local(bytes=self.bytes, log_level='error'):
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try:
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+9
-4
@@ -204,10 +204,15 @@ registers = {
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144: 't5', 152: 't6', 160: 't7', 168: 's0', 176: 's1', 184: 's2', 192: 's3', 200: 's4',
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208: 's5', 216: 's6', 224: 's7', 232: 't8', 240: 't9', 248: 'k0', 256: 'k1', 264: 'gp',
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272: 'sp', 280: 's8', 288: 'ra'},
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'aarch64': {312: 'x0', 320: 'x1', 328: 'x2', 336: 'x3', 344: 'x4', 352: 'x5', 360: 'x6',
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368: 'x7', 376: 'x8', 384: 'x9', 392: 'x10', 400: 'x11', 408: 'x12', 416: 'x13',
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424: 'x14', 432: 'x15', 440: 'x16', 448: 'x17', 456: 'x18', 528: 'x27', 536: 'x28',
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544: 'x29', 552: 'x30', 560: 'sp', 568: 'pc', 592: 'magic'}
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'aarch64': {312: 'x0', 320: 'x1', 328: 'x2', 336: 'x3',
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344: 'x4', 352: 'x5', 360: 'x6', 368: 'x7',
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376: 'x8', 384: 'x9', 392: 'x10', 400: 'x11',
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408: 'x12', 416: 'x13', 424: 'x14', 432: 'x15',
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440: 'x16', 448: 'x17', 456: 'x18', 464: 'x19',
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472: 'x20', 480: 'x21', 488: 'x22', 496: 'x23',
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504: 'x24', 512: 'x25', 520: 'x26', 528: 'x27',
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536: 'x28', 544: 'x29', 552: 'x30', 560: 'sp',
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568: 'pc', 592: 'magic'}
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}
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defaults = {
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