Non libultra Boot Cleanup (#1370)

* reorganize

* math64

* rcp_utils

* osSyncPrintfUnused

* comment spacing

Makefile

@@ -207,8 +207,7 @@ DEP_FILES := $(O_FILES:.o=.asmproc.d) $(OVL_RELOC_FILES:.o=.d)
 $(shell mkdir -p build/baserom $(foreach dir,$(SRC_DIRS) $(ASM_DIRS) $(ASSET_BIN_DIRS),build/$(dir)))
 
 # directory flags
-build/src/boot_O2/%.o: OPTFLAGS := -O2
-build/src/boot_O2_g3/%.o: OPTFLAGS := -O2 -g3
+build/src/boot/O2/%.o: OPTFLAGS := -O2
 
 build/src/libultra/os/%.o: OPTFLAGS := -O1
 build/src/libultra/voice/%.o: OPTFLAGS := -O2
@@ -225,8 +224,8 @@ build/assets/%.o: OPTFLAGS := -O1
 build/assets/%.o: ASM_PROC_FLAGS := 
 
 # file flags
-build/src/boot_O2_g3/fault.o: CFLAGS += -trapuv
-build/src/boot_O2_g3/fault_drawer.o: CFLAGS += -trapuv
+build/src/boot/fault.o: CFLAGS += -trapuv
+build/src/boot/fault_drawer.o: CFLAGS += -trapuv
 
 build/src/code/jpegutils.o: OPTFLAGS := -O2
 build/src/code/jpegdecoder.o: OPTFLAGS := -O2
@@ -239,8 +238,8 @@ build/src/libultra/libc/llcvt.o: OPTFLAGS := -O1
 build/src/libultra/libc/llcvt.o: MIPS_VERSION := -mips3 -32
 
 # cc & asm-processor
-build/src/boot_O2/%.o: CC := $(ASM_PROC) $(ASM_PROC_FLAGS) $(CC) -- $(AS) $(ASFLAGS) --
-build/src/boot_O2_g3/%.o: CC := $(ASM_PROC) $(ASM_PROC_FLAGS) $(CC) -- $(AS) $(ASFLAGS) --
+build/src/boot/%.o: CC := $(ASM_PROC) $(ASM_PROC_FLAGS) $(CC) -- $(AS) $(ASFLAGS) --
+build/src/boot/O2/%.o: CC := $(ASM_PROC) $(ASM_PROC_FLAGS) $(CC) -- $(AS) $(ASFLAGS) --
 
 build/src/libultra/%.o: CC := $(CC_OLD)
 # Needed at least until voice is decompiled

include/PR/hardware.h

@@ -15,93 +15,8 @@
 // Volatile access wrapper, enforcing uncached memory
 #define HW_REG(reg, type) *(volatile type*)((reg) | KSEG1)
 
-#define AI_DRAM_ADDR_REG   0x04500000
-#define AI_LEN_REG         0x04500004
-#define AI_CONTROL_REG     0x04500008
-#define AI_STATUS_REG      0x0450000C
-#define AI_DACRATE_REG     0x04500010
-#define AI_BITRATE_REG     0x04500014
-
-#define AI_STATUS_AI_BUSY  (1 << 30)
-#define AI_STATUS_AI_FULL  (1 << 31)
-
-#define VI_STATUS_REG          0x04400000
-#define VI_CONTROL_REG         0x04400000
-#define VI_ORIGIN_REG          0x04400004
-#define VI_DRAM_ADDR_REG       0x04400004
-#define VI_WIDTH_REG           0x04400008
-#define VI_H_WIDTH_REG         0x04400008
-#define VI_INTR_REG            0x0440000C
-#define VI_V_INTER_REG         0x0440000C
-#define VI_CURRENT_REG         0x04400010
-#define VI_V_CURRENT_LINE_REG  0x04400010
-#define VI_BURST_REG           0x04400014
-#define VI_TIMING_REG          0x04400014
-#define VI_V_SYNC_REG          0x04400018 //VI vertical sync
-#define VI_H_SYNC_REG          0x0440001C //VI horizontal sync
-#define VI_LEAP_REG            0x04400020 //VI horizontal sync leap
-#define VI_H_SYNC_LEAP_REG     0x04400020
-#define VI_H_START_REG         0x04400024 //VI horizontal video
-#define VI_H_VIDEO_REG         0x04400024
-#define VI_V_START_REG         0x04400028 //VI vertical video
-#define VI_V_VIDEO_REG         0x04400028
-#define VI_V_BURST_REG         0x0440002C //VI vertical burst
-#define VI_X_SCALE_REG         0x04400030 //VI x-scale
-#define VI_Y_SCALE_REG         0x04400034 //VI y-scale
-
-#define SP_IMEM_START  0x04001000
-#define SP_IMEM_SIZE   0x1000
-
-#define SP_DMEM_START  0x04000000
-#define SP_DMEM_SIZE   0x1000
-
 #define TMEM_SIZE 0x1000
 
-#define SP_MEM_ADDR_REG   0x04040000
-#define SP_DRAM_ADDR_REG  0x04040004
-#define SP_RD_LEN_REG     0x04040008
-#define SP_WR_LEN_REG     0x0404000C
-#define SP_STATUS_REG     0x04040010
-#define SP_DMA_FULL_REG   0x04040014
-#define SP_DMA_BUSY_REG   0x04040018
-#define SP_PC_REG         0x04080000
-
-#define PI_DRAM_ADDR_REG     0x04600000 //PI DRAM address
-#define PI_CART_ADDR_REG     0x04600004 //PI pbus (cartridge) address
-#define PI_RD_LEN_REG        0x04600008 //PI read length
-#define PI_WR_LEN_REG        0x0460000C //PI write length
-#define PI_STATUS_REG        0x04600010 //PI status
-#define PI_BSD_DOM1_LAT_REG  0x04600014 //PI dom1 latency
-#define PI_DOMAIN1_REG       0x04600014
-#define PI_BSD_DOM1_PWD_REG  0x04600018 //PI dom1 pulse width
-#define PI_BSD_DOM1_PGS_REG  0x0460001C //PI dom1 page size
-#define PI_BSD_DOM1_RLS_REG  0x04600020 //PI dom1 release
-#define PI_BSD_DOM2_LAT_REG  0x04600024 //PI dom2 latency
-#define PI_DOMAIN2_REG       0x04600024
-#define PI_BSD_DOM2_PWD_REG  0x04600028 //PI dom2 pulse width
-#define PI_BSD_DOM2_PGS_REG  0x0460002C //PI dom2 page size
-#define PI_BSD_DOM2_RLS_REG  0x04600030 //PI dom2 release
-
-#define PI_STATUS_BUSY    (1 << 0)
-#define PI_STATUS_IOBUSY  (1 << 1)
-#define PI_STATUS_ERROR   (1 << 2)
-
-#define PI_STATUS_RESET_CONTROLLER  (1 << 0)
-#define PI_STATUS_CLEAR_INTR        (1 << 1)
-
-#define SI_DRAM_ADDR_REG       0x04800000
-#define SI_PIF_ADDR_RD64B_REG  0x04800004
-#define SI_PIF_ADDR_WR64B_REG  0x04800010
-#define SI_STATUS_REG          0x04800018
-
-#define SI_STATUS_DMA_BUSY      (1 << 0)
-#define SI_STATUS_IO_READ_BUSY  (1 << 1)
-#define SI_STATUS_DMA_ERROR     (1 << 3)
-#define SI_STATUS_INTERRUPT     (1 << 12)
-
-#define PIF_RAM_START  0x1FC007C0
-#define PIF_RAM_SIZE   0x40
-
 #define MI_INIT_MODE_REG  0x04300000
 #define MI_MODE_REG       MI_INIT_MODE_REG
 #define MI_VERSION_REG    0x04300004

include/PR/os_internal.h

@@ -4,6 +4,7 @@
 #include "ultratypes.h"
 #include "os_message.h"
 #include "os_pi.h"
+#include "os_internal_rsp.h"
 
 
 typedef struct {

include/PR/os_internal_reg.h

@@ -1,5 +1,5 @@
-#ifndef PR_OS_INTERNAL_REG
-#define PR_OS_INTERNAL_REG
+#ifndef PR_OS_INTERNAL_REG_H
+#define PR_OS_INTERNAL_REG_H
 
 #include "ultratypes.h"
 #include "os_exception.h"

include/PR/os_internal_rsp.h

@@ -0,0 +1,13 @@
+#ifndef PR_OS_INTERNAL_RSP_H
+#define PR_OS_INTERNAL_RSP_H
+
+#include "ultratypes.h"
+#include "libc/stddef.h"
+
+u32 __osSpGetStatus(void);
+void __osSpSetStatus(u32 data);
+s32 __osSpSetPc(void* pc);
+s32 __osSpRawStartDma(s32 direction, void* devAddr, void* dramAddr, size_t size);
+
+
+#endif

include/PR/rcp.h

@@ -1,15 +1,98 @@
 #ifndef PR_RCP_H
 #define PR_RCP_H
 
+/**
+ * PIF Physical memory map (total size = 2 KB)
+ *
+ *            Size      Description     Mode
+ *  1FC007FF    +-------+-----------------+-----+
+ *              |  64 B | JoyChannel RAM  | R/W |
+ *  1FC007C0    +-------+-----------------+-----+
+ *              |1984 B |    Boot ROM     |  *  |  * = Reserved
+ *  1FC00000    +-------+-----------------+-----+
+ */
+#define PIF_ROM_START   0x1FC00000
+#define PIF_ROM_END     0x1FC007BF
+#define PIF_RAM_START   0x1FC007C0
+#define PIF_RAM_END     0x1FC007FF
+
+/*
+ * Patterns to interpret VI_CONTROL_REG
+ */
+#define VI_CTRL_TYPE_16             0x00002 /* [1:0] pixel size: 16 bit */
+#define VI_CTRL_TYPE_32             0x00003 /* [1:0] pixel size: 32 bit */
+#define VI_CTRL_GAMMA_DITHER_ON     0x00004 /* 2: default = on */
+#define VI_CTRL_GAMMA_ON            0x00008 /* 3: default = on */
+#define VI_CTRL_DIVOT_ON            0x00010 /* 4: default = on */
+#define VI_CTRL_SERRATE_ON          0x00040 /* 6: on if interlaced */
+#define VI_CTRL_ANTIALIAS_MASK      0x00300 /* [9:8] anti-alias mode */
+#define VI_CTRL_ANTIALIAS_MODE_1    0x00100 /* Bit [9:8] anti-alias mode */
+#define VI_CTRL_ANTIALIAS_MODE_2    0x00200 /* Bit [9:8] anti-alias mode */
+#define VI_CTRL_ANTIALIAS_MODE_3    0x00300 /* Bit [9:8] anti-alias mode */
+#define VI_CTRL_PIXEL_ADV_MASK      0x01000 /* [15:12] pixel advance mode? */
+#define VI_CTRL_PIXEL_ADV_1         0x01000 /* Bit [15:12] pixel advance mode? */
+#define VI_CTRL_PIXEL_ADV_2         0x02000 /* Bit [15:12] pixel advance mode? */
+#define VI_CTRL_PIXEL_ADV_3         0x03000 /* Bit [15:12] pixel advance mode? */
+#define VI_CTRL_DITHER_FILTER_ON    0x10000 /* 16: dither-filter mode */
+
+
 #define VI_NTSC_CLOCK       48681812        /* Hz = 48.681812 MHz */
 #define VI_PAL_CLOCK        49656530        /* Hz = 49.656530 MHz */
 #define VI_MPAL_CLOCK       48628316        /* Hz = 48.628316 MHz */
 
-#define DEVICE_TYPE_CART    0   /* ROM cartridge */
-#define DEVICE_TYPE_BULK    1   /* ROM bulk */
-#define DEVICE_TYPE_64DD    2   /* 64 Disk Drive */
-#define DEVICE_TYPE_SRAM    3   /* SRAM */
-#define DEVICE_TYPE_INIT    7   /* initial value */
+/**
+ * Audio Interface (AI) Registers
+ */
+#define AI_BASE_REG     0x04500000
+
+/* AI DRAM address (W): [23:0] starting RDRAM address (8B-aligned) */
+#define AI_DRAM_ADDR_REG    (AI_BASE_REG + 0x00)    /* R0: DRAM address */
+
+/* AI length (R/W): [14:0] transfer length (v1.0) - Bottom 3 bits are ignored */
+/*                  [17:0] transfer length (v2.0) - Bottom 3 bits are ignored */
+#define AI_LEN_REG          (AI_BASE_REG + 0x04)    /* R1: Length */
+
+/* AI control (W): [0] DMA enable - if LSB == 1, DMA is enabled */
+#define AI_CONTROL_REG      (AI_BASE_REG + 0x08)    /* R2: DMA Control */
+
+/* Value for control register */
+#define AI_CONTROL_DMA_ON   1   /* LSB = 1: DMA enable*/
+#define AI_CONTROL_DMA_OFF  0   /* LSB = 1: DMA enable*/
+
+/* 
+ * AI status (R): [31]/[0] ai_full (addr & len buffer full), [30] ai_busy 
+ *        Note that a 1->0 transition in ai_full will set interrupt
+ *           (W): clear audio interrupt 
+ */
+#define AI_STATUS_REG       (AI_BASE_REG + 0x0C)    /* R3: Status */
+
+/* Value for status register */
+#define AI_STATUS_FIFO_FULL (1 << 31)
+#define AI_STATUS_DMA_BUSY  (1 << 30)
+
+/* 
+ * AI DAC sample period register (W): [13:0] dac rate 
+ *   - vid_clock/(dperiod + 1) is the DAC sample rate
+ *   - (dperiod + 1) >= 66 * (aclockhp + 1) must be true
+ */
+#define AI_DACRATE_REG      (AI_BASE_REG + 0x10)    /* R4: DAC rate 14-lsb*/
+
+/* DAC rate = video clock / audio frequency
+ *   - DAC rate >= (66 * Bit rate) must be true
+ */
+#define AI_MAX_DAC_RATE 16384   /* 14-bit+1 */
+#define AI_MIN_DAC_RATE 132
+
+/* 
+ * AI bit rate (W): [3:0] bit rate (abus clock half period register - aclockhp)
+ *   - vid_clock/(2 * (aclockhp + 1)) is the DAC clock rate
+ *   - The abus clock stops if aclockhp is zero
+ */
+#define AI_BITRATE_REG      (AI_BASE_REG + 0x14)    /* R5: Bit rate 4-lsb */
+
+/* Bit rate <= (DAC rate / 66) */
+#define AI_MAX_BIT_RATE 16      /* 4-bit+1 */
+#define AI_MIN_BIT_RATE 2
 
 #define CHNL_ERR_NORESP     0x80    /* Bit 7 (Rx): No response error */
 #define CHNL_ERR_OVERRUN    0x40    /* Bit 6 (Rx): Overrun error */
@@ -18,6 +101,172 @@
 
 #define CHNL_ERR_MASK       0xC0    /* Bit 6-7: channel errors */
 
+#define DEVICE_TYPE_CART    0   /* ROM cartridge */
+#define DEVICE_TYPE_BULK    1   /* ROM bulk */
+#define DEVICE_TYPE_64DD    2   /* 64 Disk Drive */
+#define DEVICE_TYPE_SRAM    3   /* SRAM */
+#define DEVICE_TYPE_INIT    7   /* initial value */
+
+/**
+ * Signal Processor (SP) Memory
+ */
+#define SP_DMEM_START   0x04000000
+#define SP_DMEM_END     0x04000FFF
+#define SP_IMEM_START   0x04001000
+#define SP_IMEM_END     0x04001FFF
+
+#define SP_MEM_ADDR_REG   0x04040000
+#define SP_DRAM_ADDR_REG  0x04040004
+#define SP_RD_LEN_REG     0x04040008
+#define SP_WR_LEN_REG     0x0404000C
+#define SP_STATUS_REG     0x04040010
+#define SP_DMA_FULL_REG   0x04040014
+#define SP_DMA_BUSY_REG   0x04040018
+#define SP_PC_REG         0x04080000
+
+/**
+ * SP_STATUS_REG: write bits
+ */
+#define SP_CLR_HALT        (1 <<  0)
+#define SP_SET_HALT        (1 <<  1)
+#define SP_CLR_BROKE       (1 <<  2)
+#define SP_CLR_INTR        (1 <<  3)
+#define SP_SET_INTR        (1 <<  4)
+#define SP_CLR_SSTEP       (1 <<  5)
+#define SP_SET_SSTEP       (1 <<  6)
+#define SP_CLR_INTR_BREAK  (1 <<  7)
+#define SP_SET_INTR_BREAK  (1 <<  8)
+#define SP_CLR_SIG0        (1 <<  9)
+#define SP_SET_SIG0        (1 << 10)
+#define SP_CLR_SIG1        (1 << 11)
+#define SP_SET_SIG1        (1 << 12)
+#define SP_CLR_SIG2        (1 << 13)
+#define SP_SET_SIG2        (1 << 14)
+#define SP_CLR_SIG3        (1 << 15)
+#define SP_SET_SIG3        (1 << 16)
+#define SP_CLR_SIG4        (1 << 17)
+#define SP_SET_SIG4        (1 << 18)
+#define SP_CLR_SIG5        (1 << 19)
+#define SP_SET_SIG5        (1 << 20)
+#define SP_CLR_SIG6        (1 << 21)
+#define SP_SET_SIG6        (1 << 22)
+#define SP_CLR_SIG7        (1 << 23)
+#define SP_SET_SIG7        (1 << 24)
+
+/*
+ * SP_STATUS_REG: read bits
+ */
+#define SP_STATUS_HALT          (1 <<  0)
+#define SP_STATUS_BROKE         (1 <<  1)
+#define SP_STATUS_DMA_BUSY      (1 <<  2)
+#define SP_STATUS_DMA_FULL      (1 <<  3)
+#define SP_STATUS_IO_FULL       (1 <<  4)
+#define SP_STATUS_SSTEP         (1 <<  5)
+#define SP_STATUS_INTR_BREAK    (1 <<  6)
+#define SP_STATUS_SIG0          (1 <<  7)
+#define SP_STATUS_SIG1          (1 <<  8)
+#define SP_STATUS_SIG2          (1 <<  9)
+#define SP_STATUS_SIG3          (1 << 10)
+#define SP_STATUS_SIG4          (1 << 11)
+#define SP_STATUS_SIG5          (1 << 12)
+#define SP_STATUS_SIG6          (1 << 13)
+#define SP_STATUS_SIG7          (1 << 14)
+
+/**
+ * SP_STATUS_REG: use of SIG bits
+ */
+#define SP_CLR_YIELD            SP_CLR_SIG0
+#define SP_SET_YIELD            SP_SET_SIG0
+#define SP_STATUS_YIELD         SP_STATUS_SIG0
+#define SP_CLR_YIELDED          SP_CLR_SIG1
+#define SP_SET_YIELDED          SP_SET_SIG1
+#define SP_STATUS_YIELDED       SP_STATUS_SIG1
+#define SP_CLR_TASKDONE         SP_CLR_SIG2
+#define SP_SET_TASKDONE         SP_SET_SIG2
+#define SP_STATUS_TASKDONE      SP_STATUS_SIG2
+#define SP_CLR_RSPSIGNAL        SP_CLR_SIG3
+#define SP_SET_RSPSIGNAL        SP_SET_SIG3
+#define SP_STATUS_RSPSIGNAL     SP_STATUS_SIG3
+#define SP_CLR_CPUSIGNAL        SP_CLR_SIG4
+#define SP_SET_CPUSIGNAL        SP_SET_SIG4
+#define SP_STATUS_CPUSIGNAL     SP_STATUS_SIG4
+
+#define VI_STATUS_REG          0x04400000
+#define VI_CONTROL_REG         0x04400000
+#define VI_ORIGIN_REG          0x04400004
+#define VI_DRAM_ADDR_REG       0x04400004
+#define VI_WIDTH_REG           0x04400008
+#define VI_H_WIDTH_REG         0x04400008
+#define VI_INTR_REG            0x0440000C
+#define VI_V_INTER_REG         0x0440000C
+#define VI_CURRENT_REG         0x04400010
+#define VI_V_CURRENT_LINE_REG  0x04400010
+#define VI_BURST_REG           0x04400014
+#define VI_TIMING_REG          0x04400014
+#define VI_V_SYNC_REG          0x04400018 // VI vertical sync
+#define VI_H_SYNC_REG          0x0440001C // VI horizontal sync
+#define VI_LEAP_REG            0x04400020 // VI horizontal sync leap
+#define VI_H_SYNC_LEAP_REG     0x04400020
+#define VI_H_START_REG         0x04400024 // VI horizontal video
+#define VI_H_VIDEO_REG         0x04400024
+#define VI_V_START_REG         0x04400028 // VI vertical video
+#define VI_V_VIDEO_REG         0x04400028
+#define VI_V_BURST_REG         0x0440002C // VI vertical burst
+#define VI_X_SCALE_REG         0x04400030 // VI x-scale
+#define VI_Y_SCALE_REG         0x04400034 // VI y-scale
+
+#define PI_DRAM_ADDR_REG     0x04600000 // PI DRAM address
+#define PI_CART_ADDR_REG     0x04600004 // PI pbus (cartridge) address
+#define PI_RD_LEN_REG        0x04600008 // PI read length
+#define PI_WR_LEN_REG        0x0460000C // PI write length
+#define PI_STATUS_REG        0x04600010 // PI status
+#define PI_BSD_DOM1_LAT_REG  0x04600014 // PI dom1 latency
+#define PI_DOMAIN1_REG       0x04600014
+#define PI_BSD_DOM1_PWD_REG  0x04600018 // PI dom1 pulse width
+#define PI_BSD_DOM1_PGS_REG  0x0460001C // PI dom1 page size
+#define PI_BSD_DOM1_RLS_REG  0x04600020 // PI dom1 release
+#define PI_BSD_DOM2_LAT_REG  0x04600024 // PI dom2 latency
+#define PI_DOMAIN2_REG       0x04600024
+#define PI_BSD_DOM2_PWD_REG  0x04600028 // PI dom2 pulse width
+#define PI_BSD_DOM2_PGS_REG  0x0460002C // PI dom2 page size
+#define PI_BSD_DOM2_RLS_REG  0x04600030 // PI dom2 release
+
+#define PI_STATUS_DMA_BUSY (1 << 0)
+#define PI_STATUS_IO_BUSY  (1 << 1)
+#define PI_STATUS_ERROR    (1 << 2)
+
+/*
+ * PI_STATUS_REG: write bits
+ */
+#define PI_STATUS_RESET     (1 << 0)
+#define PI_SET_RESET        PI_STATUS_RESET
+
+#define PI_STATUS_CLR_INTR  (1 << 1)
+#define PI_CLR_INTR         PI_STATUS_CLR_INTR
+
+#define PI_DMA_BUFFER_SIZE  128
+
+#define PI_DOM1_ADDR1   0x06000000  /* to 0x07FFFFFF */
+#define PI_DOM1_ADDR2   0x10000000  /* to 0x1FBFFFFF */
+#define PI_DOM1_ADDR3   0x1FD00000  /* to 0x7FFFFFFF */
+#define PI_DOM2_ADDR1   0x05000000  /* to 0x05FFFFFF */
+#define PI_DOM2_ADDR2   0x08000000  /* to 0x0FFFFFFF */
+
+/**
+ * Serial Interface (SI) Registers
+ */
+#define SI_BASE_REG             0x04800000
+
+#define SI_DRAM_ADDR_REG        (SI_BASE_REG + 0x00)
+#define SI_PIF_ADDR_RD64B_REG   (SI_BASE_REG + 0x04)
+#define SI_PIF_ADDR_WR64B_REG   (SI_BASE_REG + 0x10)
+#define SI_STATUS_REG           (SI_BASE_REG + 0x18)
+
+#define SI_STATUS_DMA_BUSY      (1 << 0)
+#define SI_STATUS_IO_READ_BUSY  (1 << 1)
+#define SI_STATUS_DMA_ERROR     (1 << 3)
+#define SI_STATUS_INTERRUPT     (1 << 12)
+
 #define IO_READ(addr)       (*(vu32*)PHYS_TO_K1(addr))
 #define IO_WRITE(addr,data) (*(vu32*)PHYS_TO_K1(addr)=(u32)(data))
 

include/PR/rsp.h

@@ -1,58 +0,0 @@
-#ifndef PR_RSP_H
-#define PR_RSP_H
-
-#include "ultratypes.h"
-#include "libc/stddef.h"
-
-
-/* SP Status Flags */
-#define SP_STATUS_HALT        (1 <<  0)
-#define SP_STATUS_BROKE       (1 <<  1)
-#define SP_STATUS_DMA_BUSY    (1 <<  2)
-#define SP_STATUS_DMA_FULL    (1 <<  3)
-#define SP_STATUS_IO_FULL     (1 <<  4)
-#define SP_STATUS_SSTEP       (1 <<  5)
-#define SP_STATUS_INTR_BREAK  (1 <<  6)
-#define SP_STATUS_YIELD       (1 <<  7) // SIG0
-#define SP_STATUS_YIELDED     (1 <<  8) // SIG1
-#define SP_STATUS_TASKDONE    (1 <<  9) // SIG2
-#define SP_STATUS_SIG3        (1 << 10)
-#define SP_STATUS_SIG4        (1 << 11)
-#define SP_STATUS_SIG5        (1 << 12)
-#define SP_STATUS_SIG6        (1 << 13)
-#define SP_STATUS_SIG7        (1 << 14)
-
-#define SP_CLR_HALT        (1 <<  0)
-#define SP_SET_HALT        (1 <<  1)
-#define SP_CLR_BROKE       (1 <<  2)
-#define SP_CLR_INTR        (1 <<  3)
-#define SP_SET_INTR        (1 <<  4)
-#define SP_CLR_SSTEP       (1 <<  5)
-#define SP_SET_SSTEP       (1 <<  6)
-#define SP_CLR_INTR_BREAK  (1 <<  7)
-#define SP_SET_INTR_BREAK  (1 <<  8)
-#define SP_CLR_SIG0        (1 <<  9)
-#define SP_SET_SIG0        (1 << 10)
-#define SP_CLR_SIG1        (1 << 11)
-#define SP_SET_SIG1        (1 << 12)
-#define SP_CLR_SIG2        (1 << 13)
-#define SP_SET_SIG2        (1 << 14)
-#define SP_CLR_SIG3        (1 << 15)
-#define SP_SET_SIG3        (1 << 16)
-#define SP_CLR_SIG4        (1 << 17)
-#define SP_SET_SIG4        (1 << 18)
-#define SP_CLR_SIG5        (1 << 19)
-#define SP_SET_SIG5        (1 << 20)
-#define SP_CLR_SIG6        (1 << 21)
-#define SP_SET_SIG6        (1 << 22)
-#define SP_CLR_SIG7        (1 << 23)
-#define SP_SET_SIG7        (1 << 24)
-
-
-u32 __osSpGetStatus(void);
-void __osSpSetStatus(u32 data);
-s32 __osSpSetPc(void* pc);
-s32 __osSpRawStartDma(s32 direction, void* devAddr, void* dramAddr, size_t size);
-
-
-#endif

include/functions.h

@@ -40,11 +40,11 @@ void CIC6105_PrintRomInfo(void);
 void CIC6105_AddRomInfoFaultPage(void);
 void CIC6105_RemoveRomInfoFaultPage(void);
 void func_800818F4(void);
-void __osSyncVPrintf(const char* fmt, ...);
+void osSyncPrintfUnused(const char* fmt, ...);
 void rmonPrintf(const char* fmt, ...);
 
-void func_80084940(void);
-void func_80084968(void);
+void RcpUtils_PrintRegisterStatus(void);
+void RcpUtils_Reset(void);
 
 void PadUtils_Init(Input* input);
 void func_80085150(void);

include/ultra64.h

@@ -14,7 +14,6 @@
 #include "PR/sptask.h"
 #include "PR/rcp.h"
 #include "PR/rdp.h"
-#include "PR/rsp.h"
 #include "PR/r4300.h"
 #include "PR/ucode.h"
 #include "PR/viint.h"

spec

@@ -13,38 +13,38 @@ endseg
 beginseg
     name "boot"
     address 0x80080060
-    include "build/src/boot_O2_g3/boot_main.o"
+    include "build/src/boot/boot_main.o"
     include "build/data/boot/rspboot.data.o"
-    include "build/src/boot_O2_g3/idle.o"
-    include "build/src/boot_O2_g3/viconfig.o"
+    include "build/src/boot/idle.o"
+    include "build/src/boot/viconfig.o"
     include "build/data/boot/viconfig.data.o"
-    include "build/src/boot_O2_g3/z_std_dma.o"
-    include "build/src/boot_O2_g3/yaz0.o"
-    include "build/src/boot_O2_g3/irqmgr.o"
-    include "build/src/boot_O2_g3/CIC6105.o"
-    include "build/src/boot_O2_g3/syncprintf.o"
-    include "build/src/boot_O2_g3/fault.o"
-    include "build/src/boot_O2_g3/fault_drawer.o"
-    include "build/src/boot_O2/boot_80084940.o"
-    include "build/src/boot_O2/loadfragment.o"
-    include "build/src/boot_O2/loadfragment2.o"
-    include "build/src/boot_O2/padutils.o"
-    include "build/src/boot_O2/stackcheck.o"
-    include "build/src/boot_O2/gfxprint.o"
+    include "build/src/boot/z_std_dma.o"
+    include "build/src/boot/yaz0.o"
+    include "build/src/boot/irqmgr.o"
+    include "build/src/boot/CIC6105.o"
+    include "build/src/boot/syncprintf.o"
+    include "build/src/boot/fault.o"
+    include "build/src/boot/fault_drawer.o"
+    include "build/src/boot/O2/rcp_utils.o"
+    include "build/src/boot/O2/loadfragment.o"
+    include "build/src/boot/O2/loadfragment2.o"
+    include "build/src/boot/O2/padutils.o"
+    include "build/src/boot/O2/stackcheck.o"
+    include "build/src/boot/O2/gfxprint.o"
     include "build/data/boot/gfxprint.data.o"
-    include "build/src/boot_O2/mtxuty-cvt.o"
-    include "build/src/boot_O2/debug.o"
-    include "build/src/boot_O2/system_heap.o"
-    include "build/src/boot_O2/padsetup.o"
-    include "build/src/boot_O2/boot_80086760.o"
+    include "build/src/boot/O2/mtxuty-cvt.o"
+    include "build/src/boot/O2/debug.o"
+    include "build/src/boot/O2/system_heap.o"
+    include "build/src/boot/O2/padsetup.o"
+    include "build/src/boot/O2/math64.o"
     include "build/asm/boot/fp.text.o"
     include "build/data/boot/fp.data.o"
-    include "build/src/boot_O2/system_malloc.o"
-    include "build/src/boot_O2/rand.o"
-    include "build/src/boot_O2/__osMalloc.o"
+    include "build/src/boot/O2/system_malloc.o"
+    include "build/src/boot/O2/rand.o"
+    include "build/src/boot/O2/__osMalloc.o"
     include "build/src/libultra/rmon/sprintf.o"
-    include "build/src/boot_O2/printutils.o"
-    include "build/src/boot_O2/sleep.o"
+    include "build/src/boot/O2/printutils.o"
+    include "build/src/boot/O2/sleep.o"
     include "build/asm/boot/setcause.text.o"
     include "build/src/libultra/os/sendmesg.o"
     include "build/src/libultra/io/pfsfreeblocks.o"
@@ -232,12 +232,12 @@ beginseg
     include "build/src/libultra/os/sethwinterrupt.o"
     include "build/asm/boot/getwatchlo.text.o"
     include "build/asm/boot/setwatchlo.text.o"
-    include "build/src/boot_O2/fmodf.o"
-    include "build/src/boot_O2/__osMemset.o"
-    include "build/src/boot_O2/__osStrcmp.o"
-    include "build/src/boot_O2/__osStrcpy.o"
-    include "build/src/boot_O2/__osMemcpy.o"
-    include "build/src/boot_O2_g3/build.o"
+    include "build/src/boot/O2/fmodf.o"
+    include "build/src/boot/O2/__osMemset.o"
+    include "build/src/boot/O2/__osStrcmp.o"
+    include "build/src/boot/O2/__osStrcpy.o"
+    include "build/src/boot/O2/__osMemcpy.o"
+    include "build/src/boot/build.o"
 endseg
 
 beginseg

src/audio/lib/aisetnextbuf.c

@@ -19,7 +19,7 @@ s32 osAiSetNextBuffer(void* buf, u32 size) {
 
     // Originally a call to __osAiDeviceBusy
     status = HW_REG(AI_STATUS_REG, s32);
-    if (status & AI_STATUS_AI_FULL) {
+    if (status & AI_STATUS_FIFO_FULL) {
         return -1;
     }
 

src/boot/O2/rcp_utils.c

@@ -0,0 +1,23 @@
+#include "ultra64.h"
+
+void RcpUtils_PrintRegisterStatus(void) {
+    u32 spStatus = __osSpGetStatus();
+    u32 dpStatus = osDpGetStatus();
+
+    if (spStatus) {
+        // stubbed debug prints
+    }
+
+    if (dpStatus) {
+        // stubbed debug prints
+    }
+}
+
+void RcpUtils_Reset(void) {
+    RcpUtils_PrintRegisterStatus();
+    // Flush the RDP pipeline and freeze clock counter
+    osDpSetStatus(DPC_SET_FREEZE | DPC_SET_FLUSH);
+    // Halt the RSP, disable interrupt on break and set "task done" signal
+    __osSpSetStatus(SP_SET_HALT | SP_SET_TASKDONE | SP_CLR_INTR_BREAK);
+    RcpUtils_PrintRegisterStatus();
+}

src/boot/syncprintf.c

@@ -1,7 +1,6 @@
 #include "global.h"
 
-// This isn't a vprintf since it doesn't take a va_list
-void __osSyncVPrintf(const char* fmt, ...) {
+void osSyncPrintfUnused(const char* fmt, ...) {
 }
 
 void osSyncPrintf(const char* fmt, ...) {

src/boot_O2/boot_80084940.c

@@ -1,15 +0,0 @@
-#include "global.h"
-
-void func_80084940(void) {
-    u32 spStatus = __osSpGetStatus();
-    u32 dpStatus = osDpGetStatus();
-
-    if (spStatus && dpStatus) {} // stubbed debug prints
-}
-
-void func_80084968(void) {
-    func_80084940();
-    osDpSetStatus(0x28);
-    __osSpSetStatus(0x4082);
-    func_80084940();
-}

src/libultra/io/cartrominit.c

@@ -28,7 +28,7 @@ OSPiHandle* osCartRomInit(void) {
     bzero(&CartRomHandle.transferInfo, sizeof(__OSTranxInfo));
 
     /* Uses `status & PI_STATUS_ERROR` in OoT */
-    while (status = HW_REG(PI_STATUS_REG, u32), status & (PI_STATUS_BUSY | PI_STATUS_IOBUSY)) {
+    while (status = HW_REG(PI_STATUS_REG, u32), status & (PI_STATUS_DMA_BUSY | PI_STATUS_IO_BUSY)) {
         ;
     }
 

src/libultra/io/devmgr.c

@@ -51,7 +51,7 @@ void __osDevMgrMain(void* arg) {
                     __osEPiRawWriteIo(ioMesg->piHandle, 0x05000510, transfer->bmCtlShadow | 0x1000000);
                 }
                 block->errStatus = 4;
-                HW_REG(PI_STATUS_REG, u32) = PI_STATUS_CLEAR_INTR;
+                HW_REG(PI_STATUS_REG, u32) = PI_CLR_INTR;
                 __osSetGlobalIntMask(0x00100C01);
             }
             osSendMesg(ioMesg->hdr.retQueue, (OSMesg)ioMesg, OS_MESG_NOBLOCK);

src/libultra/io/epirawdma.c

@@ -4,7 +4,7 @@ s32 __osEPiRawStartDma(OSPiHandle* handle, s32 direction, uintptr_t cartAddr, vo
     s32 status;
     OSPiHandle* curHandle;
 
-    while (status = HW_REG(PI_STATUS_REG, u32), status & (PI_STATUS_BUSY | PI_STATUS_IOBUSY)) {
+    while (status = HW_REG(PI_STATUS_REG, u32), status & (PI_STATUS_DMA_BUSY | PI_STATUS_IO_BUSY)) {
         ;
     }
 

src/libultra/io/epirawread.c

@@ -4,7 +4,7 @@ s32 __osEPiRawReadIo(OSPiHandle* handle, uintptr_t devAddr, u32* data) {
     s32 status;
     OSPiHandle* curHandle;
 
-    while (status = HW_REG(PI_STATUS_REG, u32), status & (PI_STATUS_BUSY | PI_STATUS_IOBUSY)) {
+    while (status = HW_REG(PI_STATUS_REG, u32), status & (PI_STATUS_DMA_BUSY | PI_STATUS_IO_BUSY)) {
         ;
     }
 

src/libultra/io/epirawwrite.c

@@ -4,7 +4,7 @@ s32 __osEPiRawWriteIo(OSPiHandle* handle, uintptr_t devAddr, u32 data) {
     s32 status;
     OSPiHandle* curHandle;
 
-    while (status = HW_REG(PI_STATUS_REG, u32), status & (PI_STATUS_BUSY | PI_STATUS_IOBUSY)) {}
+    while (status = HW_REG(PI_STATUS_REG, u32), status & (PI_STATUS_DMA_BUSY | PI_STATUS_IO_BUSY)) {}
 
     if (__osCurrentHandle[handle->domain]->type != handle->type) {
         curHandle = __osCurrentHandle[handle->domain];

src/libultra/io/pirawdma.c

@@ -3,7 +3,7 @@
 s32 __osPiRawStartDma(s32 direction, uintptr_t devAddr, void* dramAddr, size_t size) {
     register int status = HW_REG(PI_STATUS_REG, u32);
 
-    while (status & (PI_STATUS_IOBUSY | PI_STATUS_BUSY)) {
+    while (status & (PI_STATUS_IO_BUSY | PI_STATUS_DMA_BUSY)) {
         status = HW_REG(PI_STATUS_REG, u32);
     }
 

src/libultra/io/sirawdma.c

@@ -6,7 +6,7 @@ s32 __osSiRawStartDma(s32 direction, void* dramAddr) {
     }
 
     if (direction == OS_WRITE) {
-        osWritebackDCache(dramAddr, PIF_RAM_SIZE);
+        osWritebackDCache(dramAddr, ALIGN16(PIF_RAM_END - PIF_RAM_START));
     }
 
     HW_REG(SI_DRAM_ADDR_REG, u32) = osVirtualToPhysical(dramAddr);
@@ -18,7 +18,7 @@ s32 __osSiRawStartDma(s32 direction, void* dramAddr) {
     }
 
     if (direction == OS_READ) {
-        osInvalDCache(dramAddr, PIF_RAM_SIZE);
+        osInvalDCache(dramAddr, ALIGN16(PIF_RAM_END - PIF_RAM_START));
     }
     return 0;
 }

tools/disasm/files.txt

@@ -49,7 +49,7 @@
             0x80081920 : "syncprintf",
             0x80081980 : "fault",
             0x80083EB0 : "fault_drawer",
-            0x80084940 : "boot_80084940",
+            0x80084940 : "rcp_utils",
             0x800849A0 : "loadfragment",
             0x80084DB0 : "loadfragment2",
             0x80085130 : "padutils",
@@ -59,7 +59,7 @@
             0x80086280 : "debug",
             0x800862E0 : "system_heap",
             0x80086620 : "padsetup",
-            0x80086760 : "boot_80086760",
+            0x80086760 : "math64",
             0x80086C70 : "fp",
             0x80086DD0 : "system_malloc",
             0x80086FA0 : "rand",
@@ -297,7 +297,7 @@
             0x80098C50 : "fault_drawer",
             0x80099090 : "gfxprint",
             0x800990B0 : "debug",
-            0x800990C0 : "boot_80086760",
+            0x800990C0 : "math64",
             0x80099110 : "__osMalloc",
             0x800991A0 : "setintmask",
             0x80099220 : "sinf",
@@ -320,7 +320,7 @@
             0x8009BE30 : "CIC6105",
             0x8009BE50 : "fault",
             0x8009CCD0 : "fault_drawer",
-            0x8009CD10 : "boot_80086760",
+            0x8009CD10 : "math64",
             0x8009CD20 : "system_malloc",
             0x8009CD50 : "rand",
             0x8009CD60 : "__osMalloc",

tools/disasm/functions.txt

@@ -46,7 +46,7 @@
     0x8008189C:("CIC6105_AddRomInfoFaultPage",),
     0x800818D0:("CIC6105_RemoveRomInfoFaultPage",),
     0x800818F4:("func_800818F4",),
-    0x80081920:("__osSyncVPrintf",),
+    0x80081920:("osSyncPrintfUnused",),
     0x8008193C:("osSyncPrintf",),
     0x80081958:("rmonPrintf",),
     0x80081980:("Fault_SleepImpl",),
@@ -107,8 +107,8 @@
     0x8008486C:("FaultDrawer_SetDrawerFrameBuffer",),
     0x800848A4:("FaultDrawer_SetInputCallback",),
     0x800848B8:("FaultDrawer_Init",),
-    0x80084940:("func_80084940",),
-    0x80084968:("func_80084968",),
+    0x80084940:("RcpUtils_PrintRegisterStatus",),
+    0x80084968:("RcpUtils_Reset",),
     0x800849A0:("Fragment_Relocate",),
     0x80084C0C:("Fragment_Load",),
     0x80084CD0:("Fragment_AllocateAndLoad",),

tools/sizes/boot_functions.csv

@@ -43,7 +43,7 @@ asm/non_matchings/boot/CIC6105/CIC6105_PrintRomInfo.s,CIC6105_PrintRomInfo,0x800
 asm/non_matchings/boot/CIC6105/CIC6105_AddRomInfoFaultPage.s,CIC6105_AddRomInfoFaultPage,0x8008189C,0xD
 asm/non_matchings/boot/CIC6105/CIC6105_RemoveRomInfoFaultPage.s,CIC6105_RemoveRomInfoFaultPage,0x800818D0,0x9
 asm/non_matchings/boot/CIC6105/func_800818F4.s,func_800818F4,0x800818F4,0xB
-asm/non_matchings/boot/syncprintf/__osSyncVPrintf.s,__osSyncVPrintf,0x80081920,0x7
+asm/non_matchings/boot/syncprintf/osSyncPrintfUnused.s,osSyncPrintfUnused,0x80081920,0x7
 asm/non_matchings/boot/syncprintf/osSyncPrintf.s,osSyncPrintf,0x8008193C,0x7
 asm/non_matchings/boot/syncprintf/rmonPrintf.s,rmonPrintf,0x80081958,0xA
 asm/non_matchings/boot/fault/Fault_SleepImpl.s,Fault_SleepImpl,0x80081980,0x1C
@@ -104,8 +104,8 @@ asm/non_matchings/boot/fault_drawer/FaultDrawer_DrawText.s,FaultDrawer_DrawText,
 asm/non_matchings/boot/fault_drawer/FaultDrawer_SetDrawerFrameBuffer.s,FaultDrawer_SetDrawerFrameBuffer,0x8008486C,0xE
 asm/non_matchings/boot/fault_drawer/FaultDrawer_SetInputCallback.s,FaultDrawer_SetInputCallback,0x800848A4,0x5
 asm/non_matchings/boot/fault_drawer/FaultDrawer_Init.s,FaultDrawer_Init,0x800848B8,0x22
-asm/non_matchings/boot/boot_80084940/func_80084940.s,func_80084940,0x80084940,0xA
-asm/non_matchings/boot/boot_80084940/func_80084968.s,func_80084968,0x80084968,0xE
+asm/non_matchings/boot/rcp_utils/RcpUtils_PrintRegisterStatus.s,RcpUtils_PrintRegisterStatus,0x80084940,0xA
+asm/non_matchings/boot/rcp_utils/RcpUtils_Reset.s,RcpUtils_Reset,0x80084968,0xE
 asm/non_matchings/boot/loadfragment/Fragment_Relocate.s,Fragment_Relocate,0x800849A0,0x9B
 asm/non_matchings/boot/loadfragment/Fragment_Load.s,Fragment_Load,0x80084C0C,0x31
 asm/non_matchings/boot/loadfragment/Fragment_AllocateAndLoad.s,Fragment_AllocateAndLoad,0x80084CD0,0x38
@@ -163,19 +163,19 @@ asm/non_matchings/boot/boot_800862E0/SystemHeap_RunBlockFunc1Reverse.s,SystemHea
 asm/non_matchings/boot/boot_800862E0/SystemHeap_RunInits.s,SystemHeap_RunInits,0x80086588,0x1C
 asm/non_matchings/boot/boot_800862E0/SystemHeap_Init.s,SystemHeap_Init,0x800865F8,0xA
 asm/non_matchings/boot/padsetup/PadSetup_Init.s,PadSetup_Init,0x80086620,0x50
-asm/non_matchings/boot/boot_80086760/Math_FTanF.s,Math_FTanF,0x80086760,0xD
-asm/non_matchings/boot/boot_80086760/Math_FFloorF.s,Math_FFloorF,0x80086794,0x8
-asm/non_matchings/boot/boot_80086760/Math_FCeilF.s,Math_FCeilF,0x800867B4,0x8
-asm/non_matchings/boot/boot_80086760/Math_FRoundF.s,Math_FRoundF,0x800867D4,0x8
-asm/non_matchings/boot/boot_80086760/Math_FTruncF.s,Math_FTruncF,0x800867F4,0x8
-asm/non_matchings/boot/boot_80086760/Math_FNearbyIntF.s,Math_FNearbyIntF,0x80086814,0x8
-asm/non_matchings/boot/boot_80086760/Math_FAtanTaylorQF.s,Math_FAtanTaylorQF,0x80086834,0x13
-asm/non_matchings/boot/boot_80086760/Math_FAtanTaylorF.s,Math_FAtanTaylorF,0x80086880,0x49
-asm/non_matchings/boot/boot_80086760/Math_FAtanContFracF.s,Math_FAtanContFracF,0x800869A4,0x53
-asm/non_matchings/boot/boot_80086760/Math_FAtanF.s,Math_FAtanF,0x80086AF0,0x10
-asm/non_matchings/boot/boot_80086760/Math_FAtan2F.s,Math_FAtan2F,0x80086B30,0x3A
-asm/non_matchings/boot/boot_80086760/Math_FAsinF.s,Math_FAsinF,0x80086C18,0xC
-asm/non_matchings/boot/boot_80086760/Math_FAcosF.s,Math_FAcosF,0x80086C48,0xA
+asm/non_matchings/boot/math64/Math_FTanF.s,Math_FTanF,0x80086760,0xD
+asm/non_matchings/boot/math64/Math_FFloorF.s,Math_FFloorF,0x80086794,0x8
+asm/non_matchings/boot/math64/Math_FCeilF.s,Math_FCeilF,0x800867B4,0x8
+asm/non_matchings/boot/math64/Math_FRoundF.s,Math_FRoundF,0x800867D4,0x8
+asm/non_matchings/boot/math64/Math_FTruncF.s,Math_FTruncF,0x800867F4,0x8
+asm/non_matchings/boot/math64/Math_FNearbyIntF.s,Math_FNearbyIntF,0x80086814,0x8
+asm/non_matchings/boot/math64/Math_FAtanTaylorQF.s,Math_FAtanTaylorQF,0x80086834,0x13
+asm/non_matchings/boot/math64/Math_FAtanTaylorF.s,Math_FAtanTaylorF,0x80086880,0x49
+asm/non_matchings/boot/math64/Math_FAtanContFracF.s,Math_FAtanContFracF,0x800869A4,0x53
+asm/non_matchings/boot/math64/Math_FAtanF.s,Math_FAtanF,0x80086AF0,0x10
+asm/non_matchings/boot/math64/Math_FAtan2F.s,Math_FAtan2F,0x80086B30,0x3A
+asm/non_matchings/boot/math64/Math_FAsinF.s,Math_FAsinF,0x80086C18,0xC
+asm/non_matchings/boot/math64/Math_FAcosF.s,Math_FAcosF,0x80086C48,0xA
 asm/non_matchings/boot/fp/floorf.s,floorf,0x80086C70,0x3
 asm/non_matchings/boot/fp/floor.s,floor,0x80086C7C,0x3
 asm/non_matchings/boot/fp/lfloorf.s,lfloorf,0x80086C88,0x4