mirror of
https://github.com/AngheloAlf/drmario64.git
synced 2024-11-23 04:59:55 +00:00
Update slinky and move custom scripts to the slinky yaml
This commit is contained in:
angie
parent
36281938e3
commit
80eb52110f
2
Makefile
2
Makefile
@ -259,7 +259,7 @@ SEGMENTS_D := $(SEGMENTS_SCRIPTS:.ld=.d)
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SEGMENTS := $(foreach f, $(SEGMENTS_SCRIPTS:.ld=), $(notdir $f))
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SEGMENTS_O := $(foreach f, $(SEGMENTS), $(BUILD_DIR)/segments/$f.o)
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LINKER_SCRIPTS := $(LD_SCRIPT) $(BUILD_DIR)/linker_scripts/$(VERSION)/hardware_regs.ld $(BUILD_DIR)/linker_scripts/$(VERSION)/undefined_syms.ld $(BUILD_DIR)/linker_scripts/common_undef_syms.ld
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LINKER_SCRIPTS := $(LD_SCRIPT)
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# Automatic dependency files
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@ -1 +1 @@
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dd291b9c65420fd892107f6c665b7a45 build/cn/drmario64.cn.z64
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e5c5b7d72a704e138999a638b35841f2 build/cn/drmario64.cn.z64
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@ -126,7 +126,6 @@ options:
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# asm_end_label: endlabel
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asm_jtbl_label_macro: jlabel
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asm_data_macro: dlabel
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include_macro_inc: False
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libultra_symbols: True
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ique_symbols: True
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hardware_regs: True
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@ -1 +1 @@
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697db27690b4f031cf91f28bc445a29f build/gw/drmario64.gw.z64
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28e91d332d2e67bf4db761fa91af664a build/gw/drmario64.gw.z64
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@ -125,7 +125,6 @@ options:
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# asm_end_label: endlabel
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asm_jtbl_label_macro: jlabel
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asm_data_macro: dlabel
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include_macro_inc: False
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libultra_symbols: True
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hardware_regs: True
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image_type_in_extension: True
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@ -124,7 +124,6 @@ options:
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# asm_end_label: endlabel
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asm_jtbl_label_macro: jlabel
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asm_data_macro: dlabel
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include_macro_inc: False
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libultra_symbols: True
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hardware_regs: True
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image_type_in_extension: True
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@ -1 +1 @@
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c708eff785631463ffc027b32b43bed5 build/us/drmario64_uncompressed.us.z64
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acd9547e4f219cb16e6500f8a46bc120 build/us/drmario64_uncompressed.us.z64
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@ -30,6 +30,10 @@
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.globl x ;\
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x:
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#define ABS(x, y) \
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.globl x ;\
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x = y
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.macro move dst, src
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addu \dst, \src, $zero
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.endm
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@ -1,128 +0,0 @@
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// Signal Processor Registers
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SP_MEM_ADDR_REG = 0xA4040000; // defined:True
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SP_DRAM_ADDR_REG = 0xA4040004; // defined:True
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SP_RD_LEN_REG = 0xA4040008; // defined:True
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SP_WR_LEN_REG = 0xA404000C; // defined:True
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SP_STATUS_REG = 0xA4040010; // defined:True
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SP_DMA_FULL_REG = 0xA4040014; // defined:True
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SP_DMA_BUSY_REG = 0xA4040018; // defined:True
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SP_SEMAPHORE_REG = 0xA404001C; // defined:True
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SP_PC = 0xA4080000; // defined:True
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// Display Processor Command Registers / Rasterizer Interface
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DPC_START_REG = 0xA4100000; // defined:True
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DPC_END_REG = 0xA4100004; // defined:True
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DPC_CURRENT_REG = 0xA4100008; // defined:True
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DPC_STATUS_REG = 0xA410000C; // defined:True
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DPC_CLOCK_REG = 0xA4100010; // defined:True
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DPC_BUFBUSY_REG = 0xA4100014; // defined:True
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DPC_PIPEBUSY_REG = 0xA4100018; // defined:True
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DPC_TMEM_REG = 0xA410001C; // defined:True
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// Display Processor Span Registers
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DPS_TBIST_REG = 0xA4200000; // defined:True // DPS_TBIST_REG / DP_TMEM_BIST
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DPS_TEST_MODE_REG = 0xA4200004; // defined:True
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DPS_BUFTEST_ADDR_REG = 0xA4200008; // defined:True
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DPS_BUFTEST_DATA_REG = 0xA420000C; // defined:True
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// MIPS Interface Registers
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MI_MODE_REG = 0xA4300000; // defined:True // MI_MODE_REG / MI_INIT_MODE_REG
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MI_VERSION_REG = 0xA4300004; // defined:True
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MI_INTR_REG = 0xA4300008; // defined:True
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MI_INTR_MASK_REG = 0xA430000C; // defined:True
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D_A4300010 = 0xA4300010; // defined:True
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MI_SK_EXCEPTION_REG = 0xA4300014; // defined:True
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MI_SK_WATCHDOG_TIMER = 0xA4300018; // defined:True
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D_A4300028 = 0xA4300028; // defined:True
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MI_RANDOM_BIT = 0xA430002C; // defined:True
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D_A4300030 = 0xA4300030; // defined:True
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MI_HW_INTR_REG = 0xA4300038; // defined:True
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MI_HW_INTR_MASK_REG = 0xA430003C; // defined:True
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// Video Interface Registers
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VI_STATUS_REG = 0xA4400000; // defined:True // VI_STATUS_REG / VI_CONTROL_REG
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VI_DRAM_ADDR_REG = 0xA4400004; // defined:True // VI_DRAM_ADDR_REG / VI_ORIGIN_REG
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VI_WIDTH_REG = 0xA4400008; // defined:True
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VI_INTR_REG = 0xA440000C; // defined:True
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VI_CURRENT_REG = 0xA4400010; // defined:True
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VI_BURST_REG = 0xA4400014; // defined:True // VI_BURST_REG / VI_TIMING_REG
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VI_V_SYNC_REG = 0xA4400018; // defined:True
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VI_H_SYNC_REG = 0xA440001C; // defined:True
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VI_LEAP_REG = 0xA4400020; // defined:True
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VI_H_START_REG = 0xA4400024; // defined:True
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VI_V_START_REG = 0xA4400028; // defined:True
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VI_V_BURST_REG = 0xA440002C; // defined:True
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VI_X_SCALE_REG = 0xA4400030; // defined:True
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VI_Y_SCALE_REG = 0xA4400034; // defined:True
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// Audio Interface Registers
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AI_DRAM_ADDR_REG = 0xA4500000; // defined:True
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AI_LEN_REG = 0xA4500004; // defined:True
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AI_CONTROL_REG = 0xA4500008; // defined:True
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AI_STATUS_REG = 0xA450000C; // defined:True
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AI_DACRATE_REG = 0xA4500010; // defined:True
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AI_BITRATE_REG = 0xA4500014; // defined:True
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// Peripheral/Parallel Interface Registers
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PI_DRAM_ADDR_REG = 0xA4600000; // defined:True
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PI_CART_ADDR_REG = 0xA4600004; // defined:True
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PI_RD_LEN_REG = 0xA4600008; // defined:True
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PI_WR_LEN_REG = 0xA460000C; // defined:True
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PI_STATUS_REG = 0xA4600010; // defined:True
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PI_BSD_DOM1_LAT_REG = 0xA4600014; // defined:True // PI dom1 latency
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PI_BSD_DOM1_PWD_REG = 0xA4600018; // defined:True // PI dom1 pulse width
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PI_BSD_DOM1_PGS_REG = 0xA460001C; // defined:True // PI dom1 page size
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PI_BSD_DOM1_RLS_REG = 0xA4600020; // defined:True // PI dom1 release
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PI_BSD_DOM2_LAT_REG = 0xA4600024; // defined:True // PI dom2 latency
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PI_BSD_DOM2_LWD_REG = 0xA4600028; // defined:True // PI dom2 pulse width
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PI_BSD_DOM2_PGS_REG = 0xA460002C; // defined:True // PI dom2 page size
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PI_BSD_DOM2_RLS_REG = 0xA4600030; // defined:True // PI dom2 release
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PI_CARD_STATUS_REG = 0xA4600038; // defined:True
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PI_ATB_NEXT_CONFIG = 0xA4600040; // defined:True
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D_A4600044 = 0xA4600044; // defined:True
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PI_CARD_CNT_REG = 0xA4600048; // defined:True
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PI_CARD_CONFIG_REG = 0xA460004C; // defined:True
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PI_AES_CNT = 0xA4600050; // defined:True
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PI_ALLOWED_IO = 0xA4600054; // defined:True
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PI_EX_RD_LEN_REG = 0xA4600058; // defined:True
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PI_EX_WR_LEN_REG = 0xA460005C; // defined:True
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PI_MISC_REG = 0xA4600060; // defined:True
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D_A4600064 = 0xA4600064; // defined:True
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PI_CARD_BLK_OFFSET_REG = 0xA4600070; // defined:True
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PI_EX_DMA_BUF = 0xA4610000; // defined:True
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PI_AES_EXPANDED_KEY = 0xA4610420; // defined:True
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PI_AES_IV = 0xA46104D0; // defined:True
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PI_ATB_ENTRY = 0xA4610500; // defined:True
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D_A4620000 = 0xA4620000; // defined:True
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PI_RDB_REQ_HI_REG = 0xA46E0000; // defined:True
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PI_RDB_REQ_LO_REG = 0xA46E0002; // defined:True
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D_A46E0004 = 0xA46E0004; // defined:True
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D_A46E0400 = 0xA46E0400; // defined:True
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D_A46E0402 = 0xA46E0402; // defined:True
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PI_RDB_STATUS_REG = 0xA46E8000; // defined:True
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// RDRAM Interface Registers
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RI_MODE_REG = 0xA4700000; // defined:True
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RI_CONFIG_REG = 0xA4700004; // defined:True
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RI_CURRENT_LOAD_REG = 0xA4700008; // defined:True
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RI_SELECT_REG = 0xA470000C; // defined:True
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RI_REFRESH_REG = 0xA4700010; // defined:True
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RI_LATENCY_REG = 0xA4700014; // defined:True
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RI_RERROR_REG = 0xA4700018; // defined:True
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RI_WERROR_REG = 0xA470001C; // defined:True
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// Serial Interface Registers
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SI_DRAM_ADDR_REG = 0xA4800000; // defined:True
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SI_PIF_ADDR_RD64B_REG = 0xA4800004; // defined:True
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D_A4800008 = 0xA4800008; // defined:True // reserved
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D_A480000C = 0xA480000C; // defined:True // reserved
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SI_PIF_ADDR_WR64B_REG = 0xA4800010; // defined:True
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D_A4800014 = 0xA4800014; // defined:True // reserved
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SI_STATUS_REG = 0xA4800018; // defined:True
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D_A480001C = 0xA480001C; // defined:True
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D_A4900000 = 0xA4900000; // defined:True
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USB0_STATUS_REG = 0xA4940010; // defined:True
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D_A4A00000 = 0xA4A00000; // defined:True
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USB1_STATUS_REG = 0xA4A40010; // defined:True
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@ -1,30 +0,0 @@
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ROMHEADER_CHECKSUM1 = 0xEF62A343;
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ROMHEADER_CHECKSUM2 = 0x11E41E37;
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// libultra symbols
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leoBootID = 0x800001A0;
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osTvType = 0x80000300;
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osRomType = 0x80000304;
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osRomBase = 0x80000308;
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osResetType = 0x8000030C;
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osCicId = 0x80000310;
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osVersion = 0x80000314;
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osMemSize = 0x80000318;
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osAppNMIBuffer = 0x8000031C;
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__osBbEepromAddress = 0x8000035c;
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__osBbEepromSize = 0x80000360;
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__osBbFlashAddress = 0x80000364;
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__osBbFlashSize = 0x80000368;
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__osBbSramAddress = 0x8000036c;
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__osBbSramSize = 0x80000370;
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__osBbPakAddress = 0x80000374;
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__osBbPakSize = 0x80000384;
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__osBbIsBb = 0x80000388;
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__osBbHackFlags = 0x8000038c;
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__osBbStashMagic = 0x80000390;
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__osBbPakBindings = 0x80000394;
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__osBbStateName = 0x800003a4;
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__osBbStateDirty = 0x800003b4;
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__osBbAuxDataLimit = 0x800003b8;
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@ -1,26 +0,0 @@
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#include "hasm.h"
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boot_BSS_START_HI = boot_BSS_START >> 16;
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boot_BSS_START_LO = boot_BSS_START & 0xFFFF;
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boot_BSS_SIZE_HI = boot_BSS_SIZE >> 16;
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boot_BSS_SIZE_LO = boot_BSS_SIZE & 0xFFFF;
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bootproc_HI = bootproc >> 16;
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bootproc_LO = bootproc & 0xFFFF;
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gBootThreadStack_HI = gBootThreadStack >> 16;
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gBootThreadStack_LO = gBootThreadStack & 0xFFFF;
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gBootThreadStackTop = gBootThreadStack + BOOT_STACK_SIZE;
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gBootThreadStackTop_HI = gBootThreadStackTop >> 16;
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gBootThreadStackTop_LO = gBootThreadStackTop & 0xFFFF;
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ASSERT ((boot_ROM_END <= 0x101000), "Error: boot_ROM_END is larger than 1 MB");
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ASSERT ((buffer1_VRAM_END <= 0x80205000), "Error: The segment 'buffer1' is overflowing the ram limit");
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ASSERT ((buffer2_BSS_START == 0x80205000), "Error: buffer2 shifted?");
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ASSERT ((framebuffer_BSS_START == 0x803B5000), "Error: framebuffer shifted?");
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ENTRY(entrypoint);
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@ -1,94 +0,0 @@
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// Signal Processor Registers
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SP_MEM_ADDR_REG = 0xA4040000; // defined:True
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SP_DRAM_ADDR_REG = 0xA4040004; // defined:True
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SP_RD_LEN_REG = 0xA4040008; // defined:True
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SP_WR_LEN_REG = 0xA404000C; // defined:True
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SP_STATUS_REG = 0xA4040010; // defined:True
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SP_DMA_FULL_REG = 0xA4040014; // defined:True
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SP_DMA_BUSY_REG = 0xA4040018; // defined:True
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SP_SEMAPHORE_REG = 0xA404001C; // defined:True
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SP_PC = 0xA4080000; // defined:True
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// Display Processor Command Registers / Rasterizer Interface
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DPC_START_REG = 0xA4100000; // defined:True
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DPC_END_REG = 0xA4100004; // defined:True
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DPC_CURRENT_REG = 0xA4100008; // defined:True
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DPC_STATUS_REG = 0xA410000C; // defined:True
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DPC_CLOCK_REG = 0xA4100010; // defined:True
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DPC_BUFBUSY_REG = 0xA4100014; // defined:True
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DPC_PIPEBUSY_REG = 0xA4100018; // defined:True
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DPC_TMEM_REG = 0xA410001C; // defined:True
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// Display Processor Span Registers
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DPS_TBIST_REG = 0xA4200000; // defined:True // DPS_TBIST_REG / DP_TMEM_BIST
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DPS_TEST_MODE_REG = 0xA4200004; // defined:True
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DPS_BUFTEST_ADDR_REG = 0xA4200008; // defined:True
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DPS_BUFTEST_DATA_REG = 0xA420000C; // defined:True
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// MIPS Interface Registers
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MI_MODE_REG = 0xA4300000; // defined:True // MI_MODE_REG / MI_INIT_MODE_REG
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MI_VERSION_REG = 0xA4300004; // defined:True
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MI_INTR_REG = 0xA4300008; // defined:True
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MI_INTR_MASK_REG = 0xA430000C; // defined:True
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// Video Interface Registers
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VI_STATUS_REG = 0xA4400000; // defined:True // VI_STATUS_REG / VI_CONTROL_REG
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VI_DRAM_ADDR_REG = 0xA4400004; // defined:True // VI_DRAM_ADDR_REG / VI_ORIGIN_REG
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VI_WIDTH_REG = 0xA4400008; // defined:True
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VI_INTR_REG = 0xA440000C; // defined:True
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VI_CURRENT_REG = 0xA4400010; // defined:True
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VI_BURST_REG = 0xA4400014; // defined:True // VI_BURST_REG / VI_TIMING_REG
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VI_V_SYNC_REG = 0xA4400018; // defined:True
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VI_H_SYNC_REG = 0xA440001C; // defined:True
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VI_LEAP_REG = 0xA4400020; // defined:True
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VI_H_START_REG = 0xA4400024; // defined:True
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VI_V_START_REG = 0xA4400028; // defined:True
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VI_V_BURST_REG = 0xA440002C; // defined:True
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VI_X_SCALE_REG = 0xA4400030; // defined:True
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VI_Y_SCALE_REG = 0xA4400034; // defined:True
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// Audio Interface Registers
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AI_DRAM_ADDR_REG = 0xA4500000; // defined:True
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AI_LEN_REG = 0xA4500004; // defined:True
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AI_CONTROL_REG = 0xA4500008; // defined:True
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AI_STATUS_REG = 0xA450000C; // defined:True
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AI_DACRATE_REG = 0xA4500010; // defined:True
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AI_BITRATE_REG = 0xA4500014; // defined:True
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// Peripheral/Parallel Interface Registers
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PI_DRAM_ADDR_REG = 0xA4600000; // defined:True
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PI_CART_ADDR_REG = 0xA4600004; // defined:True
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D_A4600005 = 0xA4600005; // defined:True // TODO figure out its name
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D_A4600006 = 0xA4600006; // defined:True // TODO figure out its name
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D_A4600007 = 0xA4600007; // defined:True // TODO figure out its name
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PI_RD_LEN_REG = 0xA4600008; // defined:True
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PI_WR_LEN_REG = 0xA460000C; // defined:True
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PI_STATUS_REG = 0xA4600010; // defined:True
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PI_BSD_DOM1_LAT_REG = 0xA4600014; // defined:True // PI dom1 latency
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PI_BSD_DOM1_PWD_REG = 0xA4600018; // defined:True // PI dom1 pulse width
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PI_BSD_DOM1_PGS_REG = 0xA460001C; // defined:True // PI dom1 page size
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PI_BSD_DOM1_RLS_REG = 0xA4600020; // defined:True // PI dom1 release
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PI_BSD_DOM2_LAT_REG = 0xA4600024; // defined:True // PI dom2 latency
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PI_BSD_DOM2_LWD_REG = 0xA4600028; // defined:True // PI dom2 pulse width
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PI_BSD_DOM2_PGS_REG = 0xA460002C; // defined:True // PI dom2 page size
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PI_BSD_DOM2_RLS_REG = 0xA4600030; // defined:True // PI dom2 release
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// RDRAM Interface Registers
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RI_MODE_REG = 0xA4700000; // defined:True
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RI_CONFIG_REG = 0xA4700004; // defined:True
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RI_CURRENT_LOAD_REG = 0xA4700008; // defined:True
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RI_SELECT_REG = 0xA470000C; // defined:True
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RI_REFRESH_REG = 0xA4700010; // defined:True
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RI_LATENCY_REG = 0xA4700014; // defined:True
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RI_RERROR_REG = 0xA4700018; // defined:True
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RI_WERROR_REG = 0xA470001C; // defined:True
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// Serial Interface Registers
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SI_DRAM_ADDR_REG = 0xA4800000; // defined:True
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SI_PIF_ADDR_RD64B_REG = 0xA4800004; // defined:True
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D_A4800008 = 0xA4800008; // defined:True // reserved
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D_A480000C = 0xA480000C; // defined:True // reserved
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SI_PIF_ADDR_WR64B_REG = 0xA4800010; // defined:True
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D_A4800014 = 0xA4800014; // defined:True // reserved
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SI_STATUS_REG = 0xA4800018; // defined:True
|
||||
@ -1,2 +0,0 @@
|
||||
ROMHEADER_CHECKSUM1 = 0x5A2C0815;
|
||||
ROMHEADER_CHECKSUM2 = 0xA82363D0;
|
||||
@ -1,94 +0,0 @@
|
||||
// Signal Processor Registers
|
||||
SP_MEM_ADDR_REG = 0xA4040000; // defined:True
|
||||
SP_DRAM_ADDR_REG = 0xA4040004; // defined:True
|
||||
SP_RD_LEN_REG = 0xA4040008; // defined:True
|
||||
SP_WR_LEN_REG = 0xA404000C; // defined:True
|
||||
SP_STATUS_REG = 0xA4040010; // defined:True
|
||||
SP_DMA_FULL_REG = 0xA4040014; // defined:True
|
||||
SP_DMA_BUSY_REG = 0xA4040018; // defined:True
|
||||
SP_SEMAPHORE_REG = 0xA404001C; // defined:True
|
||||
|
||||
SP_PC = 0xA4080000; // defined:True
|
||||
|
||||
// Display Processor Command Registers / Rasterizer Interface
|
||||
DPC_START_REG = 0xA4100000; // defined:True
|
||||
DPC_END_REG = 0xA4100004; // defined:True
|
||||
DPC_CURRENT_REG = 0xA4100008; // defined:True
|
||||
DPC_STATUS_REG = 0xA410000C; // defined:True
|
||||
DPC_CLOCK_REG = 0xA4100010; // defined:True
|
||||
DPC_BUFBUSY_REG = 0xA4100014; // defined:True
|
||||
DPC_PIPEBUSY_REG = 0xA4100018; // defined:True
|
||||
DPC_TMEM_REG = 0xA410001C; // defined:True
|
||||
|
||||
// Display Processor Span Registers
|
||||
DPS_TBIST_REG = 0xA4200000; // defined:True // DPS_TBIST_REG / DP_TMEM_BIST
|
||||
DPS_TEST_MODE_REG = 0xA4200004; // defined:True
|
||||
DPS_BUFTEST_ADDR_REG = 0xA4200008; // defined:True
|
||||
DPS_BUFTEST_DATA_REG = 0xA420000C; // defined:True
|
||||
|
||||
// MIPS Interface Registers
|
||||
MI_MODE_REG = 0xA4300000; // defined:True // MI_MODE_REG / MI_INIT_MODE_REG
|
||||
MI_VERSION_REG = 0xA4300004; // defined:True
|
||||
MI_INTR_REG = 0xA4300008; // defined:True
|
||||
MI_INTR_MASK_REG = 0xA430000C; // defined:True
|
||||
|
||||
// Video Interface Registers
|
||||
VI_STATUS_REG = 0xA4400000; // defined:True // VI_STATUS_REG / VI_CONTROL_REG
|
||||
VI_DRAM_ADDR_REG = 0xA4400004; // defined:True // VI_DRAM_ADDR_REG / VI_ORIGIN_REG
|
||||
VI_WIDTH_REG = 0xA4400008; // defined:True
|
||||
VI_INTR_REG = 0xA440000C; // defined:True
|
||||
VI_CURRENT_REG = 0xA4400010; // defined:True
|
||||
VI_BURST_REG = 0xA4400014; // defined:True // VI_BURST_REG / VI_TIMING_REG
|
||||
VI_V_SYNC_REG = 0xA4400018; // defined:True
|
||||
VI_H_SYNC_REG = 0xA440001C; // defined:True
|
||||
VI_LEAP_REG = 0xA4400020; // defined:True
|
||||
VI_H_START_REG = 0xA4400024; // defined:True
|
||||
VI_V_START_REG = 0xA4400028; // defined:True
|
||||
VI_V_BURST_REG = 0xA440002C; // defined:True
|
||||
VI_X_SCALE_REG = 0xA4400030; // defined:True
|
||||
VI_Y_SCALE_REG = 0xA4400034; // defined:True
|
||||
|
||||
// Audio Interface Registers
|
||||
AI_DRAM_ADDR_REG = 0xA4500000; // defined:True
|
||||
AI_LEN_REG = 0xA4500004; // defined:True
|
||||
AI_CONTROL_REG = 0xA4500008; // defined:True
|
||||
AI_STATUS_REG = 0xA450000C; // defined:True
|
||||
AI_DACRATE_REG = 0xA4500010; // defined:True
|
||||
AI_BITRATE_REG = 0xA4500014; // defined:True
|
||||
|
||||
// Peripheral/Parallel Interface Registers
|
||||
PI_DRAM_ADDR_REG = 0xA4600000; // defined:True
|
||||
PI_CART_ADDR_REG = 0xA4600004; // defined:True
|
||||
D_A4600005 = 0xA4600005; // defined:True // TODO figure out its name
|
||||
D_A4600006 = 0xA4600006; // defined:True // TODO figure out its name
|
||||
D_A4600007 = 0xA4600007; // defined:True // TODO figure out its name
|
||||
PI_RD_LEN_REG = 0xA4600008; // defined:True
|
||||
PI_WR_LEN_REG = 0xA460000C; // defined:True
|
||||
PI_STATUS_REG = 0xA4600010; // defined:True
|
||||
PI_BSD_DOM1_LAT_REG = 0xA4600014; // defined:True // PI dom1 latency
|
||||
PI_BSD_DOM1_PWD_REG = 0xA4600018; // defined:True // PI dom1 pulse width
|
||||
PI_BSD_DOM1_PGS_REG = 0xA460001C; // defined:True // PI dom1 page size
|
||||
PI_BSD_DOM1_RLS_REG = 0xA4600020; // defined:True // PI dom1 release
|
||||
PI_BSD_DOM2_LAT_REG = 0xA4600024; // defined:True // PI dom2 latency
|
||||
PI_BSD_DOM2_LWD_REG = 0xA4600028; // defined:True // PI dom2 pulse width
|
||||
PI_BSD_DOM2_PGS_REG = 0xA460002C; // defined:True // PI dom2 page size
|
||||
PI_BSD_DOM2_RLS_REG = 0xA4600030; // defined:True // PI dom2 release
|
||||
|
||||
// RDRAM Interface Registers
|
||||
RI_MODE_REG = 0xA4700000; // defined:True
|
||||
RI_CONFIG_REG = 0xA4700004; // defined:True
|
||||
RI_CURRENT_LOAD_REG = 0xA4700008; // defined:True
|
||||
RI_SELECT_REG = 0xA470000C; // defined:True
|
||||
RI_REFRESH_REG = 0xA4700010; // defined:True
|
||||
RI_LATENCY_REG = 0xA4700014; // defined:True
|
||||
RI_RERROR_REG = 0xA4700018; // defined:True
|
||||
RI_WERROR_REG = 0xA470001C; // defined:True
|
||||
|
||||
// Serial Interface Registers
|
||||
SI_DRAM_ADDR_REG = 0xA4800000; // defined:True
|
||||
SI_PIF_ADDR_RD64B_REG = 0xA4800004; // defined:True
|
||||
D_A4800008 = 0xA4800008; // defined:True // reserved
|
||||
D_A480000C = 0xA480000C; // defined:True // reserved
|
||||
SI_PIF_ADDR_WR64B_REG = 0xA4800010; // defined:True
|
||||
D_A4800014 = 0xA4800014; // defined:True // reserved
|
||||
SI_STATUS_REG = 0xA4800018; // defined:True
|
||||
@ -1,2 +0,0 @@
|
||||
ROMHEADER_CHECKSUM1 = 0x769D4D13;
|
||||
ROMHEADER_CHECKSUM2 = 0xDA233FFE;
|
||||
@ -1,6 +1,6 @@
|
||||
mapfile-parser>=2.3.2,<3.0.0
|
||||
ipl3checksum>=1.0.0,<2.0.0
|
||||
splat64[mips]>=0.24.5,<1.0.0
|
||||
splat64[mips]>=0.26.0,<1.0.0
|
||||
crunch64>=0.5.0,<1.0.0
|
||||
|
||||
# for m2c
|
||||
|
||||
577
slinky.yaml
577
slinky.yaml
@ -72,9 +72,13 @@ settings:
|
||||
section_end_align: 0x10
|
||||
|
||||
wildcard_sections: True
|
||||
|
||||
vram_classes:
|
||||
- { name: asset_00, fixed_vram: 0x00000000 }
|
||||
- { name: asset_05, fixed_vram: 0x05000000 }
|
||||
|
||||
segments:
|
||||
- name: header
|
||||
fixed_vram: 0x8F000000
|
||||
files:
|
||||
- { path: src/rom_header/rom_header.o }
|
||||
|
||||
@ -671,289 +675,289 @@ segments:
|
||||
- { path: "asm/{version}/data/segment_195290.o" }
|
||||
|
||||
- name: segment_game_etc
|
||||
fixed_vram: 0x00000000
|
||||
vram_class: asset_00
|
||||
segment_end_align: null
|
||||
section_end_align: null
|
||||
files:
|
||||
- { path: src/assets/game_etc/etc.o }
|
||||
|
||||
- name: segment_menu_bg
|
||||
fixed_vram: 0x05000000
|
||||
vram_class: asset_05
|
||||
files:
|
||||
- { path: src/assets/menu_bg/menu_bg.o }
|
||||
|
||||
- name: segment_menu_bg2
|
||||
fixed_vram: 0x05000000
|
||||
vram_class: asset_05
|
||||
files:
|
||||
- { path: src/assets/menu_bg/menu_bg2.o }
|
||||
|
||||
- name: segment_coffee01
|
||||
fixed_vram: 0x05000000
|
||||
vram_class: asset_05
|
||||
files:
|
||||
- { path: src/assets/coffee/coffee01.o }
|
||||
|
||||
- name: segment_title_all
|
||||
fixed_vram: 0x05000000
|
||||
vram_class: asset_05
|
||||
files:
|
||||
- { path: src/assets/title/title_all.o }
|
||||
|
||||
- name: segment_title_bmp
|
||||
fixed_vram: 0x00000000
|
||||
vram_class: asset_00
|
||||
files:
|
||||
- { path: src/assets/title/title_bmp.o }
|
||||
|
||||
- name: segment_waku
|
||||
fixed_vram: 0x00000000
|
||||
vram_class: asset_00
|
||||
files:
|
||||
- { path: src/assets/waku/waku.o }
|
||||
|
||||
- name: segment_waku2
|
||||
fixed_vram: 0x00000000
|
||||
vram_class: asset_00
|
||||
files:
|
||||
- { path: src/assets/waku/waku2.o }
|
||||
|
||||
- name: segment_story_bg01
|
||||
fixed_vram: 0x00000000
|
||||
vram_class: asset_00
|
||||
files:
|
||||
- { path: src/assets/story/bg01.o }
|
||||
|
||||
- name: segment_story_bg02
|
||||
fixed_vram: 0x00000000
|
||||
vram_class: asset_00
|
||||
files:
|
||||
- { path: src/assets/story/bg02.o }
|
||||
|
||||
- name: segment_story_bg03
|
||||
fixed_vram: 0x00000000
|
||||
vram_class: asset_00
|
||||
files:
|
||||
- { path: src/assets/story/bg03.o }
|
||||
|
||||
- name: segment_story_bg04
|
||||
fixed_vram: 0x00000000
|
||||
vram_class: asset_00
|
||||
files:
|
||||
- { path: src/assets/story/bg04.o }
|
||||
|
||||
- name: segment_story_bg05
|
||||
fixed_vram: 0x00000000
|
||||
vram_class: asset_00
|
||||
files:
|
||||
- { path: src/assets/story/bg05.o }
|
||||
|
||||
- name: segment_story_bg07
|
||||
fixed_vram: 0x00000000
|
||||
vram_class: asset_00
|
||||
files:
|
||||
- { path: src/assets/story/bg07.o }
|
||||
|
||||
- name: segment_story_bg08
|
||||
fixed_vram: 0x00000000
|
||||
vram_class: asset_00
|
||||
files:
|
||||
- { path: src/assets/story/bg08.o }
|
||||
|
||||
- name: segment_story_bg09
|
||||
fixed_vram: 0x00000000
|
||||
vram_class: asset_00
|
||||
files:
|
||||
- { path: src/assets/story/bg09.o }
|
||||
|
||||
- name: segment_story_bg10
|
||||
fixed_vram: 0x00000000
|
||||
vram_class: asset_00
|
||||
files:
|
||||
- { path: src/assets/story/bg10.o }
|
||||
|
||||
- name: segment_story_bg11
|
||||
fixed_vram: 0x00000000
|
||||
vram_class: asset_00
|
||||
files:
|
||||
- { path: src/assets/story/bg11.o }
|
||||
|
||||
- name: segment_menu_char
|
||||
fixed_vram: 0x00000000
|
||||
vram_class: asset_00
|
||||
files:
|
||||
- { path: src/assets/menu/menu_char.o }
|
||||
|
||||
- name: segment_menu_common
|
||||
fixed_vram: 0x00000000
|
||||
vram_class: asset_00
|
||||
files:
|
||||
- { path: src/assets/menu/menu_common.o }
|
||||
|
||||
- name: segment_menu_level
|
||||
fixed_vram: 0x00000000
|
||||
vram_class: asset_00
|
||||
files:
|
||||
- { path: src/assets/menu/menu_level.o }
|
||||
|
||||
- name: segment_menu_main
|
||||
fixed_vram: 0x00000000
|
||||
vram_class: asset_00
|
||||
files:
|
||||
- { path: src/assets/menu/menu_main.o }
|
||||
|
||||
- name: segment_menu_name
|
||||
fixed_vram: 0x00000000
|
||||
vram_class: asset_00
|
||||
files:
|
||||
- { path: src/assets/menu/menu_name.o }
|
||||
|
||||
- name: segment_menu_p2
|
||||
fixed_vram: 0x00000000
|
||||
vram_class: asset_00
|
||||
files:
|
||||
- { path: src/assets/menu/menu_p2.o }
|
||||
|
||||
- name: segment_menu_p4
|
||||
fixed_vram: 0x00000000
|
||||
vram_class: asset_00
|
||||
files:
|
||||
- { path: src/assets/menu/menu_p4.o }
|
||||
|
||||
- name: segment_menu_rank
|
||||
fixed_vram: 0x00000000
|
||||
vram_class: asset_00
|
||||
files:
|
||||
- { path: src/assets/menu/menu_rank.o }
|
||||
|
||||
- name: segment_menu_setup
|
||||
fixed_vram: 0x00000000
|
||||
vram_class: asset_00
|
||||
files:
|
||||
- { path: src/assets/menu/menu_setup.o }
|
||||
|
||||
- name: segment_menu_story
|
||||
fixed_vram: 0x00000000
|
||||
vram_class: asset_00
|
||||
files:
|
||||
- { path: src/assets/menu/menu_story.o }
|
||||
|
||||
- name: segment_menu_cont
|
||||
fixed_vram: 0x00000000
|
||||
vram_class: asset_00
|
||||
files:
|
||||
- { path: src/assets/menu/menu_cont.o }
|
||||
|
||||
- name: segment_menu_kasa
|
||||
fixed_vram: 0x00000000
|
||||
vram_class: asset_00
|
||||
files:
|
||||
- { path: src/assets/menu/menu_kasa.o }
|
||||
|
||||
- name: segment_game_al
|
||||
fixed_vram: 0x00000000
|
||||
vram_class: asset_00
|
||||
files:
|
||||
- { path: src/assets/game/game_al.o }
|
||||
|
||||
- name: segment_game_p1
|
||||
fixed_vram: 0x00000000
|
||||
vram_class: asset_00
|
||||
files:
|
||||
- { path: src/assets/game/game_p1.o }
|
||||
|
||||
- name: segment_game_p2
|
||||
fixed_vram: 0x00000000
|
||||
vram_class: asset_00
|
||||
files:
|
||||
- { path: src/assets/game/game_p2.o }
|
||||
|
||||
- name: segment_game_p4
|
||||
fixed_vram: 0x00000000
|
||||
vram_class: asset_00
|
||||
files:
|
||||
- { path: src/assets/game/game_p4.o }
|
||||
|
||||
- name: segment_game_ls
|
||||
fixed_vram: 0x00000000
|
||||
vram_class: asset_00
|
||||
files:
|
||||
- { path: src/assets/game/game_ls.o }
|
||||
|
||||
- name: segment_game_item
|
||||
fixed_vram: 0x00000000
|
||||
vram_class: asset_00
|
||||
files:
|
||||
- { path: src/assets/game/game_item.o }
|
||||
|
||||
- name: segment_anime_a
|
||||
fixed_vram: 0x00000000
|
||||
vram_class: asset_00
|
||||
files:
|
||||
- { path: src/assets/anime/anime_a.o }
|
||||
|
||||
- name: segment_anime_b
|
||||
fixed_vram: 0x00000000
|
||||
vram_class: asset_00
|
||||
files:
|
||||
- { path: src/assets/anime/anime_b.o }
|
||||
|
||||
- name: segment_anime_c
|
||||
fixed_vram: 0x00000000
|
||||
vram_class: asset_00
|
||||
files:
|
||||
- { path: src/assets/anime/anime_c.o }
|
||||
|
||||
- name: segment_anime_d
|
||||
fixed_vram: 0x00000000
|
||||
vram_class: asset_00
|
||||
files:
|
||||
- { path: src/assets/anime/anime_d.o }
|
||||
|
||||
- name: segment_anime_e
|
||||
fixed_vram: 0x00000000
|
||||
vram_class: asset_00
|
||||
files:
|
||||
- { path: src/assets/anime/anime_e.o }
|
||||
|
||||
- name: segment_anime_f
|
||||
fixed_vram: 0x00000000
|
||||
vram_class: asset_00
|
||||
files:
|
||||
- { path: src/assets/anime/anime_f.o }
|
||||
|
||||
- name: segment_anime_g
|
||||
fixed_vram: 0x00000000
|
||||
vram_class: asset_00
|
||||
files:
|
||||
- { path: src/assets/anime/anime_g.o }
|
||||
|
||||
- name: segment_anime_h
|
||||
fixed_vram: 0x00000000
|
||||
vram_class: asset_00
|
||||
files:
|
||||
- { path: src/assets/anime/anime_h.o }
|
||||
|
||||
- name: segment_anime_i
|
||||
fixed_vram: 0x00000000
|
||||
vram_class: asset_00
|
||||
files:
|
||||
- { path: src/assets/anime/anime_i.o }
|
||||
|
||||
- name: segment_anime_j
|
||||
fixed_vram: 0x00000000
|
||||
vram_class: asset_00
|
||||
files:
|
||||
- { path: src/assets/anime/anime_j.o }
|
||||
|
||||
- name: segment_anime_k
|
||||
fixed_vram: 0x00000000
|
||||
vram_class: asset_00
|
||||
files:
|
||||
- { path: src/assets/anime/anime_k.o }
|
||||
|
||||
- name: segment_anime_l
|
||||
fixed_vram: 0x00000000
|
||||
vram_class: asset_00
|
||||
files:
|
||||
- { path: src/assets/anime/anime_l.o }
|
||||
|
||||
- name: segment_anime_m
|
||||
fixed_vram: 0x00000000
|
||||
vram_class: asset_00
|
||||
files:
|
||||
- { path: src/assets/anime/anime_m.o }
|
||||
|
||||
- name: segment_anime_n
|
||||
fixed_vram: 0x00000000
|
||||
vram_class: asset_00
|
||||
files:
|
||||
- { path: src/assets/anime/anime_n.o }
|
||||
|
||||
- name: segment_anime_o
|
||||
fixed_vram: 0x00000000
|
||||
vram_class: asset_00
|
||||
files:
|
||||
- { path: src/assets/anime/anime_o.o }
|
||||
|
||||
- name: segment_anime_mario
|
||||
fixed_vram: 0x00000000
|
||||
vram_class: asset_00
|
||||
files:
|
||||
- { path: src/assets/anime/anime_mario.o }
|
||||
|
||||
- name: segment_anime_virus_b
|
||||
fixed_vram: 0x00000000
|
||||
vram_class: asset_00
|
||||
files:
|
||||
- { path: src/assets/anime/anime_virus_b.o }
|
||||
|
||||
- name: segment_anime_virus_r
|
||||
fixed_vram: 0x00000000
|
||||
vram_class: asset_00
|
||||
files:
|
||||
- { path: src/assets/anime/anime_virus_r.o }
|
||||
|
||||
- name: segment_anime_virus_y
|
||||
fixed_vram: 0x00000000
|
||||
vram_class: asset_00
|
||||
files:
|
||||
- { path: src/assets/anime/anime_virus_y.o }
|
||||
|
||||
- name: segment_anime_smog
|
||||
fixed_vram: 0x00000000
|
||||
vram_class: asset_00
|
||||
files:
|
||||
- { path: src/assets/anime/anime_smog.o }
|
||||
|
||||
- name: segment_tutorial_data
|
||||
fixed_vram: 0x00000000
|
||||
vram_class: asset_00
|
||||
files:
|
||||
- { path: src/assets/tutorial/tutorial_kasa.o }
|
||||
|
||||
@ -962,3 +966,460 @@ segments:
|
||||
include_if_any: [[version, cn]]
|
||||
files:
|
||||
- { path: "asm/{version}/data/65CF00.o" }
|
||||
|
||||
entry: entrypoint
|
||||
|
||||
symbol_assignments:
|
||||
- name: boot_BSS_START_HI
|
||||
value: boot_BSS_START >> 16;
|
||||
- name: boot_BSS_START_LO
|
||||
value: boot_BSS_START & 0xFFFF;
|
||||
- name: boot_BSS_SIZE_HI
|
||||
value: boot_BSS_SIZE >> 16;
|
||||
- name: boot_BSS_SIZE_LO
|
||||
value: boot_BSS_SIZE & 0xFFFF;
|
||||
|
||||
- name: bootproc_HI
|
||||
value: bootproc >> 16;
|
||||
- name: bootproc_LO
|
||||
value: bootproc & 0xFFFF;
|
||||
|
||||
- name: gBootThreadStack_HI
|
||||
value: gBootThreadStack >> 16;
|
||||
- name: gBootThreadStack_LO
|
||||
value: gBootThreadStack & 0xFFFF;
|
||||
|
||||
- name: gBootThreadStackTop
|
||||
value: gBootThreadStack + STACK_SIZE;
|
||||
- name: gBootThreadStackTop_HI
|
||||
value: gBootThreadStackTop >> 16;
|
||||
- name: gBootThreadStackTop_LO
|
||||
value: gBootThreadStackTop & 0xFFFF;
|
||||
|
||||
# TODO: remove when we actually use libultra files on iQue builds
|
||||
- name: leoBootID
|
||||
value: 0x800001A0
|
||||
include_if_any: [[version, cn]]
|
||||
- name: osTvType
|
||||
value: 0x80000300
|
||||
include_if_any: [[version, cn]]
|
||||
- name: osRomType
|
||||
value: 0x80000304
|
||||
include_if_any: [[version, cn]]
|
||||
- name: osRomBase
|
||||
value: 0x80000308
|
||||
include_if_any: [[version, cn]]
|
||||
- name: osResetType
|
||||
value: 0x8000030C
|
||||
include_if_any: [[version, cn]]
|
||||
- name: osCicId
|
||||
value: 0x80000310
|
||||
include_if_any: [[version, cn]]
|
||||
- name: osVersion
|
||||
value: 0x80000314
|
||||
include_if_any: [[version, cn]]
|
||||
- name: osMemSize
|
||||
value: 0x80000318
|
||||
include_if_any: [[version, cn]]
|
||||
- name: osAppNMIBuffer
|
||||
value: 0x8000031C
|
||||
include_if_any: [[version, cn]]
|
||||
- name: __osBbEepromAddress
|
||||
value: 0x8000035c
|
||||
include_if_any: [[version, cn]]
|
||||
- name: __osBbEepromSize
|
||||
value: 0x80000360
|
||||
include_if_any: [[version, cn]]
|
||||
- name: __osBbFlashAddress
|
||||
value: 0x80000364
|
||||
include_if_any: [[version, cn]]
|
||||
- name: __osBbFlashSize
|
||||
value: 0x80000368
|
||||
include_if_any: [[version, cn]]
|
||||
- name: __osBbSramAddress
|
||||
value: 0x8000036c
|
||||
include_if_any: [[version, cn]]
|
||||
- name: __osBbSramSize
|
||||
value: 0x80000370
|
||||
include_if_any: [[version, cn]]
|
||||
- name: __osBbPakAddress
|
||||
value: 0x80000374
|
||||
include_if_any: [[version, cn]]
|
||||
- name: __osBbPakSize
|
||||
value: 0x80000384
|
||||
include_if_any: [[version, cn]]
|
||||
- name: __osBbIsBb
|
||||
value: 0x80000388
|
||||
include_if_any: [[version, cn]]
|
||||
- name: __osBbHackFlags
|
||||
value: 0x8000038c
|
||||
include_if_any: [[version, cn]]
|
||||
- name: __osBbStashMagic
|
||||
value: 0x80000390
|
||||
include_if_any: [[version, cn]]
|
||||
- name: __osBbPakBindings
|
||||
value: 0x80000394
|
||||
include_if_any: [[version, cn]]
|
||||
- name: __osBbStateName
|
||||
value: 0x800003a4
|
||||
include_if_any: [[version, cn]]
|
||||
- name: __osBbStateDirty
|
||||
value: 0x800003b4
|
||||
include_if_any: [[version, cn]]
|
||||
- name: __osBbAuxDataLimit
|
||||
value: 0x800003b8
|
||||
include_if_any: [[version, cn]]
|
||||
# Signal Processor Registers
|
||||
- name: SP_MEM_ADDR_REG
|
||||
value: 0xA4040000
|
||||
include_if_any: [[version, cn]]
|
||||
- name: SP_DRAM_ADDR_REG
|
||||
value: 0xA4040004
|
||||
include_if_any: [[version, cn]]
|
||||
- name: SP_RD_LEN_REG
|
||||
value: 0xA4040008
|
||||
include_if_any: [[version, cn]]
|
||||
- name: SP_WR_LEN_REG
|
||||
value: 0xA404000C
|
||||
include_if_any: [[version, cn]]
|
||||
- name: SP_STATUS_REG
|
||||
value: 0xA4040010
|
||||
include_if_any: [[version, cn]]
|
||||
- name: SP_DMA_FULL_REG
|
||||
value: 0xA4040014
|
||||
include_if_any: [[version, cn]]
|
||||
- name: SP_DMA_BUSY_REG
|
||||
value: 0xA4040018
|
||||
include_if_any: [[version, cn]]
|
||||
- name: SP_SEMAPHORE_REG
|
||||
value: 0xA404001C
|
||||
include_if_any: [[version, cn]]
|
||||
|
||||
- name: SP_PC
|
||||
value: 0xA4080000
|
||||
include_if_any: [[version, cn]]
|
||||
|
||||
# Display Processor Command Registers / Rasterizer Interface
|
||||
- name: DPC_START_REG
|
||||
value: 0xA4100000
|
||||
include_if_any: [[version, cn]]
|
||||
- name: DPC_END_REG
|
||||
value: 0xA4100004
|
||||
include_if_any: [[version, cn]]
|
||||
- name: DPC_CURRENT_REG
|
||||
value: 0xA4100008
|
||||
include_if_any: [[version, cn]]
|
||||
- name: DPC_STATUS_REG
|
||||
value: 0xA410000C
|
||||
include_if_any: [[version, cn]]
|
||||
- name: DPC_CLOCK_REG
|
||||
value: 0xA4100010
|
||||
include_if_any: [[version, cn]]
|
||||
- name: DPC_BUFBUSY_REG
|
||||
value: 0xA4100014
|
||||
include_if_any: [[version, cn]]
|
||||
- name: DPC_PIPEBUSY_REG
|
||||
value: 0xA4100018
|
||||
include_if_any: [[version, cn]]
|
||||
- name: DPC_TMEM_REG
|
||||
value: 0xA410001C
|
||||
include_if_any: [[version, cn]]
|
||||
|
||||
# Display Processor Span Registers
|
||||
- name: DPS_TBIST_REG
|
||||
value: 0xA4200000
|
||||
include_if_any: [[version, cn]]
|
||||
- name: DPS_TEST_MODE_REG
|
||||
value: 0xA4200004
|
||||
include_if_any: [[version, cn]]
|
||||
- name: DPS_BUFTEST_ADDR_REG
|
||||
value: 0xA4200008
|
||||
include_if_any: [[version, cn]]
|
||||
- name: DPS_BUFTEST_DATA_REG
|
||||
value: 0xA420000C
|
||||
include_if_any: [[version, cn]]
|
||||
|
||||
# MIPS Interface Registers
|
||||
- name: MI_MODE_REG
|
||||
value: 0xA4300000
|
||||
include_if_any: [[version, cn]]
|
||||
- name: MI_VERSION_REG
|
||||
value: 0xA4300004
|
||||
include_if_any: [[version, cn]]
|
||||
- name: MI_INTR_REG
|
||||
value: 0xA4300008
|
||||
include_if_any: [[version, cn]]
|
||||
- name: MI_INTR_MASK_REG
|
||||
value: 0xA430000C
|
||||
include_if_any: [[version, cn]]
|
||||
- name: D_A4300010
|
||||
value: 0xA4300010
|
||||
include_if_any: [[version, cn]]
|
||||
- name: MI_SK_EXCEPTION_REG
|
||||
value: 0xA4300014
|
||||
include_if_any: [[version, cn]]
|
||||
- name: MI_SK_WATCHDOG_TIMER
|
||||
value: 0xA4300018
|
||||
include_if_any: [[version, cn]]
|
||||
- name: D_A4300028
|
||||
value: 0xA4300028
|
||||
include_if_any: [[version, cn]]
|
||||
- name: MI_RANDOM_BIT
|
||||
value: 0xA430002C
|
||||
include_if_any: [[version, cn]]
|
||||
- name: D_A4300030
|
||||
value: 0xA4300030
|
||||
include_if_any: [[version, cn]]
|
||||
- name: MI_HW_INTR_REG
|
||||
value: 0xA4300038
|
||||
include_if_any: [[version, cn]]
|
||||
- name: MI_HW_INTR_MASK_REG
|
||||
value: 0xA430003C
|
||||
include_if_any: [[version, cn]]
|
||||
|
||||
# Video Interface Registers
|
||||
- name: VI_STATUS_REG
|
||||
value: 0xA4400000
|
||||
include_if_any: [[version, cn]]
|
||||
- name: VI_DRAM_ADDR_REG
|
||||
value: 0xA4400004
|
||||
include_if_any: [[version, cn]]
|
||||
- name: VI_WIDTH_REG
|
||||
value: 0xA4400008
|
||||
include_if_any: [[version, cn]]
|
||||
- name: VI_INTR_REG
|
||||
value: 0xA440000C
|
||||
include_if_any: [[version, cn]]
|
||||
- name: VI_CURRENT_REG
|
||||
value: 0xA4400010
|
||||
include_if_any: [[version, cn]]
|
||||
- name: VI_BURST_REG
|
||||
value: 0xA4400014
|
||||
include_if_any: [[version, cn]]
|
||||
- name: VI_V_SYNC_REG
|
||||
value: 0xA4400018
|
||||
include_if_any: [[version, cn]]
|
||||
- name: VI_H_SYNC_REG
|
||||
value: 0xA440001C
|
||||
include_if_any: [[version, cn]]
|
||||
- name: VI_LEAP_REG
|
||||
value: 0xA4400020
|
||||
include_if_any: [[version, cn]]
|
||||
- name: VI_H_START_REG
|
||||
value: 0xA4400024
|
||||
include_if_any: [[version, cn]]
|
||||
- name: VI_V_START_REG
|
||||
value: 0xA4400028
|
||||
include_if_any: [[version, cn]]
|
||||
- name: VI_V_BURST_REG
|
||||
value: 0xA440002C
|
||||
include_if_any: [[version, cn]]
|
||||
- name: VI_X_SCALE_REG
|
||||
value: 0xA4400030
|
||||
include_if_any: [[version, cn]]
|
||||
- name: VI_Y_SCALE_REG
|
||||
value: 0xA4400034
|
||||
include_if_any: [[version, cn]]
|
||||
|
||||
# Audio Interface Registers
|
||||
- name: AI_DRAM_ADDR_REG
|
||||
value: 0xA4500000
|
||||
include_if_any: [[version, cn]]
|
||||
- name: AI_LEN_REG
|
||||
value: 0xA4500004
|
||||
include_if_any: [[version, cn]]
|
||||
- name: AI_CONTROL_REG
|
||||
value: 0xA4500008
|
||||
include_if_any: [[version, cn]]
|
||||
- name: AI_STATUS_REG
|
||||
value: 0xA450000C
|
||||
include_if_any: [[version, cn]]
|
||||
- name: AI_DACRATE_REG
|
||||
value: 0xA4500010
|
||||
include_if_any: [[version, cn]]
|
||||
- name: AI_BITRATE_REG
|
||||
value: 0xA4500014
|
||||
include_if_any: [[version, cn]]
|
||||
|
||||
# Peripheral/Parallel Interface Registers
|
||||
- name: PI_DRAM_ADDR_REG
|
||||
value: 0xA4600000
|
||||
include_if_any: [[version, cn]]
|
||||
- name: PI_CART_ADDR_REG
|
||||
value: 0xA4600004
|
||||
include_if_any: [[version, cn]]
|
||||
- name: PI_RD_LEN_REG
|
||||
value: 0xA4600008
|
||||
include_if_any: [[version, cn]]
|
||||
- name: PI_WR_LEN_REG
|
||||
value: 0xA460000C
|
||||
include_if_any: [[version, cn]]
|
||||
- name: PI_STATUS_REG
|
||||
value: 0xA4600010
|
||||
include_if_any: [[version, cn]]
|
||||
- name: PI_BSD_DOM1_LAT_REG
|
||||
value: 0xA4600014
|
||||
include_if_any: [[version, cn]]
|
||||
- name: PI_BSD_DOM1_PWD_REG
|
||||
value: 0xA4600018
|
||||
include_if_any: [[version, cn]]
|
||||
- name: PI_BSD_DOM1_PGS_REG
|
||||
value: 0xA460001C
|
||||
include_if_any: [[version, cn]]
|
||||
- name: PI_BSD_DOM1_RLS_REG
|
||||
value: 0xA4600020
|
||||
include_if_any: [[version, cn]]
|
||||
- name: PI_BSD_DOM2_LAT_REG
|
||||
value: 0xA4600024
|
||||
include_if_any: [[version, cn]]
|
||||
- name: PI_BSD_DOM2_LWD_REG
|
||||
value: 0xA4600028
|
||||
include_if_any: [[version, cn]]
|
||||
- name: PI_BSD_DOM2_PGS_REG
|
||||
value: 0xA460002C
|
||||
include_if_any: [[version, cn]]
|
||||
- name: PI_BSD_DOM2_RLS_REG
|
||||
value: 0xA4600030
|
||||
include_if_any: [[version, cn]]
|
||||
- name: PI_CARD_STATUS_REG
|
||||
value: 0xA4600038
|
||||
include_if_any: [[version, cn]]
|
||||
- name: PI_ATB_NEXT_CONFIG
|
||||
value: 0xA4600040
|
||||
include_if_any: [[version, cn]]
|
||||
- name: D_A4600044
|
||||
value: 0xA4600044
|
||||
include_if_any: [[version, cn]]
|
||||
- name: PI_CARD_CNT_REG
|
||||
value: 0xA4600048
|
||||
include_if_any: [[version, cn]]
|
||||
- name: PI_CARD_CONFIG_REG
|
||||
value: 0xA460004C
|
||||
include_if_any: [[version, cn]]
|
||||
- name: PI_AES_CNT
|
||||
value: 0xA4600050
|
||||
include_if_any: [[version, cn]]
|
||||
- name: PI_ALLOWED_IO
|
||||
value: 0xA4600054
|
||||
include_if_any: [[version, cn]]
|
||||
- name: PI_EX_RD_LEN_REG
|
||||
value: 0xA4600058
|
||||
include_if_any: [[version, cn]]
|
||||
- name: PI_EX_WR_LEN_REG
|
||||
value: 0xA460005C
|
||||
include_if_any: [[version, cn]]
|
||||
- name: PI_MISC_REG
|
||||
value: 0xA4600060
|
||||
include_if_any: [[version, cn]]
|
||||
- name: D_A4600064
|
||||
value: 0xA4600064
|
||||
include_if_any: [[version, cn]]
|
||||
- name: PI_CARD_BLK_OFFSET_REG
|
||||
value: 0xA4600070
|
||||
include_if_any: [[version, cn]]
|
||||
- name: PI_EX_DMA_BUF
|
||||
value: 0xA4610000
|
||||
include_if_any: [[version, cn]]
|
||||
- name: PI_AES_EXPANDED_KEY
|
||||
value: 0xA4610420
|
||||
include_if_any: [[version, cn]]
|
||||
- name: PI_AES_IV
|
||||
value: 0xA46104D0
|
||||
include_if_any: [[version, cn]]
|
||||
- name: PI_ATB_ENTRY
|
||||
value: 0xA4610500
|
||||
include_if_any: [[version, cn]]
|
||||
- name: D_A4620000
|
||||
value: 0xA4620000
|
||||
include_if_any: [[version, cn]]
|
||||
- name: PI_RDB_REQ_HI_REG
|
||||
value: 0xA46E0000
|
||||
include_if_any: [[version, cn]]
|
||||
- name: PI_RDB_REQ_LO_REG
|
||||
value: 0xA46E0002
|
||||
include_if_any: [[version, cn]]
|
||||
- name: D_A46E0004
|
||||
value: 0xA46E0004
|
||||
include_if_any: [[version, cn]]
|
||||
- name: D_A46E0400
|
||||
value: 0xA46E0400
|
||||
include_if_any: [[version, cn]]
|
||||
- name: D_A46E0402
|
||||
value: 0xA46E0402
|
||||
include_if_any: [[version, cn]]
|
||||
- name: PI_RDB_STATUS_REG
|
||||
value: 0xA46E8000
|
||||
include_if_any: [[version, cn]]
|
||||
|
||||
# RDRAM Interface Registers
|
||||
- name: RI_MODE_REG
|
||||
value: 0xA4700000
|
||||
include_if_any: [[version, cn]]
|
||||
- name: RI_CONFIG_REG
|
||||
value: 0xA4700004
|
||||
include_if_any: [[version, cn]]
|
||||
- name: RI_CURRENT_LOAD_REG
|
||||
value: 0xA4700008
|
||||
include_if_any: [[version, cn]]
|
||||
- name: RI_SELECT_REG
|
||||
value: 0xA470000C
|
||||
include_if_any: [[version, cn]]
|
||||
- name: RI_REFRESH_REG
|
||||
value: 0xA4700010
|
||||
include_if_any: [[version, cn]]
|
||||
- name: RI_LATENCY_REG
|
||||
value: 0xA4700014
|
||||
include_if_any: [[version, cn]]
|
||||
- name: RI_RERROR_REG
|
||||
value: 0xA4700018
|
||||
include_if_any: [[version, cn]]
|
||||
- name: RI_WERROR_REG
|
||||
value: 0xA470001C
|
||||
include_if_any: [[version, cn]]
|
||||
|
||||
# Serial Interface Registers
|
||||
- name: SI_DRAM_ADDR_REG
|
||||
value: 0xA4800000
|
||||
include_if_any: [[version, cn]]
|
||||
- name: SI_PIF_ADDR_RD64B_REG
|
||||
value: 0xA4800004
|
||||
include_if_any: [[version, cn]]
|
||||
- name: D_A4800008
|
||||
value: 0xA4800008
|
||||
include_if_any: [[version, cn]]
|
||||
- name: D_A480000C
|
||||
value: 0xA480000C
|
||||
include_if_any: [[version, cn]]
|
||||
- name: SI_PIF_ADDR_WR64B_REG
|
||||
value: 0xA4800010
|
||||
include_if_any: [[version, cn]]
|
||||
- name: D_A4800014
|
||||
value: 0xA4800014
|
||||
include_if_any: [[version, cn]]
|
||||
- name: SI_STATUS_REG
|
||||
value: 0xA4800018
|
||||
include_if_any: [[version, cn]]
|
||||
- name: D_A480001C
|
||||
value: 0xA480001C
|
||||
include_if_any: [[version, cn]]
|
||||
|
||||
- name: D_A4900000
|
||||
value: 0xA4900000
|
||||
include_if_any: [[version, cn]]
|
||||
- name: USB0_STATUS_REG
|
||||
value: 0xA4940010
|
||||
include_if_any: [[version, cn]]
|
||||
- name: D_A4A00000
|
||||
value: 0xA4A00000
|
||||
include_if_any: [[version, cn]]
|
||||
- name: USB1_STATUS_REG
|
||||
value: 0xA4A40010
|
||||
include_if_any: [[version, cn]]
|
||||
|
||||
asserts:
|
||||
- check: buffer1_VRAM_END <= 0x80205000
|
||||
error_message: The segment 'buffer1' is overflowing the ram limit
|
||||
- check: buffer2_BSS_START == 0x80205000
|
||||
error_message: buffer2 shifted?
|
||||
- check: framebuffer_BSS_START == 0x803B5000
|
||||
error_message: framebuffer shifted?
|
||||
|
||||
@ -1,8 +1,10 @@
|
||||
#include "hasm.h"
|
||||
|
||||
ABS(STACK_SIZE, BOOT_STACK_SIZE)
|
||||
|
||||
.section .text
|
||||
|
||||
.balign 16
|
||||
.align 4
|
||||
|
||||
LEAF(entrypoint)
|
||||
LA($t0, boot_BSS_START)
|
||||
|
||||
@ -28,9 +28,6 @@ typedef struct RomHeader {
|
||||
|
||||
void entrypoint(void);
|
||||
|
||||
extern u32 ROMHEADER_CHECKSUM1;
|
||||
extern u32 ROMHEADER_CHECKSUM2;
|
||||
|
||||
RomHeader gRomHeader = {
|
||||
// unk_00
|
||||
0x80371240,
|
||||
@ -45,10 +42,9 @@ RomHeader gRomHeader = {
|
||||
// libultraVersion
|
||||
BUILD_VERSION + 'D' - 1,
|
||||
|
||||
// checksum1
|
||||
(u32)&ROMHEADER_CHECKSUM1,
|
||||
// checksum2
|
||||
(u32)&ROMHEADER_CHECKSUM2,
|
||||
// checksum, updated automatically via tooling during the build process
|
||||
0,
|
||||
0,
|
||||
// unk_18
|
||||
0x00000000,
|
||||
// unk_1C
|
||||
|
||||
@ -64,7 +64,7 @@ $(EGCS_BINUTILS): | $(EGCS_DIR)
|
||||
$(RM) mips-binutils-egcs-2.9.5-$(DETECTED_OS).tar.gz
|
||||
|
||||
$(SLINKY): | $(SLINKY_DIR)
|
||||
wget https://github.com/decompals/slinky/releases/download/0.2.5/slinky-cli-$(HOST_TRIPLE).tar.gz
|
||||
wget https://github.com/decompals/slinky/releases/download/0.3.0/slinky-cli-$(HOST_TRIPLE).tar.gz
|
||||
tar xf slinky-cli-$(HOST_TRIPLE).tar.gz -C $(SLINKY_DIR)
|
||||
$(RM) slinky-cli-$(HOST_TRIPLE).tar.gz
|
||||
|
||||
|
||||
Loading…
Reference in New Issue
Block a user