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https://github.com/zeldaret/mm.git
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aisetfreq OK, some libultra improvements (#416)
* aisetfreq OK * Add a lot of HW_REG and some other macros to libultra * Format * Remove extra volatile * Review * De-C guNormalize * Correct typo in crc.c
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89b9d90826
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@ -11,6 +11,7 @@
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#include "ultra64/sptask.h"
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#include "ultra64/thread.h"
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#include "ultra64/rcp.h"
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#include "ultra64/rdp.h"
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#include "ultra64/rsp.h"
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#include "ultra64/vi.h"
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@ -96,6 +96,7 @@
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#define SI_STATUS_INTERRUPT (1 << 12)
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#define PIF_RAM_START 0x1FC007C0
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#define PIF_RAM_SIZE 0x40
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#define MI_INIT_MODE_REG 0x04300000
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#define MI_MODE_REG MI_INIT_MODE_REG
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45
include/ultra64/rdp.h
Normal file
45
include/ultra64/rdp.h
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@ -0,0 +1,45 @@
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#ifndef ULTRA64_RDP_H
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#define ULTRA64_RDP_H
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/* DP Command Registers */
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#define DPC_START_REG 0x04100000
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#define DPC_END_REG 0x04100004
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#define DPC_CURRENT_REG 0x04100008
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#define DPC_STATUS_REG 0x0410000C
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#define DPC_CLOCK_REG 0x04100010
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#define DPC_BUFBUSY_REG 0x04100014
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#define DPC_PIPEBUSY_REG 0x04100018
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#define DPC_TMEM_REG 0x0410001C
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/* DP Span Registers */
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#define DPS_TBIST_REG 0x04200000
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#define DPS_TEST_MODE_REG 0x04200004
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#define DPS_BUFTEST_ADDR_REG 0x04200008
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#define DPS_BUFTEST_DATA_REG 0x0420000C
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/* DP Status Read Flags */
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#define DPC_STATUS_XBUS_DMEM_DMA (1 << 0)
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#define DPC_STATUS_FREEZE (1 << 1)
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#define DPC_STATUS_FLUSH (1 << 2)
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#define DPC_STATUS_START_GCLK (1 << 3)
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#define DPC_STATUS_TMEM_BUSY (1 << 4)
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#define DPC_STATUS_PIPE_BUSY (1 << 5)
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#define DPC_STATUS_CMD_BUSY (1 << 6)
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#define DPC_STATUS_CBUF_READY (1 << 7)
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#define DPC_STATUS_DMA_BUSY (1 << 8)
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#define DPC_STATUS_END_VALID (1 << 9)
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#define DPC_STATUS_START_VALID (1 << 10)
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/* DP Status Write Flags */
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#define DPC_CLR_XBUS_DMEM_DMA (1 << 0)
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#define DPC_SET_XBUS_DMEM_DMA (1 << 1)
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#define DPC_CLR_FREEZE (1 << 2)
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#define DPC_SET_FREEZE (1 << 3)
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#define DPC_CLR_FLUSH (1 << 4)
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#define DPC_SET_FLUSH (1 << 5)
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#define DPC_CLR_TMEM_CTR (1 << 6)
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#define DPC_CLR_PIPE_CTR (1 << 7)
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#define DPC_CLR_CMD_CTR (1 << 8)
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#define DPC_CLR_CLOCK_CTR (1 << 9)
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#endif
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@ -8,7 +8,7 @@
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// pre-boot variables
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extern u32 osTvType;
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extern u32 osRomType;
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extern u32 osRomBase;
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extern uintptr_t osRomBase;
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extern u32 osResetType;
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extern u32 osCicId;
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extern u32 osVersion;
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2
spec
2
spec
@ -170,7 +170,7 @@ beginseg
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include "build/src/libultra/voice/voicecontwrite20.o"
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include "build/src/libultra/io/crc.o"
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include "build/src/libultra/os/getactivequeue.o"
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include "build/src/libultra/gu/normalize.o"
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include "build/asm/boot/normalize.text.o"
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include "build/asm/boot/setcompare.text.o"
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include "build/asm/boot/getcompare.text.o"
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include "build/src/libultra/io/dpgetstat.o"
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@ -1,3 +0,0 @@
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#include "global.h"
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#pragma GLOBAL_ASM("asm/non_matchings/boot/normalize/guNormalize.s")
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@ -1,5 +1,5 @@
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#include "global.h"
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u32 osAiGetLength(void) {
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return *(u32*)0xA4500004;
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return HW_REG(AI_LEN_REG, u32);
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}
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@ -1,3 +1,20 @@
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#include "global.h"
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#pragma GLOBAL_ASM("asm/non_matchings/boot/aisetfreq/osAiSetFrequency.s")
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s32 osAiSetFrequency(u32 frequency) {
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u8 bitrate;
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f32 dacRateF = ((f32)osViClock / frequency) + 0.5f;
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u32 dacRate = dacRateF;
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if (dacRate < 132) {
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return -1;
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}
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bitrate = (dacRate / 66);
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if (bitrate > 16) {
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bitrate = 16;
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}
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HW_REG(AI_DACRATE_REG, u32) = dacRate - 1;
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HW_REG(AI_BITRATE_REG, u32) = bitrate - 1;
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return osViClock / (s32)dacRate;
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}
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@ -34,7 +34,7 @@
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* \f[ m(X) X^n = Q(X) p(X) + R(X) \f]
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* (\f$ R(X) \f$ is the *remainder after dividing by \f$ p(X) \f$*).
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* - Therefore, \f$ m(X) X^n - R(X) \f$ is divisible by the generator polynomial. This means that if we append the
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* binary number corresponding to \f$ R(X) \f$ to the message and rerun the algorithm, we will get 0 if now errors have
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* binary number corresponding to \f$ R(X) \f$ to the message and rerun the algorithm, we will get 0 if no errors have
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* been introduced.
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*
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*
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@ -1,5 +1,5 @@
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#include "global.h"
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u32 osDpGetStatus(void) {
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return *(u32*)0xA410000C;
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return HW_REG(DPC_STATUS_REG, u32);
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}
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@ -1,5 +1,5 @@
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#include "global.h"
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void osDpSetStatus(u32 data) {
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*(u32*)0xA410000C = data;
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HW_REG(DPC_STATUS_REG, u32) = data;
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}
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@ -1,23 +1,22 @@
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#include "global.h"
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s32 __osPiRawStartDma(s32 direction, u32 devAddr, void* dramAddr, size_t size) {
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register int stat;
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s32 __osPiRawStartDma(s32 direction, uintptr_t devAddr, void* dramAddr, size_t size) {
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register int status = HW_REG(PI_STATUS_REG, u32);
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stat = *(vu32*)0xA4600010;
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while (stat & (2 | 1)) {
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stat = *(vu32*)0xA4600010;
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while (status & (PI_STATUS_IOBUSY | PI_STATUS_BUSY)) {
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status = HW_REG(PI_STATUS_REG, u32);
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}
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*(u32*)0xA4600000 = osVirtualToPhysical(dramAddr);
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HW_REG(PI_DRAM_ADDR_REG, u32) = osVirtualToPhysical(dramAddr);
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*(u32*)0xA4600004 = ((osRomBase | devAddr) & 0x1fffffff);
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HW_REG(PI_CART_ADDR_REG, u32) = ((osRomBase | devAddr) & 0x1FFFFFFF);
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switch (direction) {
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case 0:
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*(u32*)0xA460000C = size - 1;
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case OS_READ:
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HW_REG(PI_WR_LEN_REG, u32) = size - 1;
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break;
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case 1:
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*(u32*)0xA4600008 = size - 1;
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case OS_WRITE:
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HW_REG(PI_RD_LEN_REG, u32) = size - 1;
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break;
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default:
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return -1;
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@ -1,11 +1,11 @@
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#include "global.h"
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int __osSiDeviceBusy() {
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register u32 status;
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status = *(u32*)0xA4800018;
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if (status & 3) {
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return 1;
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s32 __osSiDeviceBusy() {
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register u32 status = HW_REG(SI_STATUS_REG, u32);
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if (status & (SI_STATUS_DMA_BUSY | SI_STATUS_IO_READ_BUSY)) {
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return true;
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} else {
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return 0;
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return false;
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}
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}
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#include "global.h"
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s32 __osSiRawStartDma(s32 direction, void* dramAddr) {
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if ((*(u32*)0xA4800018 & 0x3) != 0) {
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if (HW_REG(SI_STATUS_REG, u32) & (SI_STATUS_DMA_BUSY | SI_STATUS_IO_READ_BUSY)) {
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return -1;
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}
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if (direction == 1) {
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osWritebackDCache(dramAddr, 64);
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if (direction == OS_WRITE) {
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osWritebackDCache(dramAddr, PIF_RAM_SIZE);
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}
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*(u32*)0xA4800000 = osVirtualToPhysical(dramAddr);
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HW_REG(SI_DRAM_ADDR_REG, u32) = osVirtualToPhysical(dramAddr);
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if (direction == 0) {
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*(u32*)0xA4800004 = 0x1FC007C0;
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if (direction == OS_READ) {
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HW_REG(SI_PIF_ADDR_RD64B_REG, void*) = (void*)PIF_RAM_START;
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} else {
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*(u32*)0xA4800010 = 0x1FC007C0;
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HW_REG(SI_PIF_ADDR_WR64B_REG, void*) = (void*)PIF_RAM_START;
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}
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if (direction == 0) {
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osInvalDCache(dramAddr, 64);
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if (direction == OS_READ) {
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osInvalDCache(dramAddr, PIF_RAM_SIZE);
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}
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return 0;
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}
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@ -5,6 +5,7 @@ s32 __osSpDeviceBusy(void) {
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if (status & (SP_STATUS_DMA_BUSY | SP_STATUS_DMA_FULL | SP_STATUS_IO_FULL)) {
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return true;
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} else {
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return false;
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}
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return false;
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}
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#include "global.h"
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u32 __osSpGetStatus() {
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return *(vu32*)0xA4040010;
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return HW_REG(SP_STATUS_REG, u32);
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}
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#include "global.h"
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s32 __osSpRawStartDma(s32 direction, void* devAddr, void* dramAddr, size_t size) {
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if (__osSpDeviceBusy() != 0) {
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if (__osSpDeviceBusy()) {
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return -1;
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}
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*(vu32*)0xA4040000 = devAddr;
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*(vu32*)0xA4040004 = osVirtualToPhysical(dramAddr);
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HW_REG(SP_MEM_ADDR_REG, u32) = devAddr;
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HW_REG(SP_DRAM_ADDR_REG, u32) = osVirtualToPhysical(dramAddr);
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if (direction == 0) {
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*(vu32*)0xA404000C = size - 1;
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if (direction == OS_READ) {
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HW_REG(SP_WR_LEN_REG, u32) = size - 1;
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} else {
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*(vu32*)0xA4040008 = size - 1;
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HW_REG(SP_RD_LEN_REG, u32) = size - 1;
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}
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return 0;
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#include "global.h"
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void __osSpSetStatus(u32 data) {
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*(vu32*)0xA4040010 = data;
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HW_REG(SP_STATUS_REG, u32) = data;
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}
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@ -17,7 +17,7 @@ void __osViInit(void) {
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__osViNext->modep = &osViModePalLan1;
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} else if (osTvType == OS_TV_MPAL) {
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__osViNext->modep = &osViModeMpalLan1;
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} else {
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} else { // OS_TV_NTSC or OS_TV_UNK28
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__osViNext->modep = &osViModeNtscLan1;
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}
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