mirror of
https://github.com/zeldaret/mm.git
synced 2024-11-23 21:09:52 +00:00
283a37affb
* Cleanup undefined_syms.txt * removed unused from Bba textures * eyegore beamos textures * object_eg Unused -> Beamons * ssh * segment 0x07
666 lines
15 KiB
Plaintext
666 lines
15 KiB
Plaintext
// libultra OS symbols
|
|
|
|
D_80000000 = 0x80000000; // __osExceptionPreamble
|
|
D_80000004 = 0x80000004; // __osExceptionPreamble
|
|
D_80000008 = 0x80000008; // __osExceptionPreamble
|
|
D_8000000C = 0x8000000C; // __osExceptionPreamble
|
|
D_80000010 = 0x80000010; //
|
|
D_80000020 = 0x80000020; //
|
|
|
|
osTvType = 0x80000300;
|
|
osRomType = 0x80000304;
|
|
osRomBase = 0x80000308;
|
|
osResetType = 0x8000030C;
|
|
osCicId = 0x80000310;
|
|
osVersion = 0x80000314;
|
|
osMemSize = 0x80000318;
|
|
osAppNmiBuffer = 0x8000031C;
|
|
|
|
/// OS hardware registers
|
|
|
|
// Signal Processor Registers
|
|
|
|
D_A4040000 = 0xA4040000; // SP_MEM_ADDR_REG
|
|
D_A4040004 = 0xA4040004; // SP_DRAM_ADDR_REG
|
|
D_A4040008 = 0xA4040008; // SP_RD_LEN_REG
|
|
D_A404000C = 0xA404000C; // SP_WR_LEN_REG
|
|
D_A4040010 = 0xA4040010; // SP_STATUS_REG
|
|
D_A4040014 = 0xA4040014; // SP_DMA_FULL_REG
|
|
D_A4040018 = 0xA4040018; // SP_DMA_BUSY_REG
|
|
D_A404001C = 0xA404001C; // SP_SEMAPHORE_REG
|
|
|
|
D_A4080000 = 0xA4080000; // SP PC
|
|
|
|
// Display Processor Command Registers / Rasterizer Interface
|
|
|
|
D_A4100000 = 0xA4100000; // DPC_START_REG
|
|
D_A4100004 = 0xA4100004; // DPC_END_REG
|
|
D_A4100008 = 0xA4100008; // DPC_CURRENT_REG
|
|
D_A410000C = 0xA410000C; // DPC_STATUS_REG
|
|
D_A4100010 = 0xA4100010; // DPC_CLOCK_REG
|
|
D_A4100014 = 0xA4100014; // DPC_BUFBUSY_REG
|
|
D_A4100018 = 0xA4100018; // DPC_PIPEBUSY_REG
|
|
D_A410001C = 0xA410001C; // DPC_TMEM_REG
|
|
|
|
// Display Processor Span Registers
|
|
|
|
D_A4200000 = 0xA4200000; // DPS_TBIST_REG / DP_TMEM_BIST
|
|
D_A4200004 = 0xA4200004; // DPS_TEST_MODE_REG
|
|
D_A4200008 = 0xA4200008; // DPS_BUFTEST_ADDR_REG
|
|
D_A420000C = 0xA420000C; // DPS_BUFTEST_DATA_REG
|
|
|
|
// MIPS Interface Registers
|
|
|
|
D_A4300000 = 0xA4300000; // MI_MODE_REG / MI_INIT_MODE_REG
|
|
D_A4300004 = 0xA4300004; // MI_VERSION_REG
|
|
D_A4300008 = 0xA4300008; // MI_INTR_REG
|
|
D_A430000C = 0xA430000C; // MI_INTR_MASK_REG
|
|
|
|
// Video Interface Registers
|
|
|
|
D_A4400000 = 0xA4400000; // VI_STATUS_REG / VI_CONTROL_REG
|
|
D_A4400004 = 0xA4400004; // VI_DRAM_ADDR_REG / VI_ORIGIN_REG
|
|
D_A4400008 = 0xA4400008; // VI_WIDTH_REG
|
|
D_A440000C = 0xA440000C; // VI_INTR_REG
|
|
D_A4400010 = 0xA4400010; // VI_CURRENT_REG
|
|
D_A4400014 = 0xA4400014; // VI_BURST_REG / VI_TIMING_REG
|
|
D_A4400018 = 0xA4400018; // VI_V_SYNC_REG
|
|
D_A440001C = 0xA440001C; // VI_H_SYNC_REG
|
|
D_A4400020 = 0xA4400020; // VI_LEAP_REG
|
|
D_A4400024 = 0xA4400024; // VI_H_START_REG
|
|
D_A4400028 = 0xA4400028; // VI_V_START_REG
|
|
D_A440002C = 0xA440002C; // VI_V_BURST_REG
|
|
D_A4400030 = 0xA4400030; // VI_X_SCALE_REG
|
|
D_A4400034 = 0xA4400034; // VI_Y_SCALE_REG
|
|
|
|
// Audio Interface Registers
|
|
|
|
D_A4500000 = 0xA4500000; // AI_DRAM_ADDR_REG
|
|
D_A4500004 = 0xA4500004; // AI_LEN_REG
|
|
D_A4500008 = 0xA4500008; // AI_CONTROL_REG
|
|
D_A450000C = 0xA450000C; // AI_STATUS_REG
|
|
D_A4500010 = 0xA4500010; // AI_DACRATE_REG
|
|
D_A4500014 = 0xA4500014; // AI_BITRATE_REG
|
|
|
|
// Peripheral/Parallel Interface Registers
|
|
|
|
D_A4600000 = 0xA4600000; // PI_DRAM_ADDR_REG
|
|
D_A4600004 = 0xA4600004; // PI_CART_ADDR_REG
|
|
D_A4600005 = 0xA4600005;
|
|
D_A4600006 = 0xA4600006;
|
|
D_A4600007 = 0xA4600007;
|
|
D_A4600008 = 0xA4600008; // PI_RD_LEN_REG
|
|
D_A460000C = 0xA460000C; // PI_WR_LEN_REG
|
|
D_A4600010 = 0xA4600010; // PI_STATUS_REG
|
|
D_A4600014 = 0xA4600014; // PI_BSD_DOM1_LAT_REG // PI dom1 latency
|
|
D_A4600018 = 0xA4600018; // PI_BSD_DOM1_PWD_REG // PI dom1 pulse width
|
|
D_A460001C = 0xA460001C; // PI_BSD_DOM1_PGS_REG // PI dom1 page size
|
|
D_A4600020 = 0xA4600020; // PI_BSD_DOM1_RLS_REG // PI dom1 release
|
|
D_A4600024 = 0xA4600024; // PI_BSD_DOM2_LAT_REG // PI dom2 latency
|
|
D_A4600028 = 0xA4600028; // PI_BSD_DOM2_LWD_REG // PI dom2 pulse width
|
|
D_A460002C = 0xA460002C; // PI_BSD_DOM2_PGS_REG // PI dom2 page size
|
|
D_A4600030 = 0xA4600030; // PI_BSD_DOM2_RLS_REG // PI dom2 release
|
|
|
|
// RDRAM Interface Registers
|
|
|
|
D_A4700000 = 0xA4700000; // RI_MODE_REG
|
|
D_A4700004 = 0xA4700004; // RI_CONFIG_REG
|
|
D_A4700008 = 0xA4700008; // RI_CURRENT_LOAD_REG
|
|
D_A470000C = 0xA470000C; // RI_SELECT_REG
|
|
D_A4700010 = 0xA4700010; // RI_REFRESH_REG
|
|
D_A4700014 = 0xA4700014; // RI_LATENCY_REG
|
|
D_A4700018 = 0xA4700018; // RI_RERROR_REG
|
|
D_A470001C = 0xA470001C; // RI_WERROR_REG
|
|
|
|
// Serial Interface Registers
|
|
|
|
D_A4800000 = 0xA4800000; // SI_DRAM_ADDR_REG
|
|
D_A4800004 = 0xA4800004; // SI_PIF_ADDR_RD64B_REG
|
|
D_A4800008 = 0xA4800008; // reserved
|
|
D_A480000C = 0xA480000C; // reserved
|
|
D_A4800010 = 0xA4800010; // SI_PIF_ADDR_WR64B_REG
|
|
D_A4800014 = 0xA4800014; // reserved
|
|
D_A4800018 = 0xA4800018; // SI_STATUS_REG
|
|
|
|
// sys_cfb buffers
|
|
|
|
gFramebuffer1 = 0x80000500;
|
|
gFramebufferHiRes0 = 0x80780000;
|
|
gFramebufferHiRes1 = 0x80000500;
|
|
D_80025D00 = 0x80025D00;
|
|
|
|
// Ucode symbols
|
|
|
|
rspbootTextSize = 0x160;
|
|
rspbootTextEnd = rspbootTextStart + rspbootTextSize;
|
|
aspMainTextEnd = aspMainTextStart + 0x1000;
|
|
aspMainDataEnd = aspMainDataStart + 0x2E0;
|
|
|
|
// Segmented Addresses
|
|
|
|
// segment 0x01
|
|
|
|
D_01000000 = 0x01000000;
|
|
|
|
// segment 0x02
|
|
|
|
D_02000400 = 0x02000400;
|
|
D_02000E60 = 0x02000E60;
|
|
D_02002460 = 0x02002460;
|
|
D_020029A0 = 0x020029A0;
|
|
D_02002AA0 = 0x02002AA0;
|
|
D_02003F20 = 0x02003F20;
|
|
D_0200B998 = 0x0200B998;
|
|
|
|
// segment 0x03
|
|
|
|
// segment 0x04
|
|
|
|
D_0401ED00 = 0x0401ED00;
|
|
D_04023210 = 0x04023210;
|
|
D_04023348 = 0x04023348;
|
|
D_040233B8 = 0x040233B8;
|
|
D_04023428 = 0x04023428;
|
|
D_04029CB0 = 0x04029CB0;
|
|
D_04029CF0 = 0x04029CF0;
|
|
D_0402E510 = 0x0402E510;
|
|
D_04030100 = 0x04030100;
|
|
D_0403F230 = 0x0403F230;
|
|
D_04050D10 = 0x04050D10;
|
|
D_04051180 = 0x04051180;
|
|
D_04051238 = 0x04051238;
|
|
D_04054940 = 0x04054940;
|
|
D_040549A8 = 0x040549A8;
|
|
D_0406AB30 = 0x0406AB30;
|
|
D_040706E0 = 0x040706E0;
|
|
D_04076BC0 = 0x04076BC0;
|
|
D_0407AB70 = 0x0407AB70;
|
|
D_0407D590 = 0x0407D590;
|
|
D_0407E8C0 = 0x0407E8C0;
|
|
D_0407F218 = 0x0407F218;
|
|
|
|
// segment 0x05
|
|
|
|
D_050085F0 = 0x050085F0;
|
|
D_050089D0 = 0x050089D0;
|
|
|
|
// segment 0x06
|
|
|
|
// ovl_Bg_Dblue_Elevator
|
|
|
|
D_060002C8 = 0x060002C8;
|
|
D_060005C4 = 0x060005C4;
|
|
|
|
// ovl_Bg_Dy_Yoseizo
|
|
|
|
D_06008090 = 0x06008090;
|
|
D_0600D1B0 = 0x0600D1B0;
|
|
D_0600D228 = 0x0600D228;
|
|
D_0601C6F4 = 0x0601C6F4;
|
|
D_0601C8B4 = 0x0601C8B4;
|
|
|
|
// ovl_Bg_Lotus
|
|
|
|
D_06000A20 = 0x06000A20;
|
|
D_06000040 = 0x06000040;
|
|
|
|
// ovl_Boss_01
|
|
|
|
D_06000C44 = 0x06000C44;
|
|
D_06001884 = 0x06001884;
|
|
D_0600C338 = 0x0600C338;
|
|
D_0600C498 = 0x0600C498;
|
|
D_0600C5E0 = 0x0600C5E0;
|
|
D_0600C7A8 = 0x0600C7A8;
|
|
D_0600C7C8 = 0x0600C7C8;
|
|
D_0600C7F8 = 0x0600C7F8;
|
|
D_0600E3E8 = 0x0600E3E8;
|
|
D_0600F0A8 = 0x0600F0A8;
|
|
D_0600FDEC = 0x0600FDEC;
|
|
D_0600FF94 = 0x0600FF94;
|
|
D_06010150 = 0x06010150;
|
|
D_06010980 = 0x06010980;
|
|
D_060124CC = 0x060124CC;
|
|
D_06012B70 = 0x06012B70;
|
|
D_06012D10 = 0x06012D10;
|
|
D_06012EBC = 0x06012EBC;
|
|
D_06013480 = 0x06013480;
|
|
D_0601407C = 0x0601407C;
|
|
D_06014F14 = 0x06014F14;
|
|
D_06015A30 = 0x06015A30;
|
|
D_06016168 = 0x06016168;
|
|
D_060164CC = 0x060164CC;
|
|
D_06018438 = 0x06018438;
|
|
D_06019C10 = 0x06019C10;
|
|
D_0601F6A4 = 0x0601F6A4;
|
|
D_060204AC = 0x060204AC;
|
|
D_060213A8 = 0x060213A8;
|
|
D_060220A0 = 0x060220A0;
|
|
D_06022118 = 0x06022118;
|
|
D_060222D0 = 0x060222D0;
|
|
D_06022550 = 0x06022550;
|
|
|
|
// ovl_Boss_05
|
|
|
|
D_060006A4 = 0x060006A4;
|
|
D_06000A5C = 0x06000A5C;
|
|
D_06000ABC = 0x06000ABC;
|
|
D_060024E0 = 0x060024E0;
|
|
D_06002F0C = 0x06002F0C;
|
|
D_06003448 = 0x06003448;
|
|
D_06006240 = 0x06006240;
|
|
D_06006378 = 0x06006378;
|
|
D_06006484 = 0x06006484;
|
|
D_06006E50 = 0x06006E50;
|
|
D_06007488 = 0x06007488;
|
|
D_06007908 = 0x06007908;
|
|
|
|
// ovl_Boss_07
|
|
|
|
D_06000194 = 0x06000194;
|
|
D_06000428 = 0x06000428;
|
|
D_06000D0C = 0x06000D0C;
|
|
D_06002C40 = 0x06002C40;
|
|
D_06002D84 = 0x06002D84;
|
|
D_060031E4 = 0x060031E4;
|
|
D_06003854 = 0x06003854;
|
|
D_06003A64 = 0x06003A64;
|
|
D_060099A0 = 0x060099A0;
|
|
D_06009C7C = 0x06009C7C;
|
|
D_06009EA8 = 0x06009EA8;
|
|
D_0600A194 = 0x0600A194;
|
|
D_0600A400 = 0x0600A400;
|
|
D_0600A6AC = 0x0600A6AC;
|
|
D_0600AE40 = 0x0600AE40;
|
|
D_0600AFB0 = 0x0600AFB0;
|
|
D_0600B020 = 0x0600B020;
|
|
D_0600C7D8 = 0x0600C7D8;
|
|
D_0600CEE8 = 0x0600CEE8;
|
|
D_060149A0 = 0x060149A0;
|
|
D_06016090 = 0x06016090;
|
|
D_06017DE0 = 0x06017DE0;
|
|
D_06019328 = 0x06019328;
|
|
D_06019C58 = 0x06019C58;
|
|
D_06019E48 = 0x06019E48;
|
|
D_0601DEB4 = 0x0601DEB4;
|
|
D_06022BB4 = 0x06022BB4;
|
|
D_06023DAC = 0x06023DAC;
|
|
D_06025018 = 0x06025018;
|
|
D_06025878 = 0x06025878;
|
|
D_06026204 = 0x06026204;
|
|
D_060269EC = 0x060269EC;
|
|
D_06026EA0 = 0x06026EA0;
|
|
D_06027270 = 0x06027270;
|
|
D_0602EE50 = 0x0602EE50;
|
|
D_0602EEC8 = 0x0602EEC8;
|
|
D_0602EEF8 = 0x0602EEF8;
|
|
D_0602EF68 = 0x0602EF68;
|
|
D_0602EF88 = 0x0602EF88;
|
|
D_0602EFE8 = 0x0602EFE8;
|
|
D_0602F640 = 0x0602F640;
|
|
D_0602F840 = 0x0602F840;
|
|
D_06030C40 = 0x06030C40;
|
|
D_06032040 = 0x06032040;
|
|
D_060335F0 = 0x060335F0;
|
|
D_06033F80 = 0x06033F80;
|
|
D_06034E64 = 0x06034E64;
|
|
D_060358C4 = 0x060358C4;
|
|
D_06036A7C = 0x06036A7C;
|
|
D_06037ADC = 0x06037ADC;
|
|
D_0603918C = 0x0603918C;
|
|
D_0603B330 = 0x0603B330;
|
|
D_0603C4E0 = 0x0603C4E0;
|
|
D_0603CBD0 = 0x0603CBD0;
|
|
D_0603D224 = 0x0603D224;
|
|
D_0603D7F0 = 0x0603D7F0;
|
|
D_0603DD1C = 0x0603DD1C;
|
|
D_0603DD30 = 0x0603DD30;
|
|
D_0603ED30 = 0x0603ED30;
|
|
D_0603F130 = 0x0603F130;
|
|
D_06040130 = 0x06040130;
|
|
D_06040930 = 0x06040930;
|
|
D_06040B30 = 0x06040B30;
|
|
D_06041B30 = 0x06041B30;
|
|
D_06042330 = 0x06042330;
|
|
D_06043330 = 0x06043330;
|
|
|
|
// ovl_Boss_Hakugin
|
|
|
|
D_06002054 = 0x06002054;
|
|
D_0600319C = 0x0600319C;
|
|
D_06010488 = 0x06010488;
|
|
D_06010500 = 0x06010500;
|
|
D_06011100 = 0x06011100;
|
|
D_06011178 = 0x06011178;
|
|
D_06011208 = 0x06011208;
|
|
D_06011278 = 0x06011278;
|
|
D_06012ED0 = 0x06012ED0;
|
|
D_06012F40 = 0x06012F40;
|
|
D_06013158 = 0x06013158;
|
|
D_060134D0 = 0x060134D0;
|
|
D_06013828 = 0x06013828;
|
|
D_06014040 = 0x06014040;
|
|
|
|
// ovl_Dm_Tsg
|
|
|
|
D_06002D30 = 0x06002D30;
|
|
D_06011458 = 0x06011458;
|
|
|
|
// ovl_Door_Spiral
|
|
|
|
D_06000590 = 0x06000590;
|
|
D_060007A8 = 0x060007A8;
|
|
D_06000EA0 = 0x06000EA0;
|
|
D_060012C0 = 0x060012C0;
|
|
D_060014C8 = 0x060014C8;
|
|
D_06002110 = 0x06002110;
|
|
D_06004448 = 0x06004448;
|
|
D_060051B8 = 0x060051B8;
|
|
D_06006128 = 0x06006128;
|
|
D_06009278 = 0x06009278;
|
|
D_06012B70 = 0x06012B70;
|
|
D_06013EA8 = 0x06013EA8;
|
|
|
|
// ovl_En_An
|
|
|
|
D_06000308 = 0x06000308;
|
|
D_06000378 = 0x06000378;
|
|
D_06000E70 = 0x06000E70;
|
|
D_060111E8 = 0x060111E8;
|
|
D_06012478 = 0x06012478;
|
|
D_06012618 = 0x06012618;
|
|
|
|
// ovl_En_Bal
|
|
|
|
D_060005FC = 0x060005FC;
|
|
D_06000C78 = 0x06000C78;
|
|
D_0600A6D0 = 0x0600A6D0;
|
|
D_0600B604 = 0x0600B604;
|
|
D_0600CB78 = 0x0600CB78;
|
|
D_0600D530 = 0x0600D530;
|
|
|
|
// ovl_En_Bsb
|
|
|
|
D_06000C50 = 0x06000C50;
|
|
D_06004894 = 0x06004894;
|
|
D_060086BC = 0x060086BC;
|
|
D_0600C3E0 = 0x0600C3E0;
|
|
|
|
// ovl_En_Death
|
|
|
|
D_06000E64 = 0x06000E64;
|
|
D_060015B4 = 0x060015B4;
|
|
D_06001834 = 0x06001834;
|
|
D_06001F80 = 0x06001F80;
|
|
D_06002DE8 = 0x06002DE8;
|
|
D_0600352C = 0x0600352C;
|
|
D_06003CAC = 0x06003CAC;
|
|
D_06006F88 = 0x06006F88;
|
|
D_060073D0 = 0x060073D0;
|
|
D_06009988 = 0x06009988;
|
|
D_06009BA0 = 0x06009BA0;
|
|
D_06009F10 = 0x06009F10;
|
|
D_0600AD08 = 0x0600AD08;
|
|
D_0600B284 = 0x0600B284;
|
|
D_0600B508 = 0x0600B508;
|
|
D_0600CB2C = 0x0600CB2C;
|
|
D_0600CB84 = 0x0600CB84;
|
|
D_0600CBC0 = 0x0600CBC0;
|
|
|
|
// ovl_En_Dt
|
|
|
|
D_0600112C = 0x0600112C;
|
|
D_0600B0CC = 0x0600B0CC;
|
|
|
|
// ovl_En_Encount3
|
|
|
|
D_060009A0 = 0x060009A0;
|
|
|
|
// ovl_En_Ge3
|
|
|
|
D_06001EFC = 0x06001EFC;
|
|
D_0600A808 = 0x0600A808;
|
|
|
|
// ovl_En_Invadepoh
|
|
|
|
D_06000080 = 0x06000080;
|
|
D_060003B0 = 0x060003B0;
|
|
D_06000550 = 0x06000550;
|
|
D_06000560 = 0x06000560;
|
|
D_06000608 = 0x06000608;
|
|
D_060006C8 = 0x060006C8;
|
|
D_06000720 = 0x06000720;
|
|
D_06000998 = 0x06000998;
|
|
D_06001560 = 0x06001560;
|
|
D_06001674 = 0x06001674;
|
|
D_06001BD8 = 0x06001BD8;
|
|
D_06001D80 = 0x06001D80;
|
|
D_060021C8 = 0x060021C8;
|
|
D_06002A8C = 0x06002A8C;
|
|
D_06004010 = 0x06004010;
|
|
D_06004264 = 0x06004264;
|
|
D_06004C30 = 0x06004C30;
|
|
D_06004E50 = 0x06004E50;
|
|
D_06004E98 = 0x06004E98;
|
|
D_06007328 = 0x06007328;
|
|
D_060080F0 = 0x060080F0;
|
|
D_06009E58 = 0x06009E58;
|
|
D_0600A174 = 0x0600A174;
|
|
D_0600FFC8 = 0x0600FFC8;
|
|
D_060107C8 = 0x060107C8;
|
|
D_06010FC8 = 0x06010FC8;
|
|
D_060117C8 = 0x060117C8;
|
|
D_06011AD8 = 0x06011AD8;
|
|
D_06011FC8 = 0x06011FC8;
|
|
D_060122D8 = 0x060122D8;
|
|
D_060127C8 = 0x060127C8;
|
|
D_06012AD8 = 0x06012AD8;
|
|
D_06012BC8 = 0x06012BC8;
|
|
D_06012FC8 = 0x06012FC8;
|
|
D_060132D8 = 0x060132D8;
|
|
D_060133C8 = 0x060133C8;
|
|
D_06013928 = 0x06013928;
|
|
D_06013AD8 = 0x06013AD8;
|
|
D_06014088 = 0x06014088;
|
|
D_060142D8 = 0x060142D8;
|
|
D_06014AD8 = 0x06014AD8;
|
|
D_06014ED8 = 0x06014ED8;
|
|
D_060152D8 = 0x060152D8;
|
|
D_06015C28 = 0x06015C28;
|
|
D_060156D8 = 0x060156D8;
|
|
D_06016720 = 0x06016720;
|
|
|
|
// ovl_En_Invadepoh_Demo
|
|
|
|
D_06000080 = 0x06000080;
|
|
D_06000550 = 0x06000550;
|
|
D_06000560 = 0x06000560;
|
|
D_06001D80 = 0x06001D80;
|
|
D_06004010 = 0x06004010;
|
|
D_06004264 = 0x06004264;
|
|
D_06004C30 = 0x06004C30;
|
|
D_06004E50 = 0x06004E50;
|
|
D_06004E98 = 0x06004E98;
|
|
D_06011FC8 = 0x06011FC8;
|
|
D_06012FC8 = 0x06012FC8;
|
|
D_06013928 = 0x06013928;
|
|
D_06016588 = 0x06016588;
|
|
|
|
// ovl_En_Jso
|
|
|
|
D_060081F4 = 0x060081F4;
|
|
D_0600AA00 = 0x0600AA00;
|
|
|
|
// ovl_En_Jso2
|
|
|
|
D_06002ED8 = 0x06002ED8;
|
|
D_06003168 = 0x06003168;
|
|
D_060081F4 = 0x060081F4;
|
|
|
|
// ovl_En_Kitan
|
|
|
|
D_06000CE8 = 0x06000CE8;
|
|
D_0600190C = 0x0600190C;
|
|
D_06002770 = 0x06002770;
|
|
D_06007FA8 = 0x06007FA8;
|
|
|
|
// ovl_En_Knight
|
|
|
|
D_060005A8 = 0x060005A8;
|
|
D_060009E0 = 0x060009E0;
|
|
D_06000D9C = 0x06000D9C;
|
|
D_06001CDC = 0x06001CDC;
|
|
D_06002174 = 0x06002174;
|
|
D_06003008 = 0x06003008;
|
|
D_060031F0 = 0x060031F0;
|
|
D_06003650 = 0x06003650;
|
|
D_060040E0 = 0x060040E0;
|
|
D_06004620 = 0x06004620;
|
|
D_06004974 = 0x06004974;
|
|
D_06005D30 = 0x06005D30;
|
|
D_06005E78 = 0x06005E78;
|
|
D_06006754 = 0x06006754;
|
|
D_06006EF8 = 0x06006EF8;
|
|
D_060079D4 = 0x060079D4;
|
|
D_06008390 = 0x06008390;
|
|
D_06008524 = 0x06008524;
|
|
D_060089E4 = 0x060089E4;
|
|
D_06008D80 = 0x06008D80;
|
|
D_06009538 = 0x06009538;
|
|
D_06009D8C = 0x06009D8C;
|
|
D_0600A530 = 0x0600A530;
|
|
D_0600A88C = 0x0600A88C;
|
|
D_0600AFAC = 0x0600AFAC;
|
|
D_0600B5D4 = 0x0600B5D4;
|
|
D_0600BCF4 = 0x0600BCF4;
|
|
D_0600C384 = 0x0600C384;
|
|
D_0600C7F0 = 0x0600C7F0;
|
|
D_0600CDE0 = 0x0600CDE0;
|
|
D_0600D870 = 0x0600D870;
|
|
D_0600DDCC = 0x0600DDCC;
|
|
D_0600E15C = 0x0600E15C;
|
|
D_0600E45C = 0x0600E45C;
|
|
D_0600E7F4 = 0x0600E7F4;
|
|
D_0600EA90 = 0x0600EA90;
|
|
D_0600EF44 = 0x0600EF44;
|
|
D_0600FC78 = 0x0600FC78;
|
|
D_0601024C = 0x0601024C;
|
|
D_06010E98 = 0x06010E98;
|
|
D_06011298 = 0x06011298;
|
|
D_06012400 = 0x06012400;
|
|
D_06012DB0 = 0x06012DB0;
|
|
D_06013020 = 0x06013020;
|
|
D_060188F8 = 0x060188F8;
|
|
D_060189F0 = 0x060189F0;
|
|
D_06018AF0 = 0x06018AF0;
|
|
D_06018BC4 = 0x06018BC4;
|
|
D_060201A8 = 0x060201A8;
|
|
D_06020374 = 0x06020374;
|
|
D_06020950 = 0x06020950;
|
|
D_0602105C = 0x0602105C;
|
|
D_06021B10 = 0x06021B10;
|
|
D_06021E34 = 0x06021E34;
|
|
D_06022728 = 0x06022728;
|
|
D_06022CAC = 0x06022CAC;
|
|
|
|
// ovl_En_Mnk
|
|
|
|
D_06003584 = 0x06003584;
|
|
D_06005150 = 0x06005150;
|
|
D_060082C8 = 0x060082C8;
|
|
D_06008814 = 0x06008814;
|
|
D_06009CC0 = 0x06009CC0;
|
|
D_060105DC = 0x060105DC;
|
|
D_06019B88 = 0x06019B88;
|
|
D_0601D518 = 0x0601D518;
|
|
|
|
// ovl_En_Okuta
|
|
|
|
D_0600044C = 0x0600044C;
|
|
D_06003250 = 0x06003250;
|
|
D_060033D0 = 0x060033D0;
|
|
D_06003958 = 0x06003958;
|
|
D_06003B24 = 0x06003B24;
|
|
D_06003EE4 = 0x06003EE4;
|
|
D_06004204 = 0x06004204;
|
|
D_0600466C = 0x0600466C;
|
|
|
|
// ovl_En_Po_Composer
|
|
|
|
D_0600188C = 0x0600188C;
|
|
D_06006E08 = 0x06006E08;
|
|
D_06006EA8 = 0x06006EA8;
|
|
D_06006F38 = 0x06006F38;
|
|
D_06006FD8 = 0x06006FD8;
|
|
D_06009930 = 0x06009930;
|
|
|
|
// ovl_En_Takaraya
|
|
|
|
D_06000968 = 0x06000968;
|
|
D_06001384 = 0x06001384;
|
|
D_06008FC8 = 0x06008FC8;
|
|
D_06009890 = 0x06009890;
|
|
D_0600A280 = 0x0600A280;
|
|
D_0600AD98 = 0x0600AD98;
|
|
|
|
// ovl_En_Wdhand
|
|
|
|
D_060000F4 = 0x060000F4;
|
|
D_06000364 = 0x06000364;
|
|
D_06000534 = 0x06000534;
|
|
D_06000854 = 0x06000854;
|
|
D_060014C0 = 0x060014C0;
|
|
D_060015B0 = 0x060015B0;
|
|
D_06001E20 = 0x06001E20;
|
|
|
|
// ovl_En_Zl4
|
|
|
|
D_06013328 = 0x06013328;
|
|
|
|
// ovl_Obj_Boyo
|
|
|
|
D_06000300 = 0x06000300;
|
|
D_06000E88 = 0x06000E88;
|
|
|
|
// ovl_Obj_Mine
|
|
|
|
D_06000030 = 0x06000030;
|
|
D_06002068 = 0x06002068;
|
|
D_06002188 = 0x06002188;
|
|
|
|
// ovl_Obj_Takaraya_Wall
|
|
|
|
D_06000B70 = 0x06000B70;
|
|
D_06000D60 = 0x06000D60;
|
|
|
|
// segment 0x07
|
|
|
|
// segment 0x08
|
|
|
|
D_08000000 = 0x08000000;
|
|
|
|
// segment 0x09
|
|
|
|
// segment 0x0A
|
|
|
|
D_0A000D40 = 0x0A000D40;
|
|
|
|
// segment 0x0B
|
|
|
|
// segment 0x0C
|
|
|
|
D_0C000000 = 0x0C000000;
|
|
|
|
// segment 0x0E
|
|
|
|
D_0E000000 = 0x0E000000;
|
|
|
|
// TODO the following are fake and are offsets into the structure at D_0E000000
|
|
D_0E000140 = 0x0E000140;
|
|
D_0E0001C8 = 0x0E0001C8;
|
|
D_0E0002C8 = 0x0E0002C8;
|
|
|
|
// segment 0x0F
|
|
|
|
D_0F000000 = 0x0F000000;
|