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Decompile sub_0800525c, move stuff into sram subdir

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This commit is contained in:
buffet 2022-03-31 21:16:55 +00:00
parent a25c5b1982
commit c7346d7a76
8 changed files with 136 additions and 146 deletions
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2
.gitignore vendored
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@ -1,4 +1,4 @@
/src/*.s
/src/**/*.s
*.gba
*.elf

7
Makefile
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@ -38,7 +38,7 @@ CFLAGS = -O2 -mthumb-interwork -fhex-asm
CPPFLAGS = -nostdinc -Isrc/
# Objects
CSRC = $(wildcard src/*.c)
CSRC = $(wildcard src/*.c) $(wildcard src/sram/*.c)
.PRECIOUS: $(CSRC:.c=.s)
ASMSRC = $(CSRC:.c=.s) $(wildcard asm/*.s)
OBJ = $(ASMSRC:.s=.o)
@ -77,7 +77,7 @@ clean:
$Q$(RM) $(DUMPS)
$(MSG) RM \*.o
$Q$(RM) $(OBJ)
$(MSG) RM src/\*.s
$(MSG) RM src/\*\*/\*.s
$Q$(RM) $(CSRC:.c=.s)
$(MSG) RM $(GBAFIX)
$Q$(RM) $(GBAFIX)
@ -118,6 +118,9 @@ $(ELF) $(MAP): $(OBJ) linker.ld
$(MSG) CC $@
$Q$(CPP) $(CPPFLAGS) $< | $(CC) -o $@ $(CFLAGS) && printf '\t.align 2, 0 @ dont insert nops\n' >> $@
src/sram/%.s: CFLAGS = -O1 -mthumb-interwork -fhex-asm
src/sram/%.s: src/sram/%.c
tools/%: tools/%.c
$(MSG) HOSTCC $@
$Q$(HOSTCC) $< $(HOSTCFLAGS) $(HOSTCPPFLAGS) -o $@

116
asm/disasm_0x080051d4.s
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@ -74,119 +74,3 @@ lbl_08005240:
pop {r4, r5, r6}
pop {r0}
bx r0
thumb_func_start sub_0800525c
sub_0800525c: @ 0x0800525c
push {r4, r5, lr}
adds r5, r0, #0
adds r4, r1, #0
adds r3, r2, #0
ldr r2, lbl_08005294 @ =0x04000204
ldrh r0, [r2]
ldr r1, lbl_08005298 @ =0x0000fffc
ands r0, r1
movs r1, #3
orrs r0, r1
strh r0, [r2]
subs r3, #1
movs r0, #1
rsbs r0, r0, #0
cmp r3, r0
beq lbl_0800528c
adds r1, r0, #0
lbl_0800527e:
ldrb r0, [r5]
strb r0, [r4]
adds r5, #1
adds r4, #1
subs r3, #1
cmp r3, r1
bne lbl_0800527e
lbl_0800528c:
pop {r4, r5}
pop {r0}
bx r0
.align 2, 0
lbl_08005294: .4byte 0x04000204
lbl_08005298: .4byte 0x0000fffc
thumb_func_start sub_0800529c
sub_0800529c: @ 0x0800529c
push {r4, r5, lr}
adds r5, r0, #0
adds r3, r1, #0
subs r4, r2, #1
cmp r2, #0
beq lbl_080052c2
movs r2, #1
rsbs r2, r2, #0
lbl_080052ac:
ldrb r1, [r3]
ldrb r0, [r5]
adds r5, #1
adds r3, #1
cmp r1, r0
beq lbl_080052bc
subs r0, r3, #1
b lbl_080052c4
lbl_080052bc:
subs r4, #1
cmp r4, r2
bne lbl_080052ac
lbl_080052c2:
movs r0, #0
lbl_080052c4:
pop {r4, r5}
pop {r1}
bx r1
.align 2, 0
thumb_func_start sub_080052cc
sub_080052cc: @ 0x080052cc
push {r4, r5, r6, lr}
sub sp, #0xc0
adds r4, r0, #0
adds r5, r1, #0
adds r6, r2, #0
ldr r2, lbl_080052f8 @ =0x04000204
ldrh r0, [r2]
ldr r1, lbl_080052fc @ =0x0000fffc
ands r0, r1
movs r1, #3
orrs r0, r1
strh r0, [r2]
ldr r3, lbl_08005300 @ =sub_0800529c
movs r0, #1
bics r3, r0
mov r2, sp
ldr r0, lbl_08005304 @ =sub_080052cc
ldr r1, lbl_08005300 @ =sub_0800529c
subs r0, r0, r1
lsls r0, r0, #0xf
b lbl_08005314
.align 2, 0
lbl_080052f8: .4byte 0x04000204
lbl_080052fc: .4byte 0x0000fffc
lbl_08005300: .4byte sub_0800529c
lbl_08005304: .4byte sub_080052cc
lbl_08005308:
ldrh r0, [r3]
strh r0, [r2]
adds r3, #2
adds r2, #2
subs r0, r1, #1
lsls r0, r0, #0x10
lbl_08005314:
lsrs r1, r0, #0x10
cmp r1, #0
bne lbl_08005308
mov r3, sp
adds r3, #1
adds r0, r4, #0
adds r1, r5, #0
adds r2, r6, #0
bl _call_via_r3
add sp, #0xc0
pop {r4, r5, r6}
pop {r1}
bx r1

84
asm/disasm_0x0800529c.s Normal file
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@ -0,0 +1,84 @@
.include "asm/macros.inc"
.syntax unified
thumb_func_start sub_0800529c
sub_0800529c: @ 0x0800529c
push {r4, r5, lr}
adds r5, r0, #0
adds r3, r1, #0
subs r4, r2, #1
cmp r2, #0
beq lbl_080052c2
movs r2, #1
rsbs r2, r2, #0
lbl_080052ac:
ldrb r1, [r3]
ldrb r0, [r5]
adds r5, #1
adds r3, #1
cmp r1, r0
beq lbl_080052bc
subs r0, r3, #1
b lbl_080052c4
lbl_080052bc:
subs r4, #1
cmp r4, r2
bne lbl_080052ac
lbl_080052c2:
movs r0, #0
lbl_080052c4:
pop {r4, r5}
pop {r1}
bx r1
.align 2, 0
thumb_func_start sub_080052cc
sub_080052cc: @ 0x080052cc
push {r4, r5, r6, lr}
sub sp, #0xc0
adds r4, r0, #0
adds r5, r1, #0
adds r6, r2, #0
ldr r2, lbl_080052f8 @ =0x04000204
ldrh r0, [r2]
ldr r1, lbl_080052fc @ =0x0000fffc
ands r0, r1
movs r1, #3
orrs r0, r1
strh r0, [r2]
ldr r3, lbl_08005300 @ =sub_0800529c
movs r0, #1
bics r3, r0
mov r2, sp
ldr r0, lbl_08005304 @ =sub_080052cc
ldr r1, lbl_08005300 @ =sub_0800529c
subs r0, r0, r1
lsls r0, r0, #0xf
b lbl_08005314
.align 2, 0
lbl_080052f8: .4byte 0x04000204
lbl_080052fc: .4byte 0x0000fffc
lbl_08005300: .4byte sub_0800529c
lbl_08005304: .4byte sub_080052cc
lbl_08005308:
ldrh r0, [r3]
strh r0, [r2]
adds r3, #2
adds r2, #2
subs r0, r1, #1
lsls r0, r0, #0x10
lbl_08005314:
lsrs r1, r0, #0x10
cmp r1, #0
bne lbl_08005308
mov r3, sp
adds r3, #1
adds r0, r4, #0
adds r1, r5, #0
adds r2, r6, #0
bl _call_via_r3
add sp, #0xc0
pop {r4, r5, r6}
pop {r1}
bx r1

4
linker.ld
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@ -62,7 +62,9 @@ SECTIONS {
asm/disasm_0x08000c48.o(.text);
asm/syscalls.o(.text);
asm/disasm_0x080051d4.o(.text);
src/sub_08005330.o(.text);
src/sram/sub_0800525c.o(.text);
asm/disasm_0x0800529c.o(.text);
src/sram/sub_08005330.o(.text);
asm/disasm_0x08005368.o(.text);
asm/libgcc.o(.text);
asm/disasm_0x0808af18.o(.text);

55
src/gba/waitstate.h
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@ -3,37 +3,40 @@
#define REG_WAITCNT (REG_BASE + 0x204)
enum waitstate {
WAIT_SRAM_4CYCLES = 0,
WAIT_SRAM_3CYCLES = 1 << 0,
WAIT_SRAM_2CYCLES = 1 << 1,
WAIT_SRAM_8CYCLES = 1 << 0 | 1 << 1,
#define WAIT_SRAM_4CYCLES 0
#define WAIT_SRAM_3CYCLES (1 << 0)
#define WAIT_SRAM_2CYCLES (1 << 1)
#define WAIT_SRAM_8CYCLES (1 << 0 | 1 << 1)
#define WAIT_SRAM_CYCLES_MASK (1 << 0 | 1 << 1)
WAIT_BANK0_4CYCLES = 0,
WAIT_BANK0_3CYCLES = 1 << 2,
WAIT_BANK0_2CYCLES = 1 << 3,
WAIT_BANK0_8CYCLES = 1 << 2 | 1 << 3,
WAIT_BANK0_SUBSEQUENT_1CYCLE = 1 << 4,
#define WAIT_BANK0_4CYCLES 0
#define WAIT_BANK0_3CYCLES (1 << 2)
#define WAIT_BANK0_2CYCLES (1 << 3)
#define WAIT_BANK0_8CYCLES (1 << 2 | 1 << 3)
#define WAIT_BANK0_SUBSEQUENT_1CYCLE (1 << 4)
#define WAIT_BANK0_CYCLES_MASK (1 << 2 | 1 << 3 | 1 << 4)
WAIT_BANK1_4CYCLES = 0,
WAIT_BANK1_3CYCLES = 1 << 5,
WAIT_BANK1_2CYCLES = 1 << 6,
WAIT_BANK1_8CYCLES = 1 << 5 | 1 << 6,
WAIT_BANK1_SUBSEQUENT_1CYCLE = 1 << 7,
#define WAIT_BANK1_4CYCLES 0
#define WAIT_BANK1_3CYCLES (1 << 5)
#define WAIT_BANK1_2CYCLES (1 << 6)
#define WAIT_BANK1_8CYCLES (1 << 5 | 1 << 6)
#define WAIT_BANK1_SUBSEQUENT_1CYCLE (1 << 7)
#define WAIT_BANK1_CYCLES_MASK (1 << 5 | 1 << 6 | 1 << 7)
WAIT_BANK2_4CYCLES = 0,
WAIT_BANK2_3CYCLES = 1 << 8,
WAIT_BANK2_2CYCLES = 1 << 9,
WAIT_BANK2_8CYCLES = 1 << 8 | 1 << 9,
WAIT_BANK2_SUBSEQUENT_1CYCLE = 1 << 10,
#define WAIT_BANK2_4CYCLES 0
#define WAIT_BANK2_3CYCLES (1 << 8)
#define WAIT_BANK2_2CYCLES (1 << 9)
#define WAIT_BANK2_8CYCLES (1 << 8 | 1 << 9)
#define WAIT_BANK2_SUBSEQUENT_1CYCLE (1 << 10)
#define WAIT_BANK2_CYCLES_MASK (1 << 8 | 1 << 9 | 1 << 10)
WAIT_TERMOUT_4_19MHZ = 1 << 11,
WAIT_TERMOUT_8_38MHZ = 1 << 12,
WAIT_TERMOUT_16_76MHZ = 1 << 11 | 1 << 12,
#define WAIT_TERMOUT_4_19MHZ (1 << 11)
#define WAIT_TERMOUT_8_38MHZ (1 << 12)
#define WAIT_TERMOUT_16_76MHZ (1 << 11 | 1 << 12)
#define WAIT_TERMOUT_MASK (1 << 11 | 1 << 12)
WAIT_PREFETCH = 1 << 13,
#define WAIT_PREFETCH (1 << 13)
WAIT_GAMEPACK_CGB = 1 << 14,
};
#define WAIT_GAMEPACK_CGB (1 << 14)
#endif /* GBA_WAITSTATE_H */

14
src/sram/sub_0800525c.c Normal file
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@ -0,0 +1,14 @@
#include "gba.h"
#include "io.h"
#include "types.h"
void
sub_0800525c(u8 *src, u8 *dest, u32 size)
{
u16 w = read16(REG_WAITCNT) & ~WAIT_SRAM_8CYCLES | WAIT_SRAM_8CYCLES;
write16(REG_WAITCNT, w);
while (size-- != 0) {
*dest++ = *src++;
}
}

0
src/sub_08005330.c → src/sram/sub_08005330.c
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