mirror of
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libultra files and directories restructure (#1038)
* Restructure files, begin header restructure * Format * us2dex * Fix parallel spelling Co-authored-by: JoshDuMan <40190173+JoshDuMan@users.noreply.github.com> * Use OS_K0_TO_PHYSICAL in place of VIRTUAL_TO_PHYSICAL in osAiSetNextBuffer * Uppercase hex, exception vector address defines * Interrupt flags 1 Co-authored-by: Dragorn421 <Dragorn421@users.noreply.github.com> * Interrupt flags 2 Co-authored-by: Dragorn421 <Dragorn421@users.noreply.github.com> Co-authored-by: JoshDuMan <40190173+JoshDuMan@users.noreply.github.com> Co-authored-by: Dragorn421 <Dragorn421@users.noreply.github.com>
This commit is contained in:
Tharo
GitHub
parent
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commit
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38
Makefile
38
Makefile
@ -67,7 +67,7 @@ INC := -Iinclude -Isrc -Iassets -Ibuild -I.
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# Check code syntax with host compiler
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CHECK_WARNINGS := -Wall -Wextra -Wno-format-security -Wno-unknown-pragmas -Wno-unused-parameter -Wno-unused-variable -Wno-missing-braces -Wno-int-conversion
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CC_CHECK := gcc -fno-builtin -fsyntax-only -fsigned-char -std=gnu90 -D _LANGUAGE_C -D NON_MATCHING $(INC) -include stdarg.h $(CHECK_WARNINGS)
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CC_CHECK := gcc -fno-builtin -fsyntax-only -fsigned-char -std=gnu90 -D _LANGUAGE_C -D NON_MATCHING $(INC) $(CHECK_WARNINGS)
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CPP := cpp
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MKLDSCRIPT := tools/mkldscript
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@ -126,15 +126,6 @@ TEXTURE_FILES_OUT := $(foreach f,$(TEXTURE_FILES_PNG:.png=.inc.c),build/$f) \
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# create build directories
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$(shell mkdir -p build/baserom build/assets/text $(foreach dir,$(SRC_DIRS) $(ASM_DIRS) $(ASSET_BIN_DIRS),build/$(dir)))
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build/src/libultra_boot_O1/%.o: OPTFLAGS := -O1
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build/src/libultra_boot_O2/%.o: OPTFLAGS := -O2
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build/src/libultra_code_O1/%.o: OPTFLAGS := -O1
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build/src/libultra_code_O2/%.o: OPTFLAGS := -O2
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build/src/libultra_code_O2_g3/%.o: OPTFLAGS := -O2 -g3
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build/src/libultra_boot_O1/ll.o: MIPS_VERSION := -mips3 -32
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build/src/libultra_code_O1/llcvt.o: MIPS_VERSION := -mips3 -32
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build/src/code/fault.o: CFLAGS += -trapuv
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build/src/code/fault.o: OPTFLAGS := -O2 -g3
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build/src/code/fault_drawer.o: CFLAGS += -trapuv
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@ -144,11 +135,24 @@ build/src/code/code_801068B0.o: OPTFLAGS := -g
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build/src/code/code_80106860.o: OPTFLAGS := -g
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build/src/code/code_801067F0.o: OPTFLAGS := -g
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build/src/libultra_boot_O1/%.o: CC := $(CC_OLD)
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build/src/libultra_boot_O2/%.o: CC := $(CC_OLD)
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build/src/libultra_code_O1/%.o: CC := $(CC_OLD)
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build/src/libultra_code_O2/%.o: CC := $(CC_OLD)
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build/src/libultra_code_O2_g3/%.o: CC := $(CC_OLD)
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build/src/libultra/libc/absf.o: OPTFLAGS := -O2 -g3
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build/src/libultra/libc/sqrt.o: OPTFLAGS := -O2 -g3
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build/src/libultra/libc/ll.o: OPTFLAGS := -O1
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build/src/libultra/libc/ll.o: MIPS_VERSION := -mips3 -32
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build/src/libultra/libc/llcvt.o: OPTFLAGS := -O1
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build/src/libultra/libc/llcvt.o: MIPS_VERSION := -mips3 -32
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build/src/libultra/os/%.o: OPTFLAGS := -O1
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build/src/libultra/io/%.o: OPTFLAGS := -O2
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build/src/libultra/libc/%.o: OPTFLAGS := -O2
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build/src/libultra/rmon/%.o: OPTFLAGS := -O2
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build/src/libultra/gu/%.o: OPTFLAGS := -O2
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build/src/libultra/gu/%.o: CC := $(CC_OLD)
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build/src/libultra/io/%.o: CC := $(CC_OLD)
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build/src/libultra/libc/%.o: CC := $(CC_OLD)
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build/src/libultra/os/%.o: CC := $(CC_OLD)
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build/src/libultra/rmon/%.o: CC := $(CC_OLD)
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build/src/code/jpegutils.o: CC := $(CC_OLD)
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build/src/code/jpegdecoder.o: CC := $(CC_OLD)
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@ -248,13 +252,13 @@ build/src/%.o: src/%.c
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$(CC_CHECK) $<
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@$(OBJDUMP) -d $@ > $(@:.o=.s)
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build/src/libultra_boot_O1/ll.o: src/libultra_boot_O1/ll.c
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build/src/libultra/libc/ll.o: src/libultra/libc/ll.c
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$(CC) -c $(CFLAGS) $(MIPS_VERSION) $(OPTFLAGS) -o $@ $<
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$(CC_CHECK) $<
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python3 tools/set_o32abi_bit.py $@
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@$(OBJDUMP) -d $@ > $(@:.o=.s)
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build/src/libultra_code_O1/llcvt.o: src/libultra_code_O1/llcvt.c
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build/src/libultra/libc/llcvt.o: src/libultra/libc/llcvt.c
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$(CC) -c $(CFLAGS) $(MIPS_VERSION) $(OPTFLAGS) -o $@ $<
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$(CC_CHECK) $<
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python3 tools/set_o32abi_bit.py $@
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@ -66,7 +66,6 @@ void LogUtils_CheckValidPointer(const char* exp, void* ptr, const char* file, s3
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void LogUtils_LogThreadId(const char* name, s32 line);
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void LogUtils_HungupThread(const char* name, s32 line);
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void LogUtils_ResetHungup(void);
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void* proutSprintf(void* dst, const char* fmt, u32 size);
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s32 vsprintf(char* dst, const char* fmt, va_list args);
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s32 sprintf(char* dst, const char* fmt, ...);
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void __osPiCreateAccessQueue(void);
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@ -76,7 +75,6 @@ s32 osSendMesg(OSMesgQueue* mq, OSMesg mesg, s32 flag);
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void osStopThread(OSThread* thread);
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void osViExtendVStart(u32 arg0);
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s32 osRecvMesg(OSMesgQueue* mq, OSMesg* msg, s32 flag);
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void __createSpeedParam(void);
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void __osInitialize_common(void);
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void __osInitialize_autodetect(void);
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void __osExceptionPreamble();
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@ -100,9 +98,8 @@ void __osDevMgrMain(void* arg);
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s32 __osPiRawStartDma(s32 dir, u32 cartAddr, void* dramAddr, size_t size);
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u32 osVirtualToPhysical(void* vaddr);
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void osViBlack(u8 active);
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s32 __osSiRawReadIo(void* a0, u32* a1);
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s32 __osSiRawReadIo(void* devAddr, u32* dst);
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OSId osGetThreadId(OSThread* thread);
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OSIntMask osSetIntMask(OSIntMask);
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void osViSetMode(OSViMode* mode);
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u32 __osProbeTLB(void*);
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u32 osGetMemSize(void);
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@ -130,10 +127,10 @@ void __osTimerInterrupt(void);
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void __osSetTimerIntr(OSTime time);
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OSTime __osInsertTimer(OSTimer* timer);
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u32 osGetCount(void);
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void __osSetGlobalIntMask(u32 mask);
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void __osSetGlobalIntMask(OSHWIntr mask);
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void __osSetCompare(u32);
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void* bcopy(void* __src, void* __dest, u32 __n);
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void __osResetGlobalIntMask(u32 mask);
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void __osResetGlobalIntMask(OSHWIntr mask);
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s32 __osDisableInt(void);
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void __osRestoreInt(s32);
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void __osViInit(void);
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@ -153,15 +150,12 @@ void _Litob(_Pft* args, u8 type);
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ldiv_t ldiv(s32 num, s32 denom);
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lldiv_t lldiv(s64 num, s64 denom);
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void _Ldtob(_Pft* args, u8 type);
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s32 __osSiRawWriteIo(void* a0, u32 a1);
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s32 __osSiRawWriteIo(void* devAddr, u32 val);
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void osCreateViManager(OSPri pri);
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void viMgrMain(void* vargs);
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OSViContext* __osViGetCurrentContext(void);
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void osStartThread(OSThread* thread);
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void osViSetYScale(f32 scale);
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void osViSetXScale(f32 value);
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void __osSetHWIntrRoutine(OSHWIntr interrupt, s32 (*handler)(void), void* sp);
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void __osGetHWIntrRoutine(OSHWIntr interrupt, s32 (**handlerOut)(void), void** spOut);
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void __osSetWatchLo(u32);
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EnItem00* Item_DropCollectible(GlobalContext* globalCtx, Vec3f* spawnPos, s16 params);
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@ -1956,8 +1950,8 @@ void Audio_PreNMIInternal(void);
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s32 func_800E6680(void);
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u32 Audio_NextRandom(void);
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void Audio_InitMesgQueues(void);
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void Audio_osInvalDCache(void* buf, s32 size);
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void Audio_osWritebackDCache(void* mem, s32 size);
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void Audio_InvalDCache(void* buf, s32 size);
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void Audio_WritebackDCache(void* mem, s32 size);
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s32 osAiSetNextBuffer(void*, u32);
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void Audio_InitNoteSub(Note* note, NoteSubEu* sub, NoteSubAttributes* attrs);
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void Audio_NoteSetResamplingRate(NoteSubEu* noteSubEu, f32 resamplingRateInput);
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@ -2265,9 +2259,6 @@ s16 sins(u16);
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OSTask* _VirtualToPhysicalTask(OSTask* intp);
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void osSpTaskLoad(OSTask* task);
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void osSpTaskStartGo(OSTask* task);
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s32 osSetRumble(OSPfs* pfs, u32 vibrate);
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void osSetUpMempakWrite(s32 channel, OSPifRam* buf);
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s32 osProbeRumblePak(OSMesgQueue* ctrlrqueue, OSPfs* pfs, u32 channel);
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void __osSiCreateAccessQueue(void);
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void __osSiGetAccess(void);
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void __osSiRelAccess(void);
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@ -1,13 +1,16 @@
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#ifndef ULTRA64_H
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#define ULTRA64_H
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#include "stddef.h"
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#include "stdbool.h"
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#include "math.h"
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#include "ultra64/types.h"
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#include "unk.h"
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#include "ultra64/types.h"
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#include "ultra64/interrupt.h"
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#include "libc/stdarg.h"
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#include "libc/stdbool.h"
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#include "libc/stddef.h"
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#include "libc/stdlib.h"
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#include "libc/math.h"
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#include "ultra64/exception.h"
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#include "ultra64/rcp.h"
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#include "ultra64/rdp.h"
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#include "ultra64/rsp.h"
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@ -19,10 +22,11 @@
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#include "ultra64/gu.h"
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#include "ultra64/vi.h"
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#include "ultra64/pi.h"
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#include "ultra64/hardware.h"
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#include "ultra64/controller.h"
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#include "ultra64/printf.h"
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#include "ultra64/mbi.h"
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#include "ultra64/pfs.h"
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#include "ultra64/motor.h"
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#include "ultra64/r4300.h"
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#endif
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@ -2,249 +2,212 @@
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#define ULTRA64_ABI_H
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/* Audio commands: */
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/*
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#define A_SPNOOP 0
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#define A_ADPCM 1
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#define A_CLEARBUFF 2
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#define A_ENVMIXER 3
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#define A_LOADBUFF 4
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#define A_RESAMPLE 5
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#define A_SAVEBUFF 6
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#define A_SEGMENT 7
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#define A_SETBUFF 8
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#define A_SETVOL 9
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#define A_DMEMMOVE 10
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#define A_LOADADPCM 11
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#define A_MIXER 12
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#define A_INTERLEAVE 13
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#define A_POLEF 14
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#define A_SETLOOP 15
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*/
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#define A_SPNOOP 0
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#define A_ADPCM 1
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#define A_CLEARBUFF 2
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#define A_UNK3 3
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#define A_ADDMIXER 4
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#define A_RESAMPLE 5
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#define A_RESAMPLE_ZOH 6
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#define A_FILTER 7
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#define A_SETBUFF 8
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#define A_DUPLICATE 9
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#define A_DMEMMOVE 10
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#define A_LOADADPCM 11
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#define A_MIXER 12
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#define A_INTERLEAVE 13
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#define A_HILOGAIN 14
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#define A_SETLOOP 15
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#define A_INTERL 17
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#define A_ENVSETUP1 18
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#define A_ENVMIXER 19
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#define A_LOADBUFF 20
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#define A_SAVEBUFF 21
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#define A_ENVSETUP2 22
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#define A_S8DEC 23
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#define A_UNK19 25
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#define A_SPNOOP 0
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#define A_ADPCM 1
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#define A_CLEARBUFF 2
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#define A_UNK3 3
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#define A_ADDMIXER 4
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#define A_RESAMPLE 5
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#define A_RESAMPLE_ZOH 6
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#define A_FILTER 7
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#define A_SETBUFF 8
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#define A_DUPLICATE 9
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#define A_DMEMMOVE 10
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#define A_LOADADPCM 11
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#define A_MIXER 12
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#define A_INTERLEAVE 13
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#define A_HILOGAIN 14
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#define A_SETLOOP 15
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#define A_INTERL 17
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#define A_ENVSETUP1 18
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#define A_ENVMIXER 19
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#define A_LOADBUFF 20
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#define A_SAVEBUFF 21
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#define A_ENVSETUP2 22
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#define A_S8DEC 23
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#define A_UNK19 25
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#define ACMD_SIZE 32
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/*
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* Audio flags
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*/
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#define A_INIT 0x01
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#define A_CONTINUE 0x00
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#define A_LOOP 0x02
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#define A_OUT 0x02
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#define A_LEFT 0x02
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#define A_RIGHT 0x00
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#define A_VOL 0x04
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#define A_RATE 0x00
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#define A_AUX 0x08
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#define A_NOAUX 0x00
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#define A_MAIN 0x00
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#define A_MIX 0x10
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#define A_INIT 0x01
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#define A_CONTINUE 0x00
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#define A_LOOP 0x02
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#define A_OUT 0x02
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#define A_LEFT 0x02
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#define A_RIGHT 0x00
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#define A_VOL 0x04
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#define A_RATE 0x00
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#define A_AUX 0x08
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#define A_NOAUX 0x00
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#define A_MAIN 0x00
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#define A_MIX 0x10
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/*
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* Data Structures.
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*/
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typedef struct
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{
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unsigned int cmd : 8;
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unsigned int flags : 8;
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unsigned int gain : 16;
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unsigned int addr;
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typedef struct {
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u32 cmd : 8;
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u32 flags : 8;
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u32 gain : 16;
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u32 addr;
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} Aadpcm;
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typedef struct
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{
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unsigned int cmd : 8;
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unsigned int flags : 8;
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unsigned int gain : 16;
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unsigned int addr;
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typedef struct {
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u32 cmd : 8;
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u32 flags : 8;
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u32 gain : 16;
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u32 addr;
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} Apolef;
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typedef struct
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{
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unsigned int cmd : 8;
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unsigned int flags : 8;
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unsigned int pad1 : 16;
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unsigned int addr;
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typedef struct {
|
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u32 cmd : 8;
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u32 flags : 8;
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u32 pad1 : 16;
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u32 addr;
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} Aenvelope;
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typedef struct
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{
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unsigned int cmd : 8;
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unsigned int pad1 : 8;
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unsigned int dmem : 16;
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unsigned int pad2 : 16;
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unsigned int count : 16;
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typedef struct {
|
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u32 cmd : 8;
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u32 pad1 : 8;
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u32 dmem : 16;
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u32 pad2 : 16;
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u32 count : 16;
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} Aclearbuff;
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|
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typedef struct
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{
|
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unsigned int cmd : 8;
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unsigned int pad1 : 8;
|
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unsigned int pad2 : 16;
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unsigned int inL : 16;
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||||
unsigned int inR : 16;
|
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typedef struct {
|
||||
u32 cmd : 8;
|
||||
u32 pad1 : 8;
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u32 pad2 : 16;
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||||
u32 inL : 16;
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u32 inR : 16;
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||||
} Ainterleave;
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||||
|
||||
typedef struct
|
||||
{
|
||||
unsigned int cmd : 8;
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||||
unsigned int pad1 : 24;
|
||||
unsigned int addr;
|
||||
typedef struct {
|
||||
u32 cmd : 8;
|
||||
u32 pad1 : 24;
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||||
u32 addr;
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||||
} Aloadbuff;
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||||
|
||||
typedef struct
|
||||
{
|
||||
unsigned int cmd : 8;
|
||||
unsigned int flags : 8;
|
||||
unsigned int pad1 : 16;
|
||||
unsigned int addr;
|
||||
typedef struct {
|
||||
u32 cmd : 8;
|
||||
u32 flags : 8;
|
||||
u32 pad1 : 16;
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||||
u32 addr;
|
||||
} Aenvmixer;
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||||
|
||||
typedef struct
|
||||
{
|
||||
unsigned int cmd : 8;
|
||||
unsigned int flags : 8;
|
||||
unsigned int gain : 16;
|
||||
unsigned int dmemi : 16;
|
||||
unsigned int dmemo : 16;
|
||||
typedef struct {
|
||||
u32 cmd : 8;
|
||||
u32 flags : 8;
|
||||
u32 gain : 16;
|
||||
u32 dmemi : 16;
|
||||
u32 dmemo : 16;
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||||
} Amixer;
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||||
|
||||
typedef struct
|
||||
{
|
||||
unsigned int cmd : 8;
|
||||
unsigned int flags : 8;
|
||||
unsigned int dmem2 : 16;
|
||||
unsigned int addr;
|
||||
typedef struct {
|
||||
u32 cmd : 8;
|
||||
u32 flags : 8;
|
||||
u32 dmem2 : 16;
|
||||
u32 addr;
|
||||
} Apan;
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||||
|
||||
typedef struct
|
||||
{
|
||||
unsigned int cmd : 8;
|
||||
unsigned int flags : 8;
|
||||
unsigned int pitch : 16;
|
||||
unsigned int addr;
|
||||
typedef struct {
|
||||
u32 cmd : 8;
|
||||
u32 flags : 8;
|
||||
u32 pitch : 16;
|
||||
u32 addr;
|
||||
} Aresample;
|
||||
|
||||
typedef struct
|
||||
{
|
||||
unsigned int cmd : 8;
|
||||
unsigned int flags : 8;
|
||||
unsigned int pad1 : 16;
|
||||
unsigned int addr;
|
||||
typedef struct {
|
||||
u32 cmd : 8;
|
||||
u32 flags : 8;
|
||||
u32 pad1 : 16;
|
||||
u32 addr;
|
||||
} Areverb;
|
||||
|
||||
typedef struct
|
||||
{
|
||||
unsigned int cmd : 8;
|
||||
unsigned int pad1 : 24;
|
||||
unsigned int addr;
|
||||
typedef struct {
|
||||
u32 cmd : 8;
|
||||
u32 pad1 : 24;
|
||||
u32 addr;
|
||||
} Asavebuff;
|
||||
|
||||
typedef struct
|
||||
{
|
||||
unsigned int cmd : 8;
|
||||
unsigned int pad1 : 24;
|
||||
unsigned int pad2 : 2;
|
||||
unsigned int number : 4;
|
||||
unsigned int base : 24;
|
||||
typedef struct {
|
||||
u32 cmd : 8;
|
||||
u32 pad1 : 24;
|
||||
u32 pad2 : 2;
|
||||
u32 number : 4;
|
||||
u32 base : 24;
|
||||
} Asegment;
|
||||
|
||||
typedef struct
|
||||
{
|
||||
unsigned int cmd : 8;
|
||||
unsigned int flags : 8;
|
||||
unsigned int dmemin : 16;
|
||||
unsigned int dmemout : 16;
|
||||
unsigned int count : 16;
|
||||
typedef struct {
|
||||
u32 cmd : 8;
|
||||
u32 flags : 8;
|
||||
u32 dmemin : 16;
|
||||
u32 dmemout : 16;
|
||||
u32 count : 16;
|
||||
} Asetbuff;
|
||||
|
||||
typedef struct
|
||||
{
|
||||
unsigned int cmd : 8;
|
||||
unsigned int flags : 8;
|
||||
unsigned int vol : 16;
|
||||
unsigned int voltgt : 16;
|
||||
unsigned int volrate : 16;
|
||||
typedef struct {
|
||||
u32 cmd : 8;
|
||||
u32 flags : 8;
|
||||
u32 vol : 16;
|
||||
u32 voltgt : 16;
|
||||
u32 volrate : 16;
|
||||
} Asetvol;
|
||||
|
||||
typedef struct
|
||||
{
|
||||
unsigned int cmd : 8;
|
||||
unsigned int pad1 : 8;
|
||||
unsigned int dmemin : 16;
|
||||
unsigned int dmemout : 16;
|
||||
unsigned int count : 16;
|
||||
typedef struct {
|
||||
u32 cmd : 8;
|
||||
u32 pad1 : 8;
|
||||
u32 dmemin : 16;
|
||||
u32 dmemout : 16;
|
||||
u32 count : 16;
|
||||
} Admemmove;
|
||||
|
||||
typedef struct
|
||||
{
|
||||
unsigned int cmd : 8;
|
||||
unsigned int pad1 : 8;
|
||||
unsigned int count : 16;
|
||||
unsigned int addr;
|
||||
typedef struct {
|
||||
u32 cmd : 8;
|
||||
u32 pad1 : 8;
|
||||
u32 count : 16;
|
||||
u32 addr;
|
||||
} Aloadadpcm;
|
||||
|
||||
typedef struct
|
||||
{
|
||||
unsigned int cmd : 8;
|
||||
unsigned int pad1 : 8;
|
||||
unsigned int pad2 : 16;
|
||||
unsigned int addr;
|
||||
typedef struct {
|
||||
u32 cmd : 8;
|
||||
u32 pad1 : 8;
|
||||
u32 pad2 : 16;
|
||||
u32 addr;
|
||||
} Asetloop;
|
||||
|
||||
/*
|
||||
* Generic Acmd Packet
|
||||
*/
|
||||
|
||||
typedef struct
|
||||
{
|
||||
unsigned int w0;
|
||||
unsigned int w1;
|
||||
typedef struct {
|
||||
u32 w0;
|
||||
u32 w1;
|
||||
} Awords;
|
||||
|
||||
typedef union {
|
||||
Awords words;
|
||||
Aadpcm adpcm;
|
||||
Apolef polef;
|
||||
Aclearbuff clearbuff;
|
||||
Aenvelope envelope;
|
||||
Awords words;
|
||||
Aadpcm adpcm;
|
||||
Apolef polef;
|
||||
Aclearbuff clearbuff;
|
||||
Aenvelope envelope;
|
||||
Ainterleave interleave;
|
||||
Aloadbuff loadbuff;
|
||||
Aenvmixer envmixer;
|
||||
Aresample resample;
|
||||
Areverb reverb;
|
||||
Asavebuff savebuff;
|
||||
Asegment segment;
|
||||
Asetbuff setbuff;
|
||||
Asetvol setvol;
|
||||
Admemmove dmemmove;
|
||||
Aloadadpcm loadadpcm;
|
||||
Amixer mixer;
|
||||
Asetloop setloop;
|
||||
Aloadbuff loadbuff;
|
||||
Aenvmixer envmixer;
|
||||
Aresample resample;
|
||||
Areverb reverb;
|
||||
Asavebuff savebuff;
|
||||
Asegment segment;
|
||||
Asetbuff setbuff;
|
||||
Asetvol setvol;
|
||||
Admemmove dmemmove;
|
||||
Aloadadpcm loadadpcm;
|
||||
Amixer mixer;
|
||||
Asetloop setloop;
|
||||
long long int force_union_align; /* dummy, force alignment */
|
||||
} Acmd;
|
||||
|
||||
@ -280,55 +243,55 @@ typedef short ENVMIX_STATE[40];
|
||||
* Macros to assemble the audio command list
|
||||
*/
|
||||
|
||||
#define aADPCMdec(pkt, f, s) \
|
||||
{ \
|
||||
Acmd *_a = (Acmd *)pkt; \
|
||||
\
|
||||
_a->words.w0 = _SHIFTL(A_ADPCM, 24, 8) | _SHIFTL(f, 16, 8); \
|
||||
_a->words.w1 = (unsigned int)(s); \
|
||||
#define aADPCMdec(pkt, f, s) \
|
||||
{ \
|
||||
Acmd *_a = (Acmd *)pkt; \
|
||||
\
|
||||
_a->words.w0 = _SHIFTL(A_ADPCM, 24, 8) | _SHIFTL(f, 16, 8); \
|
||||
_a->words.w1 = (u32)(s); \
|
||||
}
|
||||
|
||||
#define aPoleFilter(pkt, f, g, s) \
|
||||
{ \
|
||||
Acmd *_a = (Acmd *)pkt; \
|
||||
\
|
||||
_a->words.w0 = (_SHIFTL(A_POLEF, 24, 8) | _SHIFTL(f, 16, 8) | \
|
||||
_SHIFTL(g, 0, 16)); \
|
||||
_a->words.w1 = (unsigned int)(s); \
|
||||
#define aPoleFilter(pkt, f, g, s) \
|
||||
{ \
|
||||
Acmd *_a = (Acmd *)pkt; \
|
||||
\
|
||||
_a->words.w0 = (_SHIFTL(A_POLEF, 24, 8) | _SHIFTL(f, 16, 8) | \
|
||||
_SHIFTL(g, 0, 16)); \
|
||||
_a->words.w1 = (u32)(s); \
|
||||
}
|
||||
|
||||
#define aHiLoGain(pkt, gain, count, dmem, a4) \
|
||||
{ \
|
||||
Acmd *_a = (Acmd *)pkt; \
|
||||
\
|
||||
_a->words.w0 = (_SHIFTL(A_HILOGAIN, 24, 8) | \
|
||||
_SHIFTL(gain, 16, 8) | _SHIFTL(count, 0, 16)); \
|
||||
_a->words.w1 = _SHIFTL(dmem, 16, 16) | _SHIFTL(a4, 0, 16); \
|
||||
#define aHiLoGain(pkt, gain, count, dmem, a4) \
|
||||
{ \
|
||||
Acmd *_a = (Acmd *)pkt; \
|
||||
\
|
||||
_a->words.w0 = (_SHIFTL(A_HILOGAIN, 24, 8) | \
|
||||
_SHIFTL(gain, 16, 8) | _SHIFTL(count, 0, 16)); \
|
||||
_a->words.w1 = _SHIFTL(dmem, 16, 16) | _SHIFTL(a4, 0, 16); \
|
||||
}
|
||||
|
||||
#define aUnkCmd3(pkt, a1, a2, a3) \
|
||||
{ \
|
||||
Acmd *_a = (Acmd *)pkt; \
|
||||
\
|
||||
_a->words.w0 = _SHIFTL(A_UNK3, 24, 8) | _SHIFTL(a3, 0, 16); \
|
||||
_a->words.w1 = _SHIFTL(a1, 16, 16) | _SHIFTL(a2, 0, 16); \
|
||||
#define aUnkCmd3(pkt, a1, a2, a3) \
|
||||
{ \
|
||||
Acmd *_a = (Acmd *)pkt; \
|
||||
\
|
||||
_a->words.w0 = _SHIFTL(A_UNK3, 24, 8) | _SHIFTL(a3, 0, 16); \
|
||||
_a->words.w1 = _SHIFTL(a1, 16, 16) | _SHIFTL(a2, 0, 16); \
|
||||
}
|
||||
|
||||
#define aUnkCmd19(pkt, a1, a2, a3, a4) \
|
||||
{ \
|
||||
Acmd *_a = (Acmd *)pkt; \
|
||||
\
|
||||
_a->words.w0 = (_SHIFTL(A_UNK19, 24, 8) | _SHIFTL(a1, 16, 8) | \
|
||||
_SHIFTL(a2, 0, 16)); \
|
||||
_a->words.w1 = _SHIFTL(a3, 16, 16) | _SHIFTL(a4, 0, 16); \
|
||||
#define aUnkCmd19(pkt, a1, a2, a3, a4) \
|
||||
{ \
|
||||
Acmd *_a = (Acmd *)pkt; \
|
||||
\
|
||||
_a->words.w0 = (_SHIFTL(A_UNK19, 24, 8) | _SHIFTL(a1, 16, 8) | \
|
||||
_SHIFTL(a2, 0, 16)); \
|
||||
_a->words.w1 = _SHIFTL(a3, 16, 16) | _SHIFTL(a4, 0, 16); \
|
||||
}
|
||||
|
||||
#define aS8Dec(pkt, a1, a2) \
|
||||
{ \
|
||||
Acmd *_a = (Acmd *)pkt; \
|
||||
\
|
||||
_a->words.w0 = _SHIFTL(A_S8DEC, 24, 8) | _SHIFTL(a1, 16, 8); \
|
||||
_a->words.w1 = (unsigned int)(a2); \
|
||||
#define aS8Dec(pkt, a1, a2) \
|
||||
{ \
|
||||
Acmd *_a = (Acmd *)pkt; \
|
||||
\
|
||||
_a->words.w0 = _SHIFTL(A_S8DEC, 24, 8) | _SHIFTL(a1, 16, 8); \
|
||||
_a->words.w1 = (u32)(a2); \
|
||||
}
|
||||
|
||||
#define aClearBuffer(pkt, d, c) \
|
||||
@ -336,89 +299,88 @@ typedef short ENVMIX_STATE[40];
|
||||
Acmd *_a = (Acmd *)pkt; \
|
||||
\
|
||||
_a->words.w0 = _SHIFTL(A_CLEARBUFF, 24, 8) | _SHIFTL(d, 0, 24); \
|
||||
_a->words.w1 = (unsigned int)(c); \
|
||||
_a->words.w1 = (u32)(c); \
|
||||
}
|
||||
|
||||
#define aEnvMixer(pkt, dmemi, count, swapLR, x0, x1, x2, x3, m, bits) \
|
||||
{ \
|
||||
Acmd *_a = (Acmd *)pkt; \
|
||||
\
|
||||
_a->words.w0 = (bits | _SHIFTL(dmemi >> 4, 16, 8) | \
|
||||
_SHIFTL(count, 8, 8) | _SHIFTL(swapLR, 4, 1) | \
|
||||
_SHIFTL(x0, 3, 1) | _SHIFTL(x1, 2, 1) | \
|
||||
_SHIFTL(x2, 1, 1) | _SHIFTL(x3, 0, 1)); \
|
||||
_a->words.w1 = (unsigned int)(m); \
|
||||
#define aEnvMixer(pkt, dmemi, count, swapLR, x0, x1, x2, x3, m, bits) \
|
||||
{ \
|
||||
Acmd *_a = (Acmd *)pkt; \
|
||||
\
|
||||
_a->words.w0 = (bits | _SHIFTL(dmemi >> 4, 16, 8) | \
|
||||
_SHIFTL(count, 8, 8) | _SHIFTL(swapLR, 4, 1) | \
|
||||
_SHIFTL(x0, 3, 1) | _SHIFTL(x1, 2, 1) | \
|
||||
_SHIFTL(x2, 1, 1) | _SHIFTL(x3, 0, 1)); \
|
||||
_a->words.w1 = (u32)(m); \
|
||||
}
|
||||
|
||||
#define aInterleave(pkt, o, l, r, c) \
|
||||
{ \
|
||||
Acmd *_a = (Acmd *)pkt; \
|
||||
\
|
||||
_a->words.w0 = (_SHIFTL(A_INTERLEAVE, 24, 8) | \
|
||||
_SHIFTL(c >> 4, 16, 8) | _SHIFTL(o, 0, 16)); \
|
||||
_a->words.w1 = _SHIFTL(l, 16, 16) | _SHIFTL(r, 0, 16); \
|
||||
#define aInterleave(pkt, o, l, r, c) \
|
||||
{ \
|
||||
Acmd *_a = (Acmd *)pkt; \
|
||||
\
|
||||
_a->words.w0 = (_SHIFTL(A_INTERLEAVE, 24, 8) | \
|
||||
_SHIFTL(c >> 4, 16, 8) | _SHIFTL(o, 0, 16)); \
|
||||
_a->words.w1 = _SHIFTL(l, 16, 16) | _SHIFTL(r, 0, 16); \
|
||||
}
|
||||
|
||||
#define aInterl(pkt, dmemi, dmemo, count) \
|
||||
{ \
|
||||
Acmd *_a = (Acmd*)pkt; \
|
||||
\
|
||||
_a->words.w0 = (_SHIFTL(A_INTERL, 24, 8) | \
|
||||
_SHIFTL(count, 0, 16)); \
|
||||
_a->words.w1 = _SHIFTL(dmemi, 16, 16) | _SHIFTL(dmemo, 0, 16); \
|
||||
#define aInterl(pkt, dmemi, dmemo, count) \
|
||||
{ \
|
||||
Acmd *_a = (Acmd*)pkt; \
|
||||
\
|
||||
_a->words.w0 = (_SHIFTL(A_INTERL, 24, 8) | _SHIFTL(count, 0, 16)); \
|
||||
_a->words.w1 = _SHIFTL(dmemi, 16, 16) | _SHIFTL(dmemo, 0, 16); \
|
||||
}
|
||||
|
||||
#define aLoadBuffer(pkt, s, d, c) \
|
||||
{ \
|
||||
Acmd *_a = (Acmd *)pkt; \
|
||||
\
|
||||
_a->words.w0 = _SHIFTL(A_LOADBUFF, 24, 8) | \
|
||||
_SHIFTL((c) >> 4, 16, 8) | _SHIFTL(d, 0, 16); \
|
||||
_a->words.w1 = (unsigned int)(s); \
|
||||
#define aLoadBuffer(pkt, s, d, c) \
|
||||
{ \
|
||||
Acmd *_a = (Acmd *)pkt; \
|
||||
\
|
||||
_a->words.w0 = (_SHIFTL(A_LOADBUFF, 24, 8) | \
|
||||
_SHIFTL((c) >> 4, 16, 8) | _SHIFTL(d, 0, 16)); \
|
||||
_a->words.w1 = (u32)(s); \
|
||||
}
|
||||
|
||||
#define aMix(pkt, f, g, i, o) \
|
||||
{ \
|
||||
Acmd *_a = (Acmd *)pkt; \
|
||||
\
|
||||
_a->words.w0 = (_SHIFTL(A_MIXER, 24, 8) | _SHIFTL(f, 16, 8) | \
|
||||
_SHIFTL(g, 0, 16)); \
|
||||
_a->words.w1 = _SHIFTL(i, 16, 16) | _SHIFTL(o, 0, 16); \
|
||||
#define aMix(pkt, f, g, i, o) \
|
||||
{ \
|
||||
Acmd *_a = (Acmd *)pkt; \
|
||||
\
|
||||
_a->words.w0 = (_SHIFTL(A_MIXER, 24, 8) | _SHIFTL(f, 16, 8) | \
|
||||
_SHIFTL(g, 0, 16)); \
|
||||
_a->words.w1 = _SHIFTL(i, 16, 16) | _SHIFTL(o, 0, 16); \
|
||||
}
|
||||
|
||||
#define aPan(pkt, f, d, s) \
|
||||
{ \
|
||||
Acmd *_a = (Acmd *)pkt; \
|
||||
\
|
||||
_a->words.w0 = (_SHIFTL(A_PAN, 24, 8) | _SHIFTL(f, 16, 8) | \
|
||||
_SHIFTL(d, 0, 16)); \
|
||||
_a->words.w1 = (unsigned int)(s); \
|
||||
#define aPan(pkt, f, d, s) \
|
||||
{ \
|
||||
Acmd *_a = (Acmd *)pkt; \
|
||||
\
|
||||
_a->words.w0 = (_SHIFTL(A_PAN, 24, 8) | _SHIFTL(f, 16, 8) | \
|
||||
_SHIFTL(d, 0, 16)); \
|
||||
_a->words.w1 = (u32)(s); \
|
||||
}
|
||||
|
||||
#define aResample(pkt, f, p, s) \
|
||||
{ \
|
||||
Acmd *_a = (Acmd *)pkt; \
|
||||
\
|
||||
_a->words.w0 = (_SHIFTL(A_RESAMPLE, 24, 8) | \
|
||||
_SHIFTL(f, 16, 8) | _SHIFTL(p, 0, 16)); \
|
||||
_a->words.w1 = (unsigned int)(s); \
|
||||
#define aResample(pkt, f, p, s) \
|
||||
{ \
|
||||
Acmd *_a = (Acmd *)pkt; \
|
||||
\
|
||||
_a->words.w0 = (_SHIFTL(A_RESAMPLE, 24, 8) | \
|
||||
_SHIFTL(f, 16, 8) | _SHIFTL(p, 0, 16)); \
|
||||
_a->words.w1 = (u32)(s); \
|
||||
}
|
||||
|
||||
#define aSaveBuffer(pkt, s, d, c) \
|
||||
{ \
|
||||
Acmd *_a = (Acmd *)pkt; \
|
||||
\
|
||||
_a->words.w0 = _SHIFTL(A_SAVEBUFF, 24, 8) | \
|
||||
_SHIFTL((c) >> 4, 16, 8) | _SHIFTL(s, 0, 16); \
|
||||
_a->words.w1 = (unsigned int)(d); \
|
||||
#define aSaveBuffer(pkt, s, d, c) \
|
||||
{ \
|
||||
Acmd *_a = (Acmd *)pkt; \
|
||||
\
|
||||
_a->words.w0 = (_SHIFTL(A_SAVEBUFF, 24, 8) | \
|
||||
_SHIFTL((c) >> 4, 16, 8) | _SHIFTL(s, 0, 16)); \
|
||||
_a->words.w1 = (u32)(d); \
|
||||
}
|
||||
|
||||
#define aSegment(pkt, s, b) \
|
||||
{ \
|
||||
Acmd *_a = (Acmd *)pkt; \
|
||||
\
|
||||
_a->words.w0 = _SHIFTL(A_SEGMENT, 24, 8); \
|
||||
_a->words.w1 = _SHIFTL(s, 24, 8) | _SHIFTL(b, 0, 24); \
|
||||
#define aSegment(pkt, s, b) \
|
||||
{ \
|
||||
Acmd *_a = (Acmd *)pkt; \
|
||||
\
|
||||
_a->words.w0 = _SHIFTL(A_SEGMENT, 24, 8); \
|
||||
_a->words.w1 = _SHIFTL(s, 24, 8) | _SHIFTL(b, 0, 24); \
|
||||
}
|
||||
|
||||
#define aSetBuffer(pkt, f, i, o, c) \
|
||||
@ -445,23 +407,23 @@ typedef short ENVMIX_STATE[40];
|
||||
\
|
||||
_a->words.w0 = (_SHIFTL(A_SETVOL, 24, 8) | _SHIFTL(f, 16, 16) | \
|
||||
_SHIFTL(v, 0, 16)); \
|
||||
_a->words.w1 = (unsigned int)(tr); \
|
||||
_a->words.w1 = (u32)(tr); \
|
||||
}
|
||||
|
||||
#define aSetLoop(pkt, a) \
|
||||
{ \
|
||||
Acmd *_a = (Acmd *)pkt; \
|
||||
\
|
||||
_a->words.w0 = _SHIFTL(A_SETLOOP, 24, 8); \
|
||||
_a->words.w1 = (unsigned int)(a); \
|
||||
#define aSetLoop(pkt, a) \
|
||||
{ \
|
||||
Acmd *_a = (Acmd *)pkt; \
|
||||
\
|
||||
_a->words.w0 = _SHIFTL(A_SETLOOP, 24, 8); \
|
||||
_a->words.w1 = (u32)(a); \
|
||||
}
|
||||
|
||||
#define aDMEMMove(pkt, i, o, c) \
|
||||
{ \
|
||||
Acmd *_a = (Acmd *)pkt; \
|
||||
\
|
||||
_a->words.w0 = _SHIFTL(A_DMEMMOVE, 24, 8) | _SHIFTL(i, 0, 24); \
|
||||
_a->words.w1 = _SHIFTL(o, 16, 16) | _SHIFTL(c, 0, 16); \
|
||||
#define aDMEMMove(pkt, i, o, c) \
|
||||
{ \
|
||||
Acmd *_a = (Acmd *)pkt; \
|
||||
\
|
||||
_a->words.w0 = _SHIFTL(A_DMEMMOVE, 24, 8) | _SHIFTL(i, 0, 24); \
|
||||
_a->words.w1 = _SHIFTL(o, 16, 16) | _SHIFTL(c, 0, 16); \
|
||||
}
|
||||
|
||||
#define aLoadADPCM(pkt, c, d) \
|
||||
@ -469,36 +431,34 @@ typedef short ENVMIX_STATE[40];
|
||||
Acmd *_a = (Acmd *)pkt; \
|
||||
\
|
||||
_a->words.w0 = _SHIFTL(A_LOADADPCM, 24, 8) | _SHIFTL(c, 0, 24); \
|
||||
_a->words.w1 = (unsigned int)d; \
|
||||
_a->words.w1 = (u32)d; \
|
||||
}
|
||||
|
||||
|
||||
|
||||
#define aEnvSetup1(pkt, a, b, c, d) \
|
||||
{ \
|
||||
Acmd *_a = (Acmd *)pkt; \
|
||||
\
|
||||
_a->words.w0 = (_SHIFTL(A_ENVSETUP1, 24, 8) | \
|
||||
_SHIFTL(a, 16, 8) | _SHIFTL(b, 0, 16)); \
|
||||
_a->words.w1 = _SHIFTL(c, 16, 16) | _SHIFTL(d, 0, 16); \
|
||||
#define aEnvSetup1(pkt, a, b, c, d) \
|
||||
{ \
|
||||
Acmd *_a = (Acmd *)pkt; \
|
||||
\
|
||||
_a->words.w0 = (_SHIFTL(A_ENVSETUP1, 24, 8) | \
|
||||
_SHIFTL(a, 16, 8) | _SHIFTL(b, 0, 16)); \
|
||||
_a->words.w1 = _SHIFTL(c, 16, 16) | _SHIFTL(d, 0, 16); \
|
||||
}
|
||||
|
||||
#define aEnvSetup2(pkt, volLeft, volRight) \
|
||||
{ \
|
||||
Acmd *_a = (Acmd *)pkt; \
|
||||
\
|
||||
_a->words.w0 = _SHIFTL(A_ENVSETUP2, 24, 8); \
|
||||
_a->words.w1 = _SHIFTL(volLeft, 16, 16) | \
|
||||
_SHIFTL(volRight, 0, 16); \
|
||||
#define aEnvSetup2(pkt, volLeft, volRight) \
|
||||
{ \
|
||||
Acmd *_a = (Acmd *)pkt; \
|
||||
\
|
||||
_a->words.w0 = _SHIFTL(A_ENVSETUP2, 24, 8); \
|
||||
_a->words.w1 = (_SHIFTL(volLeft, 16, 16) | \
|
||||
_SHIFTL(volRight, 0, 16)); \
|
||||
}
|
||||
|
||||
#define aFilter(pkt, f, countOrBuf, addr) \
|
||||
{ \
|
||||
Acmd *_a = (Acmd *)pkt; \
|
||||
\
|
||||
_a->words.w0 = _SHIFTL(A_FILTER, 24, 8) | _SHIFTL(f, 16, 8) | \
|
||||
_SHIFTL(countOrBuf, 0, 16); \
|
||||
_a->words.w1 = (unsigned int)(addr); \
|
||||
_a->words.w0 = (_SHIFTL(A_FILTER, 24, 8) | _SHIFTL(f, 16, 8) | \
|
||||
_SHIFTL(countOrBuf, 0, 16)); \
|
||||
_a->words.w1 = (u32)(addr); \
|
||||
}
|
||||
|
||||
#define aDuplicate(pkt, count, dmemi, dmemo, a4) \
|
||||
@ -506,26 +466,26 @@ typedef short ENVMIX_STATE[40];
|
||||
Acmd *_a = (Acmd *)pkt; \
|
||||
\
|
||||
_a->words.w0 = (_SHIFTL(A_DUPLICATE, 24, 8) | \
|
||||
_SHIFTL(count, 16, 8) | _SHIFTL(dmemi, 0, 16)); \
|
||||
_SHIFTL(count, 16, 8) | _SHIFTL(dmemi, 0, 16)); \
|
||||
_a->words.w1 = _SHIFTL(dmemo, 16, 16) | _SHIFTL(a4, 0, 16); \
|
||||
}
|
||||
|
||||
#define aAddMixer(pkt, count, dmemi, dmemo, a4) \
|
||||
{ \
|
||||
Acmd *_a = (Acmd *)pkt; \
|
||||
\
|
||||
_a->words.w0 = (_SHIFTL(A_ADDMIXER, 24, 8) | \
|
||||
_SHIFTL(count >> 4, 16, 8) | _SHIFTL(a4, 0, 16)); \
|
||||
_a->words.w1 = _SHIFTL(dmemi, 16, 16) | _SHIFTL(dmemo, 0, 16); \
|
||||
#define aAddMixer(pkt, count, dmemi, dmemo, a4) \
|
||||
{ \
|
||||
Acmd *_a = (Acmd *)pkt; \
|
||||
\
|
||||
_a->words.w0 = (_SHIFTL(A_ADDMIXER, 24, 8) | \
|
||||
_SHIFTL(count >> 4, 16, 8) | _SHIFTL(a4, 0, 16)); \
|
||||
_a->words.w1 = _SHIFTL(dmemi, 16, 16) | _SHIFTL(dmemo, 0, 16); \
|
||||
}
|
||||
|
||||
#define aResampleZoh(pkt, pitch, pitchAccu) \
|
||||
{ \
|
||||
Acmd *_a = (Acmd *)pkt; \
|
||||
\
|
||||
_a->words.w0 = (_SHIFTL(A_RESAMPLE_ZOH, 24, 8) | \
|
||||
_SHIFTL(pitch, 0, 16)); \
|
||||
_a->words.w1 = _SHIFTL(pitchAccu, 0, 16); \
|
||||
#define aResampleZoh(pkt, pitch, pitchAccu) \
|
||||
{ \
|
||||
Acmd *_a = (Acmd *)pkt; \
|
||||
\
|
||||
_a->words.w0 = (_SHIFTL(A_RESAMPLE_ZOH, 24, 8) | \
|
||||
_SHIFTL(pitch, 0, 16)); \
|
||||
_a->words.w1 = _SHIFTL(pitchAccu, 0, 16); \
|
||||
}
|
||||
|
||||
#endif /* ULTRA64_ABI_H */
|
||||
|
||||
@ -1,8 +1,7 @@
|
||||
#ifndef ULTRA64_CONTROLLER_H
|
||||
#define ULTRA64_CONTROLLER_H
|
||||
|
||||
#include "ultra64.h"
|
||||
#include "ultra64/message.h"
|
||||
#include "message.h"
|
||||
|
||||
#define SIAccessQueueSize 2
|
||||
#define BLOCKSIZE 32
|
||||
|
||||
45
include/ultra64/exception.h
Normal file
45
include/ultra64/exception.h
Normal file
@ -0,0 +1,45 @@
|
||||
#ifndef ULTRA64_EXCEPTION_H
|
||||
#define ULTRA64_EXCEPTION_H
|
||||
|
||||
#include "types.h"
|
||||
|
||||
// Interrupt masks
|
||||
#define OS_IM_NONE 0x00000001
|
||||
#define OS_IM_SW1 0x00000501
|
||||
#define OS_IM_SW2 0x00000601
|
||||
#define OS_IM_CART 0x00000C01
|
||||
#define OS_IM_PRENMI 0x00001401
|
||||
#define OS_IM_RDBWRITE 0x00002401
|
||||
#define OS_IM_RDBREAD 0x00004401
|
||||
#define OS_IM_COUNTER 0x00008401
|
||||
#define OS_IM_CPU 0x0000FF01
|
||||
#define OS_IM_SP 0x00010401
|
||||
#define OS_IM_SI 0x00020401
|
||||
#define OS_IM_AI 0x00040401
|
||||
#define OS_IM_VI 0x00080401
|
||||
#define OS_IM_PI 0x00100401
|
||||
#define OS_IM_DP 0x00200401
|
||||
#define OS_IM_ALL 0x003FFF01
|
||||
|
||||
#define RCP_IMASK 0x003F0000
|
||||
#define RCP_IMASKSHIFT 16
|
||||
|
||||
typedef u32 OSIntMask;
|
||||
typedef u32 OSHWIntr;
|
||||
|
||||
typedef struct {
|
||||
/* 0x00 */ void* callback;
|
||||
/* 0x04 */ void* sp;
|
||||
} __osHwInt; // size = 0x08
|
||||
|
||||
OSIntMask osSetIntMask(OSIntMask);
|
||||
|
||||
void __osSetHWIntrRoutine(OSHWIntr interrupt, s32 (*callback)(void), void *sp);
|
||||
void __osGetHWIntrRoutine(OSHWIntr interrupt, s32 (**callbackOut)(void), void **spOut);
|
||||
|
||||
void __osSetGlobalIntMask(OSHWIntr mask);
|
||||
void __osResetGlobalIntMask(OSHWIntr mask);
|
||||
|
||||
extern __osHwInt __osHwIntTable[];
|
||||
|
||||
#endif
|
||||
@ -1,4 +1,4 @@
|
||||
#include "ultra64/mbi.h"
|
||||
#include "mbi.h"
|
||||
|
||||
#ifndef ULTRA64_GBI_H
|
||||
#define ULTRA64_GBI_H
|
||||
|
||||
@ -1,90 +0,0 @@
|
||||
#ifndef ULTRA64_HARDWARE_H
|
||||
#define ULTRA64_HARDWARE_H
|
||||
|
||||
#define HW_REG(reg, type) *(volatile type*)((reg) | 0xa0000000)
|
||||
|
||||
#define AI_DRAM_ADDR_REG 0x04500000
|
||||
#define AI_LEN_REG 0x04500004
|
||||
#define AI_CONTROL_REG 0x04500008
|
||||
#define AI_STATUS_REG 0x0450000C
|
||||
#define AI_STATUS_AI_FULL (1 << 31)
|
||||
#define AI_STATUS_AI_BUSY (1 << 30)
|
||||
#define AI_DACRATE_REG 0x04500010
|
||||
#define AI_BITRATE_REG 0x04500014
|
||||
|
||||
#define VI_STATUS_REG 0x04400000
|
||||
#define VI_CONTROL_REG 0x04400000
|
||||
#define VI_ORIGIN_REG 0x04400004
|
||||
#define VI_DRAM_ADDR_REG 0x04400004
|
||||
#define VI_WIDTH_REG 0x04400008
|
||||
#define VI_H_WIDTH_REG 0x04400008
|
||||
#define VI_INTR_REG 0x0440000C
|
||||
#define VI_V_INTER_REG 0x0440000C
|
||||
#define VI_CURRENT_REG 0x04400010
|
||||
#define VI_V_CURRENT_LINE_REG 0x04400010
|
||||
#define VI_BURST_REG 0x04400014
|
||||
#define VI_TIMING_REG 0x04400014
|
||||
#define VI_V_SYNC_REG 0x04400018 //VI vertical sync
|
||||
#define VI_H_SYNC_REG 0x0440001C //VI horizontal sync
|
||||
#define VI_LEAP_REG 0x04400020 //VI horizontal sync leap
|
||||
#define VI_H_SYNC_LEAP_REG 0x04400020
|
||||
#define VI_H_START_REG 0x04400024 //VI horizontal video
|
||||
#define VI_H_VIDEO_REG 0x04400024
|
||||
#define VI_V_START_REG 0x04400028 //VI vertical video
|
||||
#define VI_V_VIDEO_REG 0x04400028
|
||||
#define VI_V_BURST_REG 0x0440002C //VI vertical burst
|
||||
#define VI_X_SCALE_REG 0x04400030 //VI x-scale
|
||||
#define VI_Y_SCALE_REG 0x04400034 //VI y-scale
|
||||
|
||||
#define SP_IMEM_START 0x04001000
|
||||
#define SP_DMEM_START 0x04000000
|
||||
|
||||
#define SP_MEM_ADDR_REG 0x04040000
|
||||
#define SP_DRAM_ADDR_REG 0x04040004
|
||||
#define SP_RD_LEN_REG 0x04040008
|
||||
#define SP_WR_LEN_REG 0x0404000C
|
||||
#define SP_STATUS_REG 0x04040010
|
||||
#define SP_PC_REG 0x04080000
|
||||
|
||||
#define PI_DRAM_ADDR_REG 0x04600000 //PI DRAM address
|
||||
#define PI_CART_ADDR_REG 0x04600004 //PI pbus (cartridge) address
|
||||
#define PI_RD_LEN_REG 0x04600008 //PI read length
|
||||
#define PI_WR_LEN_REG 0x0460000C //PI write length
|
||||
#define PI_STATUS_REG 0x04600010 //PI status
|
||||
#define PI_BSD_DOM1_LAT_REG 0x04600014 //PI dom1 latency
|
||||
#define PI_DOMAIN1_REG 0x04600014
|
||||
#define PI_BSD_DOM1_PWD_REG 0x04600018 //PI dom1 pulse width
|
||||
#define PI_BSD_DOM1_PGS_REG 0x0460001C //PI dom1 page size
|
||||
#define PI_BSD_DOM1_RLS_REG 0x04600020 //PI dom1 release
|
||||
#define PI_BSD_DOM2_LAT_REG 0x04600024 //PI dom2 latency
|
||||
#define PI_DOMAIN2_REG 0x04600024
|
||||
#define PI_BSD_DOM2_PWD_REG 0x04600028 //PI dom2 pulse width
|
||||
#define PI_BSD_DOM2_PGS_REG 0x0460002C //PI dom2 page size
|
||||
#define PI_BSD_DOM2_RLS_REG 0x04600030 //PI dom2 release
|
||||
|
||||
#define PI_STATUS_BUSY 0x1
|
||||
#define PI_STATUS_IOBUSY 0x2
|
||||
#define PI_STATUS_ERROR 0x4
|
||||
|
||||
#define PI_STATUS_RESET_CONTROLLER 0x1
|
||||
#define PI_STATUS_CLEAR_INTR 0x2
|
||||
|
||||
#define SI_DRAM_ADDR_REG 0x04800000
|
||||
#define SI_PIF_ADDR_RD64B_REG 0x04800004
|
||||
#define SI_PIF_ADDR_WR64B_REG 0x04800010
|
||||
#define SI_STATUS_REG 0x04800018
|
||||
|
||||
#define SI_STATUS_DMA_BUSY 0x1
|
||||
#define SI_STATUS_IO_READ_BUSY 0x2
|
||||
#define SI_STATUS_DMA_ERROR 0x8
|
||||
#define SI_STATUS_INTERRUPT (1 << 12)
|
||||
|
||||
#define PIF_RAM_START 0x1FC007C0
|
||||
|
||||
#define MI_INIT_MODE_REG 0x04300000
|
||||
#define MI_MODE_REG MI_INIT_MODE_REG
|
||||
#define MI_VERSION_REG 0x04300004
|
||||
#define MI_INTR_REG 0x04300008
|
||||
#define MI_INTR_MASK_REG 0x0430000C
|
||||
|
||||
#endif
|
||||
@ -1,6 +1,8 @@
|
||||
#ifndef ULTRA64_INTERNAL_H
|
||||
#define ULTRA64_INTERNAL_H
|
||||
|
||||
#include "pi.h"
|
||||
|
||||
typedef struct {
|
||||
/* 0x00 */ u32 initialized;
|
||||
/* 0x04 */ OSThread* mgrThread;
|
||||
@ -11,18 +13,12 @@ typedef struct {
|
||||
/* 0x18 */ s32 (*epiDmaCallback)(OSPiHandle*, s32, u32, void*, size_t);
|
||||
} OSMgrArgs; // size = 0x1C
|
||||
|
||||
typedef struct {
|
||||
/* 0x00 */ s32 (*handler)(void);
|
||||
/* 0x04 */ void* sp;
|
||||
} __osHwInt; // size = 0x08
|
||||
|
||||
typedef struct {
|
||||
/* 0x00 */ OSMesgQueue* queue;
|
||||
/* 0x04 */ OSMesg msg;
|
||||
} __OSEventState; // size = 0x08
|
||||
|
||||
extern OSMgrArgs __osPiDevMgr;
|
||||
extern __osHwInt __osHwIntTable[];
|
||||
extern __OSEventState __osEventStateTab[];
|
||||
|
||||
#endif
|
||||
|
||||
@ -1,7 +0,0 @@
|
||||
#ifndef ULTRA64_INTERRUPT_H
|
||||
#define ULTRA64_INTERRUPT_H
|
||||
|
||||
typedef u32 OSIntMask;
|
||||
typedef u32 OSHWIntr;
|
||||
|
||||
#endif
|
||||
@ -32,11 +32,11 @@
|
||||
#define G_ON (1)
|
||||
#define G_OFF (0)
|
||||
|
||||
#include "ultra64/gbi.h"
|
||||
#include "ultra64/abi.h"
|
||||
#include "gbi.h"
|
||||
#include "abi.h"
|
||||
|
||||
#define NUM_SEGMENTS (16)
|
||||
#define SEGMENT_OFFSET(a) ((u32)(a) & 0x00ffffff)
|
||||
#define SEGMENT_OFFSET(a) ((u32)(a) & 0x00FFFFFF)
|
||||
#define SEGMENT_NUMBER(a) (((u32)(a) << 4) >> 28)
|
||||
#define SEGMENT_ADDR(num, off) (((num) << 24) + (off))
|
||||
|
||||
|
||||
@ -1,7 +1,7 @@
|
||||
#ifndef ULTRA64_MESSAGE_H
|
||||
#define ULTRA64_MESSAGE_H
|
||||
|
||||
#include "ultra64/types.h"
|
||||
#include "thread.h"
|
||||
|
||||
#define OS_MESG_NOBLOCK 0
|
||||
#define OS_MESG_BLOCK 1
|
||||
|
||||
15
include/ultra64/motor.h
Normal file
15
include/ultra64/motor.h
Normal file
@ -0,0 +1,15 @@
|
||||
#ifndef ULTRA64_MOTOR_H
|
||||
#define ULTRA64_MOTOR_H
|
||||
|
||||
#include "pfs.h"
|
||||
|
||||
#define MOTOR_START 1
|
||||
#define MOTOR_STOP 0
|
||||
|
||||
#define osMotorStart(x) __osMotorAccess((x), MOTOR_START)
|
||||
#define osMotorStop(x) __osMotorAccess((x), MOTOR_STOP)
|
||||
|
||||
s32 __osMotorAccess(OSPfs* pfs, u32 vibrate);
|
||||
s32 osMotorInit(OSMesgQueue* ctrlrqueue, OSPfs* pfs, s32 channel);
|
||||
|
||||
#endif
|
||||
@ -1,7 +1,7 @@
|
||||
#ifndef ULTRA64_PFS_H
|
||||
#define ULTRA64_PFS_H
|
||||
|
||||
#include "ultra64.h"
|
||||
#include "message.h"
|
||||
|
||||
/* File System size */
|
||||
#define OS_PFS_VERSION 0x0200
|
||||
|
||||
@ -1,6 +1,8 @@
|
||||
#ifndef ULTRA64_PI_H
|
||||
#define ULTRA64_PI_H
|
||||
|
||||
#include "message.h"
|
||||
|
||||
typedef struct {
|
||||
/* 0x00 */ u32 errStatus;
|
||||
/* 0x04 */ void* dramAddr;
|
||||
@ -54,10 +56,28 @@ typedef struct {
|
||||
/* 0x14 */ OSPiHandle* piHandle;
|
||||
} OSIoMesg; // size = 0x18
|
||||
|
||||
#define OS_READ 0 // device -> RDRAM
|
||||
#define OS_READ 0 // device -> RDRAM
|
||||
#define OS_WRITE 1 // device <- RDRAM
|
||||
#define OS_OTHERS 2 // for disk drive transfers
|
||||
|
||||
#define PI_DOMAIN1 0
|
||||
#define PI_DOMAIN2 1
|
||||
|
||||
#define OS_MESG_TYPE_LOOPBACK 10
|
||||
#define OS_MESG_TYPE_DMAREAD 11
|
||||
#define OS_MESG_TYPE_DMAWRITE 12
|
||||
#define OS_MESG_TYPE_VRETRACE 13
|
||||
#define OS_MESG_TYPE_COUNTER 14
|
||||
#define OS_MESG_TYPE_EDMAREAD 15
|
||||
#define OS_MESG_TYPE_EDMAWRITE 16
|
||||
|
||||
#define OS_MESG_PRI_NORMAL 0
|
||||
#define OS_MESG_PRI_HIGH 1
|
||||
|
||||
#define DEVICE_TYPE_CART 0 /* ROM cartridge */
|
||||
#define DEVICE_TYPE_BULK 1 /* ROM bulk */
|
||||
#define DEVICE_TYPE_64DD 2 /* 64 Disk Drive */
|
||||
#define DEVICE_TYPE_SRAM 3 /* SRAM */
|
||||
#define DEVICE_TYPE_INIT 7 /* initial value */
|
||||
|
||||
#endif
|
||||
|
||||
@ -1,6 +1,7 @@
|
||||
#ifndef ULTRA64_PRINTF_H
|
||||
#define ULTRA64_PRINTF_H
|
||||
#include "stdarg.h"
|
||||
|
||||
#include "types.h"
|
||||
|
||||
typedef struct {
|
||||
/* 0x0 */ union {
|
||||
|
||||
367
include/ultra64/r4300.h
Normal file
367
include/ultra64/r4300.h
Normal file
@ -0,0 +1,367 @@
|
||||
#ifndef ULTRA64_R4300_H
|
||||
#define ULTRA64_R4300_H
|
||||
|
||||
#ifdef _LANGUAGE_C
|
||||
#include "types.h"
|
||||
#define U32(x) ((u32)x)
|
||||
#define C_REG(x) (x)
|
||||
#else
|
||||
#define U32(x) (x)
|
||||
#define C_REG(x) $x
|
||||
#endif
|
||||
|
||||
// Segment base addresses and sizes
|
||||
#define KUBASE 0
|
||||
#define KUSIZE 0x80000000
|
||||
#define K0BASE 0x80000000
|
||||
#define K0SIZE 0x20000000
|
||||
#define K1BASE 0xA0000000
|
||||
#define K1SIZE 0x20000000
|
||||
#define K2BASE 0xC0000000
|
||||
#define K2SIZE 0x20000000
|
||||
|
||||
// Exception vectors
|
||||
#define SIZE_EXCVEC 0x80 // Size of an exc. vec
|
||||
#define UT_VEC K0BASE // utlbmiss vector
|
||||
#define R_VEC (K1BASE + 0x1FC00000) // reset vector
|
||||
#define XUT_VEC (K0BASE + 0x80) // extended address tlbmiss
|
||||
#define ECC_VEC (K0BASE + 0x100) // Ecc exception vector
|
||||
#define E_VEC (K0BASE + 0x180) // Gen. exception vector
|
||||
|
||||
// Address conversion macros
|
||||
#define K0_TO_K1(x) (U32(x) | 0xA0000000) // kseg0 to kseg1
|
||||
#define K1_TO_K0(x) (U32(x) & 0x9FFFFFFF) // kseg1 to kseg0
|
||||
#define K0_TO_PHYS(x) (U32(x) & 0x1FFFFFFF) // kseg0 to physical
|
||||
#define K1_TO_PHYS(x) (U32(x) & 0x1FFFFFFF) // kseg1 to physical
|
||||
#define KDM_TO_PHYS(x) (U32(x) & 0x1FFFFFFF) // direct mapped to physical
|
||||
#define PHYS_TO_K0(x) (U32(x) | 0x80000000) // physical to kseg0
|
||||
#define PHYS_TO_K1(x) (U32(x) | 0xA0000000) // physical to kseg1
|
||||
|
||||
// Address predicates
|
||||
#define IS_KSEG0(x) (U32(x) >= K0BASE && U32(x) < K1BASE)
|
||||
#define IS_KSEG1(x) (U32(x) >= K1BASE && U32(x) < K2BASE)
|
||||
#define IS_KSEGDM(x) (U32(x) >= K0BASE && U32(x) < K2BASE)
|
||||
#define IS_KSEG2(x) (U32(x) >= K2BASE && U32(x) < KPTE_SHDUBASE)
|
||||
#define IS_KPTESEG(x) (U32(x) >= KPTE_SHDUBASE)
|
||||
#define IS_KUSEG(x) (U32(x) < K0BASE)
|
||||
|
||||
// TLB size constants
|
||||
#define NTLBENTRIES 31 /* entry 31 is reserved by rdb */
|
||||
|
||||
#define TLBHI_VPN2MASK 0xFFFFE000
|
||||
#define TLBHI_VPN2SHIFT 13
|
||||
#define TLBHI_PIDMASK 0xFF
|
||||
#define TLBHI_PIDSHIFT 0
|
||||
#define TLBHI_NPID 255 // 255 to fit in 8 bits
|
||||
|
||||
#define TLBLO_PFNMASK 0x3FFFFFC0
|
||||
#define TLBLO_PFNSHIFT 6
|
||||
#define TLBLO_CACHMASK 0x38 // cache coherency algorithm
|
||||
#define TLBLO_CACHSHIFT 3
|
||||
#define TLBLO_UNCACHED 0x10 // not cached
|
||||
#define TLBLO_NONCOHRNT 0x18 // Cacheable non-coherent
|
||||
#define TLBLO_EXLWR 0x28 // Exclusive write
|
||||
#define TLBLO_D 0x4 // writeable
|
||||
#define TLBLO_V 0x2 // valid bit
|
||||
#define TLBLO_G 0x1 // global access bit
|
||||
|
||||
#define TLBINX_PROBE 0x80000000
|
||||
#define TLBINX_INXMASK 0x3F
|
||||
#define TLBINX_INXSHIFT 0
|
||||
|
||||
#define TLBRAND_RANDMASK 0x3F
|
||||
#define TLBRAND_RANDSHIFT 0
|
||||
|
||||
#define TLBWIRED_WIREDMASK 0x3F
|
||||
|
||||
#define TLBCTXT_BASEMASK 0xFF800000
|
||||
#define TLBCTXT_BASESHIFT 23
|
||||
#define TLBCTXT_BASEBITS 9
|
||||
|
||||
#define TLBCTXT_VPNMASK 0x7FFFF0
|
||||
#define TLBCTXT_VPNSHIFT 4
|
||||
|
||||
#define TLBPGMASK_4K 0x0
|
||||
#define TLBPGMASK_16K 0x6000
|
||||
#define TLBPGMASK_64K 0x1E000
|
||||
|
||||
/*
|
||||
* Status register
|
||||
*/
|
||||
#define SR_CUMASK 0xF0000000 // coproc usable bits
|
||||
|
||||
#define SR_CU3 0x80000000 // Coprocessor 3 usable
|
||||
#define SR_CU2 0x40000000 // Coprocessor 2 usable
|
||||
#define SR_CU1 0x20000000 // Coprocessor 1 usable
|
||||
#define SR_CU0 0x10000000 // Coprocessor 0 usable
|
||||
#define SR_RP 0x08000000 // Reduced power (quarter speed)
|
||||
#define SR_FR 0x04000000 // MIPS III FP register mode
|
||||
#define SR_RE 0x02000000 // Reverse endian
|
||||
#define SR_ITS 0x01000000 // Instruction trace support
|
||||
#define SR_BEV 0x00400000 // Use boot exception vectors
|
||||
#define SR_TS 0x00200000 // TLB shutdown
|
||||
#define SR_SR 0x00100000 // Soft reset occured
|
||||
#define SR_CH 0x00040000 // Cache hit for last 'cache' op
|
||||
#define SR_CE 0x00020000 // Create ECC
|
||||
#define SR_DE 0x00010000 // ECC of parity does not cause error
|
||||
|
||||
// Interrupt enable bits
|
||||
// (NOTE: bits set to 1 enable the corresponding level interrupt)
|
||||
#define SR_IMASK 0x0000FF00 // Interrupt mask
|
||||
#define SR_IMASK8 0x00000000 // mask level 8
|
||||
#define SR_IMASK7 0x00008000 // mask level 7
|
||||
#define SR_IMASK6 0x0000C000 // mask level 6
|
||||
#define SR_IMASK5 0x0000E000 // mask level 5
|
||||
#define SR_IMASK4 0x0000F000 // mask level 4
|
||||
#define SR_IMASK3 0x0000F800 // mask level 3
|
||||
#define SR_IMASK2 0x0000FC00 // mask level 2
|
||||
#define SR_IMASK1 0x0000FE00 // mask level 1
|
||||
#define SR_IMASK0 0x0000FF00 // mask level 0
|
||||
|
||||
#define SR_IBIT8 0x00008000 // bit level 8
|
||||
#define SR_IBIT7 0x00004000 // bit level 7
|
||||
#define SR_IBIT6 0x00002000 // bit level 6
|
||||
#define SR_IBIT5 0x00001000 // bit level 5
|
||||
#define SR_IBIT4 0x00000800 // bit level 4
|
||||
#define SR_IBIT3 0x00000400 // bit level 3
|
||||
#define SR_IBIT2 0x00000200 // bit level 2
|
||||
#define SR_IBIT1 0x00000100 // bit level 1
|
||||
|
||||
#define SR_IMASKSHIFT 8
|
||||
|
||||
#define SR_KX 0x00000080 // extended-addr TLB vec in kernel
|
||||
#define SR_SX 0x00000040 // xtended-addr TLB vec supervisor
|
||||
#define SR_UX 0x00000020 // xtended-addr TLB vec in user mode
|
||||
#define SR_KSU_MASK 0x00000018 // mode mask
|
||||
#define SR_KSU_USR 0x00000010 // user mode
|
||||
#define SR_KSU_SUP 0x00000008 // supervisor mode
|
||||
#define SR_KSU_KER 0x00000000 // kernel mode
|
||||
#define SR_ERL 0x00000004 // Error level, 1=>cache error
|
||||
#define SR_EXL 0x00000002 // Exception level, 1=>exception
|
||||
#define SR_IE 0x00000001 // interrupt enable, 1=>enable
|
||||
|
||||
// Cause Register
|
||||
#define CAUSE_BD 0x80000000 // Branch delay slot
|
||||
#define CAUSE_CEMASK 0x30000000 // coprocessor error
|
||||
#define CAUSE_CESHIFT 28
|
||||
|
||||
// Interrupt pending bits
|
||||
#define CAUSE_IP8 0x00008000 // External level 8 pending - COMPARE
|
||||
#define CAUSE_IP7 0x00004000 // External level 7 pending - INT4
|
||||
#define CAUSE_IP6 0x00002000 // External level 6 pending - INT3
|
||||
#define CAUSE_IP5 0x00001000 // External level 5 pending - INT2
|
||||
#define CAUSE_IP4 0x00000800 // External level 4 pending - INT1
|
||||
#define CAUSE_IP3 0x00000400 // External level 3 pending - INT0
|
||||
#define CAUSE_SW2 0x00000200 // Software level 2 pending
|
||||
#define CAUSE_SW1 0x00000100 // Software level 1 pending
|
||||
|
||||
#define CAUSE_IPMASK 0x0000FF00 // Pending interrupt mask
|
||||
#define CAUSE_IPSHIFT 8
|
||||
|
||||
#define CAUSE_EXCMASK 0x0000007C // Cause code bits
|
||||
#define CAUSE_EXCSHIFT 2
|
||||
|
||||
// Cause register exception codes
|
||||
|
||||
#define EXC_CODE(x) ((x) << 2)
|
||||
|
||||
// Hardware exception codes
|
||||
#define EXC_INT EXC_CODE(0) // interrupt
|
||||
#define EXC_MOD EXC_CODE(1) // TLB mod
|
||||
#define EXC_RMISS EXC_CODE(2) // Read TLB Miss
|
||||
#define EXC_WMISS EXC_CODE(3) // Write TLB Miss
|
||||
#define EXC_RADE EXC_CODE(4) // Read Address Error
|
||||
#define EXC_WADE EXC_CODE(5) // Write Address Error
|
||||
#define EXC_IBE EXC_CODE(6) // Instruction Bus Error
|
||||
#define EXC_DBE EXC_CODE(7) // Data Bus Error
|
||||
#define EXC_SYSCALL EXC_CODE(8) // SYSCALL
|
||||
#define EXC_BREAK EXC_CODE(9) // BREAKpoint
|
||||
#define EXC_II EXC_CODE(10) // Illegal Instruction
|
||||
#define EXC_CPU EXC_CODE(11) // CoProcessor Unusable
|
||||
#define EXC_OV EXC_CODE(12) // OVerflow
|
||||
#define EXC_TRAP EXC_CODE(13) // Trap exception
|
||||
#define EXC_VCEI EXC_CODE(14) // Virt. Coherency on Inst. fetch
|
||||
#define EXC_FPE EXC_CODE(15) // Floating Point Exception
|
||||
#define EXC_WATCH EXC_CODE(23) // Watchpoint reference
|
||||
#define EXC_VCED EXC_CODE(31) // Virt. Coherency on data read
|
||||
|
||||
// C0_PRID Defines
|
||||
#define C0_IMPMASK 0xFF00
|
||||
#define C0_IMPSHIFT 8
|
||||
#define C0_REVMASK 0xFF
|
||||
#define C0_MAJREVMASK 0xF0
|
||||
#define C0_MAJREVSHIFT 4
|
||||
#define C0_MINREVMASK 0xF
|
||||
|
||||
// Coprocessor 0 operations
|
||||
#define C0_READI 0x1 // read ITLB entry addressed by C0_INDEX
|
||||
#define C0_WRITEI 0x2 // write ITLB entry addressed by C0_INDEX
|
||||
#define C0_WRITER 0x6 // write ITLB entry addressed by C0_RAND
|
||||
#define C0_PROBE 0x8 // probe for ITLB entry addressed by TLBHI
|
||||
#define C0_RFE 0x10 // restore for exception
|
||||
|
||||
// 'cache' instruction definitions
|
||||
|
||||
// Target cache
|
||||
#define CACH_PI 0x0 // specifies primary inst. cache
|
||||
#define CACH_PD 0x1 // primary data cache
|
||||
#define CACH_SI 0x2 // secondary instruction cache
|
||||
#define CACH_SD 0x3 // secondary data cache
|
||||
|
||||
// Cache operations
|
||||
#define C_IINV 0x0 // index invalidate (inst, 2nd inst)
|
||||
#define C_IWBINV 0x0 // index writeback inval (d, sd)
|
||||
#define C_ILT 0x4 // index load tag (all)
|
||||
#define C_IST 0x8 // index store tag (all)
|
||||
#define C_CDX 0xC // create dirty exclusive (d, sd)
|
||||
#define C_HINV 0x10 // hit invalidate (all)
|
||||
#define C_HWBINV 0x14 // hit writeback inv. (d, sd)
|
||||
#define C_FILL 0x14 // fill (i)
|
||||
#define C_HWB 0x18 // hit writeback (i, d, sd)
|
||||
#define C_HSV 0x1C // hit set virt. (si, sd)
|
||||
|
||||
// Cache size definitions
|
||||
#define ICACHE_SIZE 0x4000 // 16K
|
||||
#define ICACHE_LINESIZE 32 // 8 words
|
||||
#define ICACHE_LINEMASK (ICACHE_LINESIZE - 1)
|
||||
|
||||
#define DCACHE_SIZE 0x2000 // 8K
|
||||
#define DCACHE_LINESIZE 16 // 4 words
|
||||
#define DCACHE_LINEMASK (DCACHE_LINESIZE - 1)
|
||||
|
||||
// C0_CONFIG register definitions
|
||||
#define CONFIG_CM 0x80000000 // 1 == Master-Checker enabled
|
||||
#define CONFIG_EC 0x70000000 // System Clock ratio
|
||||
#define CONFIG_EC_1_1 0x6 // System Clock ratio 1 :1
|
||||
#define CONFIG_EC_3_2 0x7 // System Clock ratio 1.5 :1
|
||||
#define CONFIG_EC_2_1 0x0 // System Clock ratio 2 :1
|
||||
#define CONFIG_EC_3_1 0x1 // System Clock ratio 3 :1
|
||||
#define CONFIG_EP 0x0F000000 // Transmit Data Pattern
|
||||
#define CONFIG_SB 0x00C00000 // Secondary cache block size
|
||||
|
||||
#define CONFIG_SS 0x00200000 // Split scache: 0 == I&D combined
|
||||
#define CONFIG_SW 0x00100000 // scache port: 0==128, 1==64
|
||||
#define CONFIG_EW 0x000C0000 // System Port width: 0==64, 1==32
|
||||
#define CONFIG_SC 0x00020000 // 0 -> 2nd cache present
|
||||
#define CONFIG_SM 0x00010000 // 0 -> Dirty Shared Coherency enable
|
||||
#define CONFIG_BE 0x00008000 // Endian-ness: 1 --> BE
|
||||
#define CONFIG_EM 0x00004000 // 1 -> ECC mode, 0 -> parity
|
||||
#define CONFIG_EB 0x00002000 // Block order:1->sequent,0->subblock
|
||||
|
||||
#define CONFIG_IC 0x00000E00 // Primary Icache size
|
||||
#define CONFIG_DC 0x000001C0 // Primary Dcache size
|
||||
#define CONFIG_IB 0x00000020 // Icache block size
|
||||
#define CONFIG_DB 0x00000010 // Dcache block size
|
||||
#define CONFIG_CU 0x00000008 // Update on Store-conditional
|
||||
#define CONFIG_K0 0x00000007 // K0SEG Coherency algorithm
|
||||
|
||||
#define CONFIG_UNCACHED 0x00000002 // K0 is uncached
|
||||
#define CONFIG_NONCOHRNT 0x00000003
|
||||
#define CONFIG_COHRNT_EXLWR 0x00000005
|
||||
#define CONFIG_SB_SHFT 22 // shift SB to bit position 0
|
||||
#define CONFIG_IC_SHFT 9 // shift IC to bit position 0
|
||||
#define CONFIG_DC_SHFT 6 // shift DC to bit position 0
|
||||
#define CONFIG_BE_SHFT 15 // shift BE to bit position 0
|
||||
|
||||
// C0_TAGLO definitions for setting/getting cache states and physaddr bits
|
||||
#define SADDRMASK 0xFFFFE000 // 31..13 -> scache paddr bits 35..17
|
||||
#define SVINDEXMASK 0x00000380 // 9..7: prim virt index bits 14..12
|
||||
#define SSTATEMASK 0x00001C00 // bits 12..10 hold scache line state
|
||||
#define SINVALID 0x00000000 // invalid --> 000 == state 0
|
||||
#define SCLEANEXCL 0x00001000 // clean exclusive --> 100 == state 4
|
||||
#define SDIRTYEXCL 0x00001400 // dirty exclusive --> 101 == state 5
|
||||
#define SECC_MASK 0x0000007F // low 7 bits are ecc for the tag
|
||||
#define SADDR_SHIFT 4 // shift STagLo (31..13) to 35..17
|
||||
|
||||
#define PADDRMASK 0xFFFFFF00 // PTagLo31..8->prim paddr bits35..12
|
||||
#define PADDR_SHIFT 4 // roll bits 35..12 down to 31..8
|
||||
#define PSTATEMASK 0x00C0 // bits 7..6 hold primary line state
|
||||
#define PINVALID 0x0000 // invalid --> 000 == state 0
|
||||
#define PCLEANEXCL 0x0080 // clean exclusive --> 10 == state 2
|
||||
#define PDIRTYEXCL 0x00C0 // dirty exclusive --> 11 == state 3
|
||||
#define PPARITY_MASK 0x0001 // low bit is parity bit (even).
|
||||
|
||||
// C0_CACHE_ERR definitions.
|
||||
#define CACHERR_ER 0x80000000 // 0: inst ref, 1: data ref
|
||||
#define CACHERR_EC 0x40000000 // 0: primary, 1: secondary
|
||||
#define CACHERR_ED 0x20000000 // 1: data error
|
||||
#define CACHERR_ET 0x10000000 // 1: tag error
|
||||
#define CACHERR_ES 0x08000000 // 1: external ref, e.g. snoo
|
||||
#define CACHERR_EE 0x04000000 // error on SysAD bus
|
||||
#define CACHERR_EB 0x02000000 // complicated, see spec.
|
||||
#define CACHERR_EI 0x01000000 // complicated, see spec.
|
||||
#define CACHERR_SIDX_MASK 0x003FFFF8 // secondary cache index
|
||||
#define CACHERR_PIDX_MASK 0x00000007 // primary cache index
|
||||
#define CACHERR_PIDX_SHIFT 12 // bits 2..0 are paddr14..12
|
||||
|
||||
/*
|
||||
* R4000 family supports hardware watchpoints:
|
||||
* C0_WATCHLO:
|
||||
* bits 31..3 are bits 31..3 of physaddr to watch
|
||||
* bit 2: reserved; must be written as 0.
|
||||
* bit 1: when set causes a watchpoint trap on load accesses to paddr.
|
||||
* bit 0: when set traps on stores to paddr;
|
||||
* C0_WATCHHI
|
||||
* bits 31..4 are reserved and must be written as zeros.
|
||||
* bits 3..0 are bits 35..32 of the physaddr to watch
|
||||
*/
|
||||
#define WATCHLO_WTRAP 0x00000001
|
||||
#define WATCHLO_RTRAP 0x00000002
|
||||
#define WATCHLO_ADDRMASK 0xFFFFFFF8
|
||||
#define WATCHLO_VALIDMASK 0xFFFFFFFB
|
||||
#define WATCHHI_VALIDMASK 0x0000000F
|
||||
|
||||
// Coprocessor 0 registers
|
||||
#define C0_INX C_REG(0)
|
||||
#define C0_RAND C_REG(1)
|
||||
#define C0_ENTRYLO0 C_REG(2)
|
||||
#define C0_ENTRYLO1 C_REG(3)
|
||||
#define C0_CONTEXT C_REG(4)
|
||||
#define C0_PAGEMASK C_REG(5) // page mask
|
||||
#define C0_WIRED C_REG(6) // # wired entries in tlb
|
||||
#define C0_BADVADDR C_REG(8)
|
||||
#define C0_COUNT C_REG(9) // free-running counter
|
||||
#define C0_ENTRYHI C_REG(10)
|
||||
#define C0_COMPARE C_REG(11) // counter comparison reg.
|
||||
#define C0_SR C_REG(12)
|
||||
#define C0_CAUSE C_REG(13)
|
||||
#define C0_EPC C_REG(14)
|
||||
#define C0_PRID C_REG(15) // revision identifier
|
||||
#define C0_CONFIG C_REG(16) // hardware configuration
|
||||
#define C0_LLADDR C_REG(17) // load linked address
|
||||
#define C0_WATCHLO C_REG(18) // watchpoint
|
||||
#define C0_WATCHHI C_REG(19) // watchpoint
|
||||
#define C0_ECC C_REG(26) // S-cache ECC and primary parity
|
||||
#define C0_CACHE_ERR C_REG(27) // cache error status
|
||||
#define C0_TAGLO C_REG(28) // cache operations
|
||||
#define C0_TAGHI C_REG(29) // cache operations
|
||||
#define C0_ERROR_EPC C_REG(30) // ECC error prg. counter
|
||||
|
||||
// floating-point status register
|
||||
#define C1_FPCSR C_REG(31)
|
||||
|
||||
#define FPCSR_FS 0x01000000 // flush denorm to zero
|
||||
#define FPCSR_C 0x00800000 // condition bit
|
||||
#define FPCSR_CE 0x00020000 // cause: unimplemented operation
|
||||
#define FPCSR_CV 0x00010000 // cause: invalid operation
|
||||
#define FPCSR_CZ 0x00008000 // cause: division by zero
|
||||
#define FPCSR_CO 0x00004000 // cause: overflow
|
||||
#define FPCSR_CU 0x00002000 // cause: underflow
|
||||
#define FPCSR_CI 0x00001000 // cause: inexact operation
|
||||
#define FPCSR_EV 0x00000800 // enable: invalid operation
|
||||
#define FPCSR_EZ 0x00000400 // enable: division by zero
|
||||
#define FPCSR_EO 0x00000200 // enable: overflow
|
||||
#define FPCSR_EU 0x00000100 // enable: underflow
|
||||
#define FPCSR_EI 0x00000080 // enable: inexact operation
|
||||
#define FPCSR_FV 0x00000040 // flag: invalid operation
|
||||
#define FPCSR_FZ 0x00000020 // flag: division by zero
|
||||
#define FPCSR_FO 0x00000010 // flag: overflow
|
||||
#define FPCSR_FU 0x00000008 // flag: underflow
|
||||
#define FPCSR_FI 0x00000004 // flag: inexact operation
|
||||
#define FPCSR_RM_MASK 0x00000003 // rounding mode mask
|
||||
#define FPCSR_RM_RN 0x00000000 // round to nearest
|
||||
#define FPCSR_RM_RZ 0x00000001 // round to zero
|
||||
#define FPCSR_RM_RP 0x00000002 // round to positive infinity
|
||||
#define FPCSR_RM_RM 0x00000003 // round to negative infinity
|
||||
|
||||
#endif
|
||||
@ -1,14 +1,95 @@
|
||||
#ifndef ULTRA64_RCP_H
|
||||
#define ULTRA64_RCP_H
|
||||
|
||||
#define VI_NTSC_CLOCK 48681812 /* Hz = 48.681812 MHz */
|
||||
#define VI_PAL_CLOCK 49656530 /* Hz = 49.656530 MHz */
|
||||
#define VI_MPAL_CLOCK 48628316 /* Hz = 48.628316 MHz */
|
||||
#define HW_REG(reg, type) *(volatile type*)((reg) | 0xA0000000)
|
||||
|
||||
#define DEVICE_TYPE_CART 0 /* ROM cartridge */
|
||||
#define DEVICE_TYPE_BULK 1 /* ROM bulk */
|
||||
#define DEVICE_TYPE_64DD 2 /* 64 Disk Drive */
|
||||
#define DEVICE_TYPE_SRAM 3 /* SRAM */
|
||||
#define DEVICE_TYPE_INIT 7 /* initial value */
|
||||
#define AI_DRAM_ADDR_REG 0x04500000
|
||||
#define AI_LEN_REG 0x04500004
|
||||
#define AI_CONTROL_REG 0x04500008
|
||||
#define AI_STATUS_REG 0x0450000C
|
||||
#define AI_DACRATE_REG 0x04500010
|
||||
#define AI_BITRATE_REG 0x04500014
|
||||
|
||||
#define AI_STATUS_AI_FULL (1 << 31)
|
||||
#define AI_STATUS_AI_BUSY (1 << 30)
|
||||
|
||||
#define VI_STATUS_REG 0x04400000
|
||||
#define VI_CONTROL_REG VI_STATUS_REG
|
||||
#define VI_ORIGIN_REG 0x04400004
|
||||
#define VI_DRAM_ADDR_REG VI_ORIGIN_REG
|
||||
#define VI_WIDTH_REG 0x04400008
|
||||
#define VI_H_WIDTH_REG VI_WIDTH_REG
|
||||
#define VI_INTR_REG 0x0440000C
|
||||
#define VI_V_INTER_REG VI_H_WIDTH_REG
|
||||
#define VI_CURRENT_REG 0x04400010
|
||||
#define VI_V_CURRENT_LINE_REG VI_CURRENT_REG
|
||||
#define VI_BURST_REG 0x04400014
|
||||
#define VI_TIMING_REG VI_BURST_REG
|
||||
#define VI_V_SYNC_REG 0x04400018 //VI vertical sync
|
||||
#define VI_H_SYNC_REG 0x0440001C //VI horizontal sync
|
||||
#define VI_LEAP_REG 0x04400020 //VI horizontal sync leap
|
||||
#define VI_H_SYNC_LEAP_REG VI_LEAP_REG
|
||||
#define VI_H_START_REG 0x04400024 //VI horizontal video
|
||||
#define VI_H_VIDEO_REG VI_H_START_REG
|
||||
#define VI_V_START_REG 0x04400028 //VI vertical video
|
||||
#define VI_V_VIDEO_REG VI_V_START_REG
|
||||
#define VI_V_BURST_REG 0x0440002C //VI vertical burst
|
||||
#define VI_X_SCALE_REG 0x04400030 //VI x-scale
|
||||
#define VI_Y_SCALE_REG 0x04400034 //VI y-scale
|
||||
|
||||
#define SP_IMEM_START 0x04001000
|
||||
#define SP_DMEM_START 0x04000000
|
||||
|
||||
#define SP_MEM_ADDR_REG 0x04040000
|
||||
#define SP_DRAM_ADDR_REG 0x04040004
|
||||
#define SP_RD_LEN_REG 0x04040008
|
||||
#define SP_WR_LEN_REG 0x0404000C
|
||||
#define SP_STATUS_REG 0x04040010
|
||||
#define SP_PC_REG 0x04080000
|
||||
|
||||
#define PI_DRAM_ADDR_REG 0x04600000 //PI DRAM address
|
||||
#define PI_CART_ADDR_REG 0x04600004 //PI pbus (cartridge) address
|
||||
#define PI_RD_LEN_REG 0x04600008 //PI read length
|
||||
#define PI_WR_LEN_REG 0x0460000C //PI write length
|
||||
#define PI_STATUS_REG 0x04600010 //PI status
|
||||
#define PI_BSD_DOM1_LAT_REG 0x04600014 //PI dom1 latency
|
||||
#define PI_DOMAIN1_REG 0x04600014
|
||||
#define PI_BSD_DOM1_PWD_REG 0x04600018 //PI dom1 pulse width
|
||||
#define PI_BSD_DOM1_PGS_REG 0x0460001C //PI dom1 page size
|
||||
#define PI_BSD_DOM1_RLS_REG 0x04600020 //PI dom1 release
|
||||
#define PI_BSD_DOM2_LAT_REG 0x04600024 //PI dom2 latency
|
||||
#define PI_DOMAIN2_REG 0x04600024
|
||||
#define PI_BSD_DOM2_PWD_REG 0x04600028 //PI dom2 pulse width
|
||||
#define PI_BSD_DOM2_PGS_REG 0x0460002C //PI dom2 page size
|
||||
#define PI_BSD_DOM2_RLS_REG 0x04600030 //PI dom2 release
|
||||
|
||||
#define PI_STATUS_BUSY 0x1
|
||||
#define PI_STATUS_IOBUSY 0x2
|
||||
#define PI_STATUS_ERROR 0x4
|
||||
|
||||
#define PI_STATUS_RESET_CONTROLLER 0x1
|
||||
#define PI_STATUS_CLEAR_INTR 0x2
|
||||
|
||||
#define SI_DRAM_ADDR_REG 0x04800000
|
||||
#define SI_PIF_ADDR_RD64B_REG 0x04800004
|
||||
#define SI_PIF_ADDR_WR64B_REG 0x04800010
|
||||
#define SI_STATUS_REG 0x04800018
|
||||
|
||||
#define SI_STATUS_DMA_BUSY 0x1
|
||||
#define SI_STATUS_IO_READ_BUSY 0x2
|
||||
#define SI_STATUS_DMA_ERROR 0x8
|
||||
#define SI_STATUS_INTERRUPT (1 << 12)
|
||||
|
||||
#define PIF_RAM_START 0x1FC007C0
|
||||
|
||||
#define MI_INIT_MODE_REG 0x04300000
|
||||
#define MI_MODE_REG MI_INIT_MODE_REG
|
||||
#define MI_VERSION_REG 0x04300004
|
||||
#define MI_INTR_REG 0x04300008
|
||||
#define MI_INTR_MASK_REG 0x0430000C
|
||||
|
||||
#define VI_NTSC_CLOCK 48681812 /* Hz = 48.681812 MHz */
|
||||
#define VI_PAL_CLOCK 49656530 /* Hz = 49.656530 MHz */
|
||||
#define VI_MPAL_CLOCK 48628316 /* Hz = 48.628316 MHz */
|
||||
|
||||
#endif
|
||||
|
||||
@ -5,19 +5,18 @@
|
||||
|
||||
#define DPC_REG_BASE 0xA4100000
|
||||
|
||||
#define DPC_START_REG (*(vu32*)(DPC_REG_BASE + 0x00))
|
||||
#define DPC_END_REG (*(vu32*)(DPC_REG_BASE + 0x04))
|
||||
#define DPC_CURRENT_REG (*(vu32*)(DPC_REG_BASE + 0x08))
|
||||
#define DPC_STATUS_REG (*(vu32*)(DPC_REG_BASE + 0x0C))
|
||||
#define DPC_CLOCK_REG (*(vu32*)(DPC_REG_BASE + 0x10))
|
||||
#define DPC_BUFBUSY_REG (*(vu32*)(DPC_REG_BASE + 0x14))
|
||||
#define DPC_PIPEBUSY_REG (*(vu32*)(DPC_REG_BASE + 0x18))
|
||||
#define DPC_TMEM_REG (*(vu32*)(DPC_REG_BASE + 0x1C))
|
||||
|
||||
#define DPC_START_REG (*(vu32*)(DPC_REG_BASE + 0x00))
|
||||
#define DPC_END_REG (*(vu32*)(DPC_REG_BASE + 0x04))
|
||||
#define DPC_CURRENT_REG (*(vu32*)(DPC_REG_BASE + 0x08))
|
||||
#define DPC_STATUS_REG (*(vu32*)(DPC_REG_BASE + 0x0C))
|
||||
#define DPC_CLOCK_REG (*(vu32*)(DPC_REG_BASE + 0x10))
|
||||
#define DPC_BUFBUSY_REG (*(vu32*)(DPC_REG_BASE + 0x14))
|
||||
#define DPC_PIPEBUSY_REG (*(vu32*)(DPC_REG_BASE + 0x18))
|
||||
#define DPC_TMEM_REG (*(vu32*)(DPC_REG_BASE + 0x1C))
|
||||
|
||||
/* DP Span Registers */
|
||||
|
||||
#define DPS_REG_BASE 0xA4200000
|
||||
#define DPS_REG_BASE 0xA4200000
|
||||
|
||||
#define DPS_TBIST_REG (*(vu32*)(DPS_REG_BASE + 0x00))
|
||||
#define DPS_TEST_MODE_REG (*(vu32*)(DPS_REG_BASE + 0x04))
|
||||
|
||||
@ -1,14 +1,16 @@
|
||||
#ifndef ULTRA64_SPTASK_H
|
||||
#define ULTRA64_SPTASK_H
|
||||
|
||||
#include "types.h"
|
||||
|
||||
/* Task Types */
|
||||
#define M_NULTASK 0
|
||||
#define M_GFXTASK 1
|
||||
#define M_AUDTASK 2
|
||||
#define M_VIDTASK 3
|
||||
#define M_NULTASK 0
|
||||
#define M_GFXTASK 1
|
||||
#define M_AUDTASK 2
|
||||
#define M_VIDTASK 3
|
||||
#define M_NJPEGTASK 4
|
||||
#define M_HVQTASK 6
|
||||
#define M_HVQMTASK 7
|
||||
#define M_HVQTASK 6
|
||||
#define M_HVQMTASK 7
|
||||
|
||||
/* Task Flags */
|
||||
#define M_TASK_FLAG0 1
|
||||
@ -52,8 +54,7 @@ typedef struct {
|
||||
/* 0x3C */ u32 yield_data_size;
|
||||
} OSTask_t; // size = 0x40
|
||||
|
||||
typedef union
|
||||
{
|
||||
typedef union {
|
||||
OSTask_t t;
|
||||
long long int force_structure_alignment;
|
||||
} OSTask;
|
||||
|
||||
@ -1,6 +1,8 @@
|
||||
#ifndef ULTRA64_THREAD_H
|
||||
#define ULTRA64_THREAD_H
|
||||
|
||||
#include "types.h"
|
||||
|
||||
#define OS_PRIORITY_MAX 255
|
||||
#define OS_PRIORITY_VIMGR 254
|
||||
#define OS_PRIORITY_RMON 250
|
||||
@ -15,6 +17,9 @@
|
||||
#define OS_STATE_RUNNING 4
|
||||
#define OS_STATE_WAITING 8
|
||||
|
||||
#define OS_FLAG_CPU_BREAK 1
|
||||
#define OS_FLAG_FAULT 2
|
||||
|
||||
typedef s32 OSPri;
|
||||
typedef s32 OSId;
|
||||
|
||||
|
||||
@ -1,7 +1,7 @@
|
||||
#ifndef ULTRA64_TIME_H
|
||||
#define ULTRA64_TIME_H
|
||||
|
||||
#include "ultra64/message.h"
|
||||
#include "message.h"
|
||||
|
||||
typedef u64 OSTime;
|
||||
|
||||
|
||||
@ -1,6 +1,8 @@
|
||||
#ifndef ULTRA64_VI_H
|
||||
#define ULTRA64_VI_H
|
||||
|
||||
#include "message.h"
|
||||
|
||||
/* Special Features */
|
||||
#define OS_VI_GAMMA_ON 0x0001
|
||||
#define OS_VI_GAMMA_OFF 0x0002
|
||||
@ -60,7 +62,7 @@ typedef struct {
|
||||
/* 0x02 */ u16 retraceCount;
|
||||
/* 0x04 */ void* buffer;
|
||||
/* 0x08 */ OSViMode* modep;
|
||||
/* 0x0c */ u32 features;
|
||||
/* 0x0C */ u32 features;
|
||||
/* 0x10 */ OSMesgQueue* mq;
|
||||
/* 0x14 */ OSMesg* msg;
|
||||
/* 0x18 */ __OSViScale x;
|
||||
@ -97,6 +99,36 @@ typedef struct {
|
||||
#define OS_VI_PAL_HPN2 26
|
||||
#define OS_VI_PAL_HPF2 27
|
||||
|
||||
#define OS_VI_MPAL_LPN1 28 /* MPAL - mainly Brazil */
|
||||
#define OS_VI_MPAL_LPF1 29
|
||||
#define OS_VI_MPAL_LAN1 30
|
||||
#define OS_VI_MPAL_LAF1 31
|
||||
#define OS_VI_MPAL_LPN2 32
|
||||
#define OS_VI_MPAL_LPF2 33
|
||||
#define OS_VI_MPAL_LAN2 34
|
||||
#define OS_VI_MPAL_LAF2 35
|
||||
#define OS_VI_MPAL_HPN1 36
|
||||
#define OS_VI_MPAL_HPF1 37
|
||||
#define OS_VI_MPAL_HAN1 38
|
||||
#define OS_VI_MPAL_HAF1 39
|
||||
#define OS_VI_MPAL_HPN2 40
|
||||
#define OS_VI_MPAL_HPF2 41
|
||||
|
||||
#define OS_VI_FPAL_LPN1 42 /* FPAL - Full screen PAL */
|
||||
#define OS_VI_FPAL_LPF1 43
|
||||
#define OS_VI_FPAL_LAN1 44
|
||||
#define OS_VI_FPAL_LAF1 45
|
||||
#define OS_VI_FPAL_LPN2 46
|
||||
#define OS_VI_FPAL_LPF2 47
|
||||
#define OS_VI_FPAL_LAN2 48
|
||||
#define OS_VI_FPAL_LAF2 49
|
||||
#define OS_VI_FPAL_HPN1 50
|
||||
#define OS_VI_FPAL_HPF1 51
|
||||
#define OS_VI_FPAL_HAN1 52
|
||||
#define OS_VI_FPAL_HAF1 53
|
||||
#define OS_VI_FPAL_HPN2 54
|
||||
#define OS_VI_FPAL_HPF2 55
|
||||
|
||||
#define OS_TV_PAL 0
|
||||
#define OS_TV_NTSC 1
|
||||
#define OS_TV_MPAL 2
|
||||
|
||||
@ -37,7 +37,7 @@ extern OSViMode osViModePalLan1;
|
||||
extern u64 osClockRate;
|
||||
extern s32 osViClock;
|
||||
extern u32 __osShutdown;
|
||||
extern u32 __OSGlobalIntMask;
|
||||
extern OSHWIntr __OSGlobalIntMask;
|
||||
extern OSThread* __osThreadTail[];
|
||||
extern OSThread* __osRunQueue;
|
||||
extern OSThread* __osActiveQueue;
|
||||
|
||||
@ -27,8 +27,6 @@
|
||||
#include "sfx.h"
|
||||
#include "color.h"
|
||||
#include "ichain.h"
|
||||
#include "stdarg.h"
|
||||
#include "stdlib.h"
|
||||
#include "regs.h"
|
||||
|
||||
#define SCREEN_WIDTH 320
|
||||
|
||||
242
spec
242
spec
@ -21,92 +21,92 @@ beginseg
|
||||
include "build/src/boot/z_locale.o"
|
||||
include "build/src/boot/assert.o"
|
||||
include "build/src/boot/is_debug.o"
|
||||
include "build/src/libultra_boot_O2/osDriveRomInit.o"
|
||||
include "build/src/libultra/io/driverominit.o"
|
||||
include "build/asm/mio0.o"
|
||||
include "build/src/boot/stackcheck.o"
|
||||
include "build/src/boot/logutils.o"
|
||||
include "build/src/libultra_boot_O2/sprintf.o"
|
||||
include "build/src/libultra_boot_O1/piacs.o"
|
||||
include "build/src/libultra_boot_O1/osSendMesg.o"
|
||||
include "build/src/libultra_boot_O1/osStopThread.o"
|
||||
include "build/src/libultra_boot_O1/osViExtendVStart.o"
|
||||
include "build/src/libultra_boot_O1/osViModePalLan1.o"
|
||||
include "build/src/libultra_boot_O1/osRecvMesg.o"
|
||||
include "build/src/libultra_boot_O1/initialize.o"
|
||||
include "build/src/libultra_boot_O1/ll.o"
|
||||
include "build/src/libultra/rmon/sprintf.o"
|
||||
include "build/src/libultra/io/piacs.o"
|
||||
include "build/src/libultra/os/sendmesg.o"
|
||||
include "build/src/libultra/os/stopthread.o"
|
||||
include "build/src/libultra/io/viextend.o"
|
||||
include "build/src/libultra/io/vimodepallan1.o"
|
||||
include "build/src/libultra/os/recvmesg.o"
|
||||
include "build/src/libultra/os/initialize.o"
|
||||
include "build/src/libultra/libc/ll.o"
|
||||
include "build/asm/exceptasm.o"
|
||||
include "build/src/libultra_boot_O1/__osDequeueThread.o"
|
||||
include "build/src/libultra_boot_O1/osDestroyThread.o"
|
||||
include "build/src/libultra/os/dequeuethread.o"
|
||||
include "build/src/libultra/os/destroythread.o"
|
||||
include "build/asm/bzero.o"
|
||||
include "build/src/libultra_boot_O1/osCreateThread.o"
|
||||
include "build/src/libultra/os/createthread.o"
|
||||
include "build/asm/__osSetSR.o"
|
||||
include "build/asm/__osGetSR.o"
|
||||
include "build/asm/osWritebackDCache.o"
|
||||
include "build/src/libultra_boot_O2/osViGetNextFramebuffer.o"
|
||||
include "build/src/libultra_boot_O2/pimgr.o"
|
||||
include "build/src/libultra_boot_O2/__osDevMgrMain.o"
|
||||
include "build/src/libultra_boot_O2/__osPiRawStartDma.o"
|
||||
include "build/src/libultra_boot_O1/osVirtualToPhysical.o"
|
||||
include "build/src/libultra_boot_O2/osViBlack.o"
|
||||
include "build/src/libultra_boot_O2/__osSiRawReadIo.o"
|
||||
include "build/src/libultra_boot_O1/osGetThreadId.o"
|
||||
include "build/src/libultra/io/vigetnextframebuf.o"
|
||||
include "build/src/libultra/io/pimgr.o"
|
||||
include "build/src/libultra/io/devmgr.o"
|
||||
include "build/src/libultra/io/pirawdma.o"
|
||||
include "build/src/libultra/os/virtualtophysical.o"
|
||||
include "build/src/libultra/io/viblack.o"
|
||||
include "build/src/libultra/io/sirawread.o"
|
||||
include "build/src/libultra/os/getthreadid.o"
|
||||
include "build/asm/osSetIntMask.o"
|
||||
include "build/src/libultra_boot_O2/osViSetMode.o"
|
||||
include "build/src/libultra/io/visetmode.o"
|
||||
include "build/asm/__osProbeTLB.o"
|
||||
include "build/src/libultra_boot_O1/osGetMemSize.o"
|
||||
include "build/src/libultra_boot_O1/osSetEventMesg.o"
|
||||
include "build/src/libultra_boot_O2/_Printf.o"
|
||||
include "build/src/libultra/os/getmemsize.o"
|
||||
include "build/src/libultra/os/seteventmesg.o"
|
||||
include "build/src/libultra/rmon/xprintf.o"
|
||||
include "build/asm/osUnmapTLBAll.o"
|
||||
include "build/src/libultra_boot_O2/osEPiStartDma.o"
|
||||
include "build/src/libultra_boot_O2/string.o"
|
||||
include "build/src/libultra/io/epidma.o"
|
||||
include "build/src/libultra/libc/string.o"
|
||||
include "build/asm/osInvalICache.o"
|
||||
include "build/src/libultra_boot_O1/osCreateMesgQueue.o"
|
||||
include "build/src/libultra/os/createmesgqueue.o"
|
||||
include "build/asm/osInvalDCache.o"
|
||||
include "build/src/libultra_boot_O2/__osSiDeviceBusy.o"
|
||||
include "build/src/libultra_boot_O1/osJamMesg.o"
|
||||
include "build/src/libultra_boot_O1/osSetThreadPri.o"
|
||||
include "build/src/libultra_boot_O1/osGetThreadPri.o"
|
||||
include "build/src/libultra_boot_O2/__osEPiRawReadIo.o"
|
||||
include "build/src/libultra_boot_O2/osViSwapBuffer.o"
|
||||
include "build/src/libultra_boot_O2/__osEPiRawStartDma.o"
|
||||
include "build/src/libultra/io/si.o"
|
||||
include "build/src/libultra/os/jammesg.o"
|
||||
include "build/src/libultra/os/setthreadpri.o"
|
||||
include "build/src/libultra/os/getthreadpri.o"
|
||||
include "build/src/libultra/io/epirawread.o"
|
||||
include "build/src/libultra/io/viswapbuf.o"
|
||||
include "build/src/libultra/io/epirawdma.o"
|
||||
include "build/asm/bcmp.o"
|
||||
include "build/src/libultra_boot_O1/osGetTime.o"
|
||||
include "build/src/libultra_boot_O1/timerintr.o"
|
||||
include "build/src/libultra/os/gettime.o"
|
||||
include "build/src/libultra/os/timerintr.o"
|
||||
include "build/asm/osGetCount.o"
|
||||
include "build/src/libultra_boot_O1/__osSetGlobalIntMask.o"
|
||||
include "build/src/libultra/os/setglobalintmask.o"
|
||||
include "build/asm/__osSetCompare.o"
|
||||
include "build/asm/bcopy.o"
|
||||
include "build/src/libultra_boot_O1/__osResetGlobalIntMask.o"
|
||||
include "build/src/libultra/os/resetglobalintmask.o"
|
||||
include "build/asm/__osDisableInt.o"
|
||||
include "build/asm/__osRestoreInt.o"
|
||||
include "build/src/libultra_boot_O2/osViModeNtscLan1.o"
|
||||
include "build/src/libultra_boot_O2/osViModeMpalLan1.o"
|
||||
include "build/src/libultra_boot_O2/__osViInit.o"
|
||||
include "build/src/libultra_boot_O2/__osViSwapContext.o"
|
||||
include "build/src/libultra_boot_O2/osPiGetCmdQueue.o"
|
||||
include "build/src/libultra_boot_O2/osEPiReadIo.o"
|
||||
include "build/src/libultra_boot_O2/osViSetSpecialFeatures.o"
|
||||
include "build/src/libultra_boot_O2/osCartRomInit.o"
|
||||
include "build/src/libultra_boot_O2/osViModeFpalLan1.o"
|
||||
include "build/src/libultra/io/vimodentsclan1.o"
|
||||
include "build/src/libultra/io/vimodempallan1.o"
|
||||
include "build/src/libultra/io/vi.o"
|
||||
include "build/src/libultra/io/viswapcontext.o"
|
||||
include "build/src/libultra/io/pigetcmdq.o"
|
||||
include "build/src/libultra/io/epiread.o"
|
||||
include "build/src/libultra/io/visetspecial.o"
|
||||
include "build/src/libultra/io/cartrominit.o"
|
||||
include "build/src/libultra/io/vimodefpallan1.o"
|
||||
include "build/asm/__osSetFpcCsr.o"
|
||||
include "build/asm/__osGetFpcCsr.o"
|
||||
include "build/src/libultra_boot_O2/osEPiWriteIo.o"
|
||||
include "build/src/libultra/io/epiwrite.o"
|
||||
include "build/asm/osMapTLBRdb.o"
|
||||
include "build/src/libultra_boot_O1/osYieldThread.o"
|
||||
include "build/src/libultra/os/yieldthread.o"
|
||||
include "build/asm/__osGetCause.o"
|
||||
include "build/src/libultra_boot_O2/__osEPiRawWriteIo.o"
|
||||
include "build/src/libultra_boot_O2/_Litob.o"
|
||||
include "build/src/libultra_boot_O2/ldiv.o"
|
||||
include "build/src/libultra_boot_O2/_Ldtob.o"
|
||||
include "build/src/libultra/io/epirawwrite.o"
|
||||
include "build/src/libultra/rmon/xlitob.o"
|
||||
include "build/src/libultra/libc/ldiv.o"
|
||||
include "build/src/libultra/rmon/xldtob.o"
|
||||
include "build/src/boot/build.o"
|
||||
include "build/src/libultra_boot_O2/__osSiRawWriteIo.o"
|
||||
include "build/src/libultra_boot_O2/vimgr.o"
|
||||
include "build/src/libultra_boot_O2/__osViGetCurrentContext.o"
|
||||
include "build/src/libultra_boot_O1/osStartThread.o"
|
||||
include "build/src/libultra_boot_O2/osViSetYScale.o"
|
||||
include "build/src/libultra_boot_O2/osViSetXScale.o"
|
||||
include "build/src/libultra_boot_O1/__osSetHWIntrRoutine.o"
|
||||
include "build/src/libultra_boot_O1/__osGetHWIntrRoutine.o"
|
||||
include "build/src/libultra/io/sirawwrite.o"
|
||||
include "build/src/libultra/io/vimgr.o"
|
||||
include "build/src/libultra/io/vigetcurrcontext.o"
|
||||
include "build/src/libultra/os/startthread.o"
|
||||
include "build/src/libultra/io/visetyscale.o"
|
||||
include "build/src/libultra/io/visetxscale.o"
|
||||
include "build/src/libultra/os/sethwintrroutine.o"
|
||||
include "build/src/libultra/os/gethwintrroutine.o"
|
||||
include "build/asm/__osSetWatchLo.o"
|
||||
include "build/data/rsp_boot.text.o"
|
||||
endseg
|
||||
@ -413,8 +413,8 @@ beginseg
|
||||
include "build/src/code/audio_heap.o"
|
||||
include "build/src/code/audio_load.o"
|
||||
include "build/src/code/code_800E4FE0.o"
|
||||
include "build/src/libultra_code_O2/code_800E6840.o"
|
||||
include "build/src/libultra_code_O2/osAiSetNextBuffer.o"
|
||||
include "build/src/code/code_800E6840.o"
|
||||
include "build/src/libultra/io/aisetnextbuf.o"
|
||||
include "build/src/code/audio_playback.o"
|
||||
include "build/src/code/audio_effects.o"
|
||||
include "build/src/code/audio_seqplayer.o"
|
||||
@ -443,71 +443,71 @@ beginseg
|
||||
include "build/src/code/sleep.o"
|
||||
include "build/src/code/jpegutils.o"
|
||||
include "build/src/code/jpegdecoder.o"
|
||||
include "build/src/libultra_code_O2/osPfsFreeBlocks.o"
|
||||
include "build/src/libultra/io/pfsfreeblocks.o"
|
||||
include "build/asm/guScale.o"
|
||||
include "build/src/libultra_code_O2/sinf.o"
|
||||
include "build/src/libultra_code_O2/sins.o"
|
||||
include "build/src/libultra_code_O2/sptask.o"
|
||||
include "build/src/libultra_code_O2/osRumblePak.o"
|
||||
include "build/src/libultra_code_O2/__osSiCreateAccessQueue.o"
|
||||
include "build/src/libultra_code_O2/osContInit.o"
|
||||
include "build/src/libultra_code_O2/osContStartReadData.o"
|
||||
include "build/src/libultra_code_O2/guPerspectiveF.o"
|
||||
include "build/src/libultra_code_O2/__osSpRawStartDma.o"
|
||||
include "build/src/libultra_code_O2/__osSiRawStartDma.o"
|
||||
include "build/src/libultra_code_O2/osSpTaskYield.o"
|
||||
include "build/src/libultra_code_O2/pfsreadwritefile.o"
|
||||
include "build/src/libultra_code_O2/__osPfsGetStatus.o"
|
||||
include "build/src/libultra/gu/sinf.o"
|
||||
include "build/src/libultra/gu/sins.o"
|
||||
include "build/src/libultra/io/sptask.o"
|
||||
include "build/src/libultra/io/motor.o"
|
||||
include "build/src/libultra/io/siacs.o"
|
||||
include "build/src/libultra/io/controller.o"
|
||||
include "build/src/libultra/io/contreaddata.o"
|
||||
include "build/src/libultra/gu/perspective.o"
|
||||
include "build/src/libultra/io/sprawdma.o"
|
||||
include "build/src/libultra/io/sirawdma.o"
|
||||
include "build/src/libultra/io/sptaskyield.o"
|
||||
include "build/src/libultra/io/pfsreadwritefile.o"
|
||||
include "build/src/libultra/io/pfsgetstatus.o"
|
||||
include "build/asm/guMtxIdentF.o"
|
||||
include "build/src/libultra_code_O2/guLookAt.o"
|
||||
include "build/src/libultra_code_O2/pfsallocatefile.o"
|
||||
include "build/src/libultra_code_O1/osStopTimer.o"
|
||||
include "build/src/libultra_code_O2/contpfs.o"
|
||||
include "build/src/libultra/gu/lookat.o"
|
||||
include "build/src/libultra/io/pfsallocatefile.o"
|
||||
include "build/src/libultra/os/stoptimer.o"
|
||||
include "build/src/libultra/io/contpfs.o"
|
||||
include "build/asm/guMtxL2F.o"
|
||||
include "build/src/libultra_code_O2/osPfsFindFile.o"
|
||||
include "build/src/libultra_code_O2/sqrtf.o"
|
||||
include "build/src/libultra_code_O2/osAfterPreNMI.o"
|
||||
include "build/src/libultra_code_O2/contquery.o"
|
||||
include "build/src/libultra_code_O2/guLookAtHilite.o"
|
||||
include "build/src/libultra_code_O2/sp.o"
|
||||
include "build/src/libultra/io/pfsfindfile.o"
|
||||
include "build/src/libultra/gu/sqrtf.o"
|
||||
include "build/src/libultra/os/afterprenmi.o"
|
||||
include "build/src/libultra/io/contquery.o"
|
||||
include "build/src/libultra/gu/lookathil.o"
|
||||
include "build/src/libultra/io/sp.o"
|
||||
include "build/asm/guMtxIdent.o"
|
||||
include "build/src/libultra_code_O2/guPosition.o"
|
||||
include "build/src/libultra_code_O2/osSpTaskYielded.o"
|
||||
include "build/src/libultra_code_O2/rotate.o"
|
||||
include "build/src/libultra_code_O2/osAiSetFrequency.o"
|
||||
include "build/src/libultra_code_O2/__osGetActiveQueue.o"
|
||||
include "build/src/libultra/gu/position.o"
|
||||
include "build/src/libultra/io/sptaskyielded.o"
|
||||
include "build/src/libultra/gu/rotate.o"
|
||||
include "build/src/libultra/io/aisetfreq.o"
|
||||
include "build/src/libultra/os/getactivequeue.o"
|
||||
include "build/asm/guNormalize.o"
|
||||
include "build/src/libultra_code_O2/osDpGetStatus.o"
|
||||
include "build/src/libultra_code_O2/osDpSetStatus.o"
|
||||
include "build/src/libultra_code_O2/osPfsDeleteFile.o"
|
||||
include "build/src/libultra_code_O2/ortho.o"
|
||||
include "build/src/libultra_code_O2/cosf.o"
|
||||
include "build/data/__libm_qnan_f.rodata.o"
|
||||
include "build/src/libultra_code_O2/coss.o"
|
||||
include "build/src/libultra_code_O2/osViSetEvent.o"
|
||||
include "build/src/libultra_code_O2/osPfsIsPlug.o"
|
||||
include "build/src/libultra_code_O2/guS2DInitBg.o"
|
||||
include "build/src/libultra_code_O2/__osPfsSelectBank.o"
|
||||
include "build/src/libultra_code_O2/osContSetCh.o"
|
||||
include "build/src/libultra_code_O2/osPfsFileState.o"
|
||||
include "build/src/libultra_code_O2/pfsinitpak.o"
|
||||
include "build/src/libultra_code_O2/pfschecker.o"
|
||||
include "build/src/libultra_code_O2/osAiGetLength.o"
|
||||
include "build/src/libultra/io/dpgetstat.o"
|
||||
include "build/src/libultra/io/dpsetstat.o"
|
||||
include "build/src/libultra/io/pfsdeletefile.o"
|
||||
include "build/src/libultra/gu/ortho.o"
|
||||
include "build/src/libultra/gu/cosf.o"
|
||||
include "build/asm/libm_vals.o"
|
||||
include "build/src/libultra/gu/coss.o"
|
||||
include "build/src/libultra/io/visetevent.o"
|
||||
include "build/src/libultra/io/pfsisplug.o"
|
||||
include "build/src/libultra/gu/us2dex.o"
|
||||
include "build/src/libultra/io/pfsselectbank.o"
|
||||
include "build/src/libultra/io/contsetch.o"
|
||||
include "build/src/libultra/io/pfsfilestate.o"
|
||||
include "build/src/libultra/io/pfsinitpak.o"
|
||||
include "build/src/libultra/io/pfschecker.o"
|
||||
include "build/src/libultra/io/aigetlen.o"
|
||||
include "build/asm/guTranslate.o"
|
||||
include "build/src/libultra_code_O2/__osContRamWrite.o"
|
||||
include "build/src/libultra_code_O2/__osContRamRead.o"
|
||||
include "build/src/libultra_code_O2/__osContAddressCrc.o"
|
||||
include "build/src/libultra_code_O1/osSetTimer.o"
|
||||
include "build/src/libultra_code_O2/__osSpGetStatus.o"
|
||||
include "build/src/libultra_code_O2/__osSpSetStatus.o"
|
||||
include "build/src/libultra/io/contramwrite.o"
|
||||
include "build/src/libultra/io/contramread.o"
|
||||
include "build/src/libultra/io/crc.o"
|
||||
include "build/src/libultra/os/settimer.o"
|
||||
include "build/src/libultra/io/spgetstat.o"
|
||||
include "build/src/libultra/io/spsetstat.o"
|
||||
include "build/asm/osWritebackDCacheAll.o"
|
||||
include "build/src/libultra_code_O2/__osGetCurrFaultedThread.o"
|
||||
include "build/src/libultra/os/getcurrfaultedthread.o"
|
||||
include "build/asm/guMtxF2L.o"
|
||||
include "build/src/libultra_code_O1/llcvt.o"
|
||||
include "build/src/libultra_code_O2/osViGetCurrentFramebuffer.o"
|
||||
include "build/src/libultra_code_O2/__osSpSetPc.o"
|
||||
include "build/src/libultra_code_O2_g3/sqrt.o"
|
||||
include "build/src/libultra_code_O2_g3/absf.o"
|
||||
include "build/src/libultra/libc/llcvt.o"
|
||||
include "build/src/libultra/io/vigetcurrframebuf.o"
|
||||
include "build/src/libultra/io/spsetpc.o"
|
||||
include "build/src/libultra/libc/sqrt.o"
|
||||
include "build/src/libultra/libc/absf.o"
|
||||
include "build/src/code/code_801067F0.o"
|
||||
include "build/src/code/code_80106860.o"
|
||||
include "build/src/code/code_801068B0.o"
|
||||
|
||||
@ -106,7 +106,7 @@ void AudioHeap_DiscardSequence(s32 seqId) {
|
||||
}
|
||||
|
||||
void AudioHeap_WritebackDCache(void* mem, u32 size) {
|
||||
Audio_osWritebackDCache(mem, size);
|
||||
Audio_WritebackDCache(mem, size);
|
||||
}
|
||||
|
||||
void* AudioHeap_AllocZeroedAttemptExternal(AudioAllocPool* pool, u32 size) {
|
||||
@ -802,7 +802,7 @@ void AudioHeap_Init(void) {
|
||||
s32 temporaryMem;
|
||||
s32 totalMem;
|
||||
s32 wantMisc;
|
||||
u32 intMask;
|
||||
OSIntMask intMask;
|
||||
s32 i;
|
||||
s32 j;
|
||||
s32 pad2;
|
||||
|
||||
@ -868,7 +868,7 @@ void AudioLoad_SyncDma(u32 devAddr, u8* addr, u32 size, s32 medium) {
|
||||
OSIoMesg* ioMesg = &gAudioContext.syncDmaIoMesg;
|
||||
size = ALIGN16(size);
|
||||
|
||||
Audio_osInvalDCache(addr, size);
|
||||
Audio_InvalDCache(addr, size);
|
||||
|
||||
while (true) {
|
||||
if (size < 0x400) {
|
||||
@ -1312,10 +1312,10 @@ void AudioLoad_ProcessSlowLoads(s32 resetStatus) {
|
||||
}
|
||||
|
||||
void AudioLoad_DmaSlowCopy(AudioSlowLoad* slowLoad, s32 size) {
|
||||
Audio_osInvalDCache(slowLoad->curRamAddr, size);
|
||||
Audio_InvalDCache(slowLoad->curRamAddr, size);
|
||||
osCreateMesgQueue(&slowLoad->msgqueue, &slowLoad->msg, 1);
|
||||
AudioLoad_Dma(&slowLoad->ioMesg, 0U, 0, slowLoad->curDevAddr, slowLoad->curRamAddr, size, &slowLoad->msgqueue,
|
||||
slowLoad->medium, "SLOWCOPY");
|
||||
AudioLoad_Dma(&slowLoad->ioMesg, OS_MESG_PRI_NORMAL, 0, slowLoad->curDevAddr, slowLoad->curRamAddr, size,
|
||||
&slowLoad->msgqueue, slowLoad->medium, "SLOWCOPY");
|
||||
}
|
||||
|
||||
void AudioLoad_DmaSlowCopyUnkMedium(s32 devAddr, u8* ramAddr, s32 size, s32 arg3) {
|
||||
@ -1548,7 +1548,7 @@ void AudioLoad_ProcessAsyncLoad(AudioAsyncLoad* asyncLoad, s32 resetStatus) {
|
||||
|
||||
void AudioLoad_AsyncDma(AudioAsyncLoad* asyncLoad, u32 size) {
|
||||
size = ALIGN16(size);
|
||||
Audio_osInvalDCache(asyncLoad->curRamAddr, size);
|
||||
Audio_InvalDCache(asyncLoad->curRamAddr, size);
|
||||
osCreateMesgQueue(&asyncLoad->msgQueue, &asyncLoad->msg, 1);
|
||||
AudioLoad_Dma(&asyncLoad->ioMesg, 0, 0, asyncLoad->curDevAddr, asyncLoad->curRamAddr, size, &asyncLoad->msgQueue,
|
||||
asyncLoad->medium, "BGCOPY");
|
||||
|
||||
@ -55,7 +55,7 @@ void AudioSynth_InitNextRingBuf(s32 chunkLen, s32 bufIndex, s32 reverbIndex) {
|
||||
if (reverb->downsampleRate >= 2) {
|
||||
if (reverb->framesToIgnore == 0) {
|
||||
bufItem = &reverb->items[reverb->curFrame][bufIndex];
|
||||
Audio_osInvalDCache(bufItem->toDownsampleLeft, DEFAULT_LEN_2CH);
|
||||
Audio_InvalDCache(bufItem->toDownsampleLeft, DEFAULT_LEN_2CH);
|
||||
|
||||
for (j = 0, i = 0; i < bufItem->lengthA / 2; j += reverb->downsampleRate, i++) {
|
||||
reverb->leftRingBuf[bufItem->startPos + i] = bufItem->toDownsampleLeft[j];
|
||||
|
||||
@ -1,13 +1,15 @@
|
||||
#include "global.h"
|
||||
|
||||
void Audio_osInvalDCache(void* buf, s32 size) {
|
||||
void Audio_InvalDCache(void* buf, s32 size) {
|
||||
OSIntMask prevMask = osSetIntMask(1);
|
||||
|
||||
osInvalDCache(buf, size);
|
||||
osSetIntMask(prevMask);
|
||||
}
|
||||
|
||||
void Audio_osWritebackDCache(void* buf, s32 size) {
|
||||
void Audio_WritebackDCache(void* buf, s32 size) {
|
||||
OSIntMask prevMask = osSetIntMask(1);
|
||||
|
||||
osWritebackDCache(buf, size);
|
||||
osSetIntMask(prevMask);
|
||||
}
|
||||
@ -1,6 +1,6 @@
|
||||
#include "global.h"
|
||||
|
||||
// memcpy used in __osMalloc.c
|
||||
// memmove used in __osMalloc.c
|
||||
void* func_801068B0(void* dst, void* src, size_t size) {
|
||||
u8* spC = dst;
|
||||
u8* sp8 = src;
|
||||
|
||||
@ -17,7 +17,7 @@ u32 sIrqMgrRetraceCount = 0;
|
||||
#define STATUS_NMI 2
|
||||
|
||||
void IrqMgr_AddClient(IrqMgr* this, IrqMgrClient* c, OSMesgQueue* msgQ) {
|
||||
u32 prevInt;
|
||||
OSIntMask prevInt;
|
||||
|
||||
LogUtils_CheckNullPointer("this", this, "../irqmgr.c", 96);
|
||||
LogUtils_CheckNullPointer("c", c, "../irqmgr.c", 97);
|
||||
@ -43,7 +43,7 @@ void IrqMgr_AddClient(IrqMgr* this, IrqMgrClient* c, OSMesgQueue* msgQ) {
|
||||
void IrqMgr_RemoveClient(IrqMgr* this, IrqMgrClient* c) {
|
||||
IrqMgrClient* iter = this->clients;
|
||||
IrqMgrClient* lastIter = NULL;
|
||||
u32 prevInt;
|
||||
OSIntMask prevInt;
|
||||
|
||||
LogUtils_CheckNullPointer("this", this, "../irqmgr.c", 129);
|
||||
LogUtils_CheckNullPointer("c", c, "../irqmgr.c", 130);
|
||||
|
||||
@ -72,7 +72,7 @@ void PadMgr_RumbleControl(PadMgr* padMgr) {
|
||||
osSyncPrintf("padmgr: %dコン: %s\n", i + 1, "振動パック ぶるぶるぶるぶる");
|
||||
osSyncPrintf(VT_RST);
|
||||
|
||||
if (osSetRumble(&padMgr->pfs[i], temp) != 0) {
|
||||
if (__osMotorAccess(&padMgr->pfs[i], temp) != 0) {
|
||||
padMgr->pakType[i] = 0;
|
||||
osSyncPrintf(VT_FGCOL(YELLOW));
|
||||
// "A communication error has occurred with the vibration pack"
|
||||
@ -94,7 +94,7 @@ void PadMgr_RumbleControl(PadMgr* padMgr) {
|
||||
osSyncPrintf("padmgr: %dコン: %s\n", i + 1, "振動パック 停止");
|
||||
osSyncPrintf(VT_RST);
|
||||
|
||||
if (osSetRumble(&padMgr->pfs[i], 0) != 0) {
|
||||
if (osMotorStop(&padMgr->pfs[i]) != 0) {
|
||||
padMgr->pakType[i] = 0;
|
||||
osSyncPrintf(VT_FGCOL(YELLOW));
|
||||
// "A communication error has occurred with the vibration pack"
|
||||
@ -133,12 +133,12 @@ void PadMgr_RumbleControl(PadMgr* padMgr) {
|
||||
i = frame % 4;
|
||||
|
||||
if (padMgr->ctrlrIsConnected[i] && (padMgr->padStatus[i].status & 1) && (padMgr->pakType[i] != 1)) {
|
||||
var4 = osProbeRumblePak(ctrlrQ, &padMgr->pfs[i], i);
|
||||
var4 = osMotorInit(ctrlrQ, &padMgr->pfs[i], i);
|
||||
|
||||
if (var4 == 0) {
|
||||
padMgr->pakType[i] = 1;
|
||||
osSetRumble(&padMgr->pfs[i], 1);
|
||||
osSetRumble(&padMgr->pfs[i], 0);
|
||||
osMotorStart(&padMgr->pfs[i]);
|
||||
osMotorStop(&padMgr->pfs[i]);
|
||||
osSyncPrintf(VT_FGCOL(YELLOW));
|
||||
// "Recognized vibration pack"
|
||||
osSyncPrintf("padmgr: %dコン: %s\n", i + 1, "振動パックを認識しました");
|
||||
@ -164,7 +164,7 @@ void PadMgr_RumbleStop(PadMgr* padMgr) {
|
||||
OSMesgQueue* ctrlrQ = PadMgr_LockSerialMesgQueue(padMgr);
|
||||
|
||||
for (i = 0; i < 4; i++) {
|
||||
if (osProbeRumblePak(ctrlrQ, &padMgr->pfs[i], i) == 0) {
|
||||
if (osMotorInit(ctrlrQ, &padMgr->pfs[i], i) == 0) {
|
||||
if ((gFaultStruct.msgId == 0) && (padMgr->rumbleOnFrames != 0)) {
|
||||
osSyncPrintf(VT_FGCOL(YELLOW));
|
||||
// "Stop vibration pack"
|
||||
@ -172,7 +172,7 @@ void PadMgr_RumbleStop(PadMgr* padMgr) {
|
||||
osSyncPrintf(VT_RST);
|
||||
}
|
||||
|
||||
osSetRumble(&padMgr->pfs[i], 0);
|
||||
osMotorStop(&padMgr->pfs[i]);
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
@ -3117,7 +3117,8 @@ void Message_Update(GlobalContext* globalCtx) {
|
||||
R_TEXT_CHOICE_YPOS(1) = R_TEXTBOX_Y_TARGET + 32;
|
||||
R_TEXT_CHOICE_YPOS(2) = R_TEXTBOX_Y_TARGET + 44;
|
||||
osSyncPrintf("message->msg_disp_type=%x\n", msgCtx->textBoxProperties & 0xF0);
|
||||
if (msgCtx->textBoxType == TEXTBOX_TYPE_NONE_BOTTOM || msgCtx->textBoxType == TEXTBOX_TYPE_NONE_NO_SHADOW) {
|
||||
if (msgCtx->textBoxType == TEXTBOX_TYPE_NONE_BOTTOM ||
|
||||
msgCtx->textBoxType == TEXTBOX_TYPE_NONE_NO_SHADOW) {
|
||||
msgCtx->msgMode = MSGMODE_TEXT_STARTING;
|
||||
R_TEXTBOX_X = R_TEXTBOX_X_TARGET;
|
||||
R_TEXTBOX_Y = R_TEXTBOX_Y_TARGET;
|
||||
|
||||
@ -23,12 +23,15 @@ void SsSram_Init(u32 addr, u8 handleType, u8 handleDomain, u8 handleLatency, u8
|
||||
sSsSramContext.piHandle.relDuration = handleRelDuration;
|
||||
sSsSramContext.piHandle.domain = handleDomain;
|
||||
sSsSramContext.piHandle.speed = handleSpeed;
|
||||
|
||||
bzero(&sSsSramContext.piHandle.transferInfo, sizeof(__OSTranxInfo));
|
||||
|
||||
prevInt = __osDisableInt();
|
||||
sSsSramContext.piHandle.next = __osPiTable;
|
||||
__osPiTable = &sSsSramContext.piHandle;
|
||||
__osRestoreInt(prevInt);
|
||||
sSsSramContext.ioMesg.hdr.pri = 0;
|
||||
|
||||
sSsSramContext.ioMesg.hdr.pri = OS_MESG_PRI_NORMAL;
|
||||
sSsSramContext.ioMesg.hdr.retQueue = &sSsSramContext.mesgQ;
|
||||
sSsSramContext.ioMesg.devAddr = addr;
|
||||
}
|
||||
@ -48,6 +51,6 @@ void SsSram_Dma(void* dramAddr, size_t size, s32 direction) {
|
||||
|
||||
void SsSram_ReadWrite(u32 addr, void* dramAddr, size_t size, s32 direction) {
|
||||
osSyncPrintf("ssSRAMReadWrite:%08x %08x %08x %d\n", addr, dramAddr, size, direction);
|
||||
SsSram_Init(addr, DEVICE_TYPE_SRAM, 1, 5, 0xD, 2, 0xC, 0);
|
||||
SsSram_Init(addr, DEVICE_TYPE_SRAM, PI_DOMAIN2, 5, 0xD, 2, 0xC, 0);
|
||||
SsSram_Dma(dramAddr, size, direction);
|
||||
}
|
||||
|
||||
@ -43,7 +43,7 @@ void guPositionF(f32 mf[4][4], f32 rot, f32 pitch, f32 yaw, f32 scale, f32 x, f3
|
||||
|
||||
/**
|
||||
* guPosition
|
||||
* Creates a rotational/paralell translation moeling matrix (fixed point)
|
||||
* Creates a rotational/parallel translation modeling matrix (fixed point)
|
||||
*/
|
||||
void guPosition(Mtx* m, f32 rot, f32 pitch, f32 yaw, f32 scale, f32 x, f32 y, f32 z) {
|
||||
f32 mf[4][4];
|
||||
@ -1,5 +1,8 @@
|
||||
#include "global.h"
|
||||
|
||||
//! Note that this is not the same as the original libultra
|
||||
//! osAiSetNextBuffer, see comments in the function
|
||||
|
||||
s32 osAiSetNextBuffer(void* buf, u32 size) {
|
||||
static u8 D_80130500 = false;
|
||||
u32 bufAdjusted = (u32)buf;
|
||||
@ -14,12 +17,15 @@ s32 osAiSetNextBuffer(void* buf, u32 size) {
|
||||
D_80130500 = false;
|
||||
}
|
||||
|
||||
// Originally a call to __osAiDeviceBusy
|
||||
status = HW_REG(AI_STATUS_REG, s32);
|
||||
if (status & AI_STATUS_AI_FULL) {
|
||||
return -1;
|
||||
}
|
||||
|
||||
HW_REG(AI_DRAM_ADDR_REG, u32) = PHYSICAL_TO_VIRTUAL(bufAdjusted);
|
||||
// OS_K0_TO_PHYSICAL replaces osVirtualToPhysical, this replacement
|
||||
// assumes that only KSEG0 addresses are given
|
||||
HW_REG(AI_DRAM_ADDR_REG, u32) = OS_K0_TO_PHYSICAL(bufAdjusted);
|
||||
HW_REG(AI_LEN_REG, u32) = size;
|
||||
return 0;
|
||||
}
|
||||
@ -23,7 +23,7 @@ OSPiHandle* osCartRomInit(void) {
|
||||
D_8000AF10 = 0;
|
||||
__CartRomHandle.type = DEVICE_TYPE_CART;
|
||||
__CartRomHandle.baseAddress = 0xB0000000;
|
||||
__CartRomHandle.domain = 0;
|
||||
__CartRomHandle.domain = PI_DOMAIN1;
|
||||
__CartRomHandle.speed = 0;
|
||||
bzero(&__CartRomHandle.transferInfo, sizeof(__OSTranxInfo));
|
||||
|
||||
@ -61,25 +61,25 @@ void __osDevMgrMain(void* arg) {
|
||||
}
|
||||
} else {
|
||||
switch (ioMesg->hdr.type) {
|
||||
case 11:
|
||||
case OS_MESG_TYPE_DMAREAD:
|
||||
osRecvMesg(arg0->acccessQueue, &sp6C, OS_MESG_BLOCK);
|
||||
phi_s0 = arg0->piDmaCallback(OS_READ, ioMesg->devAddr, ioMesg->dramAddr, ioMesg->size);
|
||||
break;
|
||||
case 12:
|
||||
case OS_MESG_TYPE_DMAWRITE:
|
||||
osRecvMesg(arg0->acccessQueue, &sp6C, OS_MESG_BLOCK);
|
||||
phi_s0 = arg0->piDmaCallback(OS_WRITE, ioMesg->devAddr, ioMesg->dramAddr, ioMesg->size);
|
||||
break;
|
||||
case 15:
|
||||
case OS_MESG_TYPE_EDMAREAD:
|
||||
osRecvMesg(arg0->acccessQueue, &sp6C, OS_MESG_BLOCK);
|
||||
phi_s0 = arg0->epiDmaCallback(ioMesg->piHandle, OS_READ, ioMesg->devAddr, ioMesg->dramAddr,
|
||||
ioMesg->size);
|
||||
break;
|
||||
case 16:
|
||||
case OS_MESG_TYPE_EDMAWRITE:
|
||||
osRecvMesg(arg0->acccessQueue, &sp6C, OS_MESG_BLOCK);
|
||||
phi_s0 = arg0->epiDmaCallback(ioMesg->piHandle, OS_WRITE, ioMesg->devAddr, ioMesg->dramAddr,
|
||||
ioMesg->size);
|
||||
break;
|
||||
case 10:
|
||||
case OS_MESG_TYPE_LOOPBACK:
|
||||
osSendMesg(ioMesg->hdr.retQueue, ioMesg, OS_MESG_NOBLOCK);
|
||||
phi_s0 = -1;
|
||||
break;
|
||||
@ -18,7 +18,7 @@ OSPiHandle* osDriveRomInit(void) {
|
||||
D_8000AC70 = 0;
|
||||
__DriveRomHandle.type = DEVICE_TYPE_BULK;
|
||||
__DriveRomHandle.baseAddress = 0xA6000000;
|
||||
__DriveRomHandle.domain = 0;
|
||||
__DriveRomHandle.domain = PI_DOMAIN1;
|
||||
__DriveRomHandle.speed = 0;
|
||||
bzero(&__DriveRomHandle.transferInfo, sizeof(__OSTranxInfo));
|
||||
|
||||
@ -5,7 +5,7 @@
|
||||
|
||||
OSPifRam osPifBuffers[MAXCONTROLLERS];
|
||||
|
||||
s32 osSetRumble(OSPfs* pfs, u32 vibrate) {
|
||||
s32 __osMotorAccess(OSPfs* pfs, u32 vibrate) {
|
||||
s32 i;
|
||||
s32 ret;
|
||||
u8* buf = (u8*)&osPifBuffers[pfs->channel];
|
||||
@ -45,7 +45,7 @@ s32 osSetRumble(OSPfs* pfs, u32 vibrate) {
|
||||
return ret;
|
||||
}
|
||||
|
||||
void osSetUpMempakWrite(s32 channel, OSPifRam* buf) {
|
||||
void _MakeMotorData(s32 channel, OSPifRam* buf) {
|
||||
u8* bufptr = (u8*)buf;
|
||||
__OSContRamHeader mempakwr;
|
||||
s32 i;
|
||||
@ -68,7 +68,7 @@ void osSetUpMempakWrite(s32 channel, OSPifRam* buf) {
|
||||
*bufptr = 0xFE;
|
||||
}
|
||||
|
||||
s32 osProbeRumblePak(OSMesgQueue* ctrlrqueue, OSPfs* pfs, u32 channel) {
|
||||
s32 osMotorInit(OSMesgQueue* ctrlrqueue, OSPfs* pfs, s32 channel) {
|
||||
s32 ret;
|
||||
u8 sp24[BLOCKSIZE];
|
||||
|
||||
@ -112,7 +112,7 @@ s32 osProbeRumblePak(OSMesgQueue* ctrlrqueue, OSPfs* pfs, u32 channel) {
|
||||
return 0xB;
|
||||
}
|
||||
if ((pfs->status & PFS_MOTOR_INITIALIZED) == 0) {
|
||||
osSetUpMempakWrite(channel, &osPifBuffers[channel]);
|
||||
_MakeMotorData(channel, &osPifBuffers[channel]);
|
||||
}
|
||||
pfs->status = PFS_MOTOR_INITIALIZED;
|
||||
|
||||
@ -1,9 +1,9 @@
|
||||
#include "global.h"
|
||||
|
||||
s32 __osSiRawWriteIo(void* a0, u32 a1) {
|
||||
s32 __osSiRawReadIo(void* devAddr, u32* dst) {
|
||||
if (__osSiDeviceBusy()) {
|
||||
return -1;
|
||||
}
|
||||
HW_REG((u32)a0, u32) = a1;
|
||||
*dst = HW_REG((u32)devAddr, u32);
|
||||
return 0;
|
||||
}
|
||||
@ -1,9 +1,9 @@
|
||||
#include "global.h"
|
||||
|
||||
s32 __osSiRawReadIo(void* a0, u32* a1) {
|
||||
s32 __osSiRawWriteIo(void* devAddr, u32 val) {
|
||||
if (__osSiDeviceBusy()) {
|
||||
return -1;
|
||||
}
|
||||
*a1 = HW_REG((u32)a0, u32);
|
||||
HW_REG((u32)devAddr, u32) = val;
|
||||
return 0;
|
||||
}
|
||||
Some files were not shown because too many files have changed in this diff Show More
Loading…
Reference in New Issue
Block a user