mirror of
https://github.com/n64decomp/perfect_dark.git
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Convert llcvt.c to assembly
This commit is contained in:
Ryan Dwyer
parent
28f678bfee
commit
a617fd62b1
8
Makefile
8
Makefile
@ -340,8 +340,7 @@ ifeq ($(COMPILER), ido)
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MIPS3_C_FILES := \
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src/lib/rng_c.c \
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src/lib/ultra/libc/ll.c \
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src/lib/ultra/libc/llcvt.c
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src/lib/ultra/libc/ll.c
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G_C_FILES := \
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$(shell find src/lib/ultra/audio -name '*.c') \
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@ -378,7 +377,6 @@ ifeq ($(COMPILER), ido)
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src/lib/ultra/io/visetyscale.c \
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src/lib/ultra/io/viswapbuf.c \
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src/lib/ultra/libc/ll.c \
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src/lib/ultra/libc/llcvt.c \
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src/lib/ultra/os/atomic.c \
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src/lib/ultra/os/createmesgqueue.c \
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src/lib/ultra/os/destroythread.c \
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@ -772,9 +770,9 @@ $(B_DIR)/lib/rng_c.o: src/lib/rng_c.c $(ASSETMGR_O_FILES) $(RECOMP_FILES)
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$(CC) -c $(CFLAGS) $(OPT_LVL) -o $@ $<
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tools/patchmips3 $@ || rm $@
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$(B_DIR)/lib/ultra/libc/llcvt.o: src/lib/ultra/libc/llcvt.c $(ASSETMGR_O_FILES) $(RECOMP_FILES)
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$(B_DIR)/lib/ultra/libc/llcvt.o: src/lib/ultra/libc/llcvt.s
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@mkdir -p $(dir $@)
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$(CC) -c $(CFLAGS) $(OPT_LVL) -o $@ $<
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cpp -P -Wno-trigraphs -I include -I include/PR -I src/include $(C_DEFINES) -D_LANGUAGE_ASSEMBLY -D_MIPSEB $< | $(AS) $(ASFLAGS) -o $@
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tools/patchmips3 $@ || rm $@
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$(B_DIR)/lib/ultra/libc/ll.o: src/lib/ultra/libc/ll.c $(ASSETMGR_O_FILES) $(RECOMP_FILES)
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@ -1,285 +0,0 @@
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#include "constants.h"
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#ifdef __sgi
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#if VERSION < VERSION_NTSC_1_0
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long long __d_to_ll(double f)
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{
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return f;
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}
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#endif
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long long __f_to_ll(float f)
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{
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return f;
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}
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#if VERSION < VERSION_NTSC_1_0
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#if MATCHING
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GLOBAL_ASM(
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glabel __d_to_ull
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/* 5ad8: 444ef800 */ cfc1 $t6,$31
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/* 5adc: 24020001 */ addiu $v0,$zero,0x1
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/* 5ae0: 44c2f800 */ ctc1 $v0,$31
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/* 5ae4: 00000000 */ sll $zero,$zero,0x0
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/* 5ae8: 46206125 */ cvt.l.d $f4,$f12
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/* 5aec: 4442f800 */ cfc1 $v0,$31
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/* 5af0: 00000000 */ sll $zero,$zero,0x0
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/* 5af4: 30410004 */ andi $at,$v0,0x4
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/* 5af8: 30420078 */ andi $v0,$v0,0x78
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/* 5afc: 10400014 */ beqz $v0,.NB00005b50
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/* 5b00: 3c0143e0 */ lui $at,0x43e0
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/* 5b04: 44812000 */ mtc1 $at,$f4
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/* 5b08: 24020001 */ addiu $v0,$zero,0x1
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/* 5b0c: 46246101 */ sub.d $f4,$f12,$f4
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/* 5b10: 44c2f800 */ ctc1 $v0,$31
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/* 5b14: 00000000 */ sll $zero,$zero,0x0
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/* 5b18: 46202125 */ cvt.l.d $f4,$f4
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/* 5b1c: 4442f800 */ cfc1 $v0,$31
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/* 5b20: 00000000 */ sll $zero,$zero,0x0
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/* 5b24: 30410004 */ andi $at,$v0,0x4
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/* 5b28: 30420078 */ andi $v0,$v0,0x78
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/* 5b2c: 14400006 */ bnez $v0,.NB00005b48
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/* 5b30: 00000000 */ sll $zero,$zero,0x0
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/* 5b34: 3c0f8000 */ lui $t7,0x8000
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/* 5b38: 000f783c */ dsll32 $t7,$t7,0x0
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/* 5b3c: 44222000 */ dmfc1 $v0,$f4
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/* 5b40: 10000007 */ beqz $zero,.NB00005b60
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/* 5b44: 004f1025 */ or $v0,$v0,$t7
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.NB00005b48:
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/* 5b48: 10000005 */ beqz $zero,.NB00005b60
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/* 5b4c: 2402ffff */ addiu $v0,$zero,-1
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.NB00005b50:
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/* 5b50: 44222000 */ dmfc1 $v0,$f4
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/* 5b54: 00000000 */ sll $zero,$zero,0x0
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/* 5b58: 0440fffb */ bltz $v0,.NB00005b48
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/* 5b5c: 00000000 */ sll $zero,$zero,0x0
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.NB00005b60:
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/* 5b60: 44cef800 */ ctc1 $t6,$31
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/* 5b64: 0002183c */ dsll32 $v1,$v0,0x0
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/* 5b68: 0003183f */ dsra32 $v1,$v1,0x0
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/* 5b6c: 03e00008 */ jr $ra
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/* 5b70: 0002103f */ dsra32 $v0,$v0,0x0
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);
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#else
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unsigned long long __d_to_ull(double d)
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{
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return d;
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}
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#endif
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#endif
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#if MATCHING
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GLOBAL_ASM(
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glabel __f_to_ull
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/* 5a7c: 444ef800 */ cfc1 $t6,$31
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/* 5a80: 24020001 */ addiu $v0,$zero,0x1
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/* 5a84: 44c2f800 */ ctc1 $v0,$31
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/* 5a88: 00000000 */ nop
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/* 5a8c: 46006125 */ cvt.l.s $f4,$f12
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/* 5a90: 4442f800 */ cfc1 $v0,$31
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/* 5a94: 00000000 */ nop
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/* 5a98: 30410004 */ andi $at,$v0,0x4
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/* 5a9c: 30420078 */ andi $v0,$v0,0x78
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/* 5aa0: 10400014 */ beqz $v0,.L00005af4
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/* 5aa4: 3c015f00 */ lui $at,0x5f00
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/* 5aa8: 44812000 */ mtc1 $at,$f4
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/* 5aac: 24020001 */ addiu $v0,$zero,0x1
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/* 5ab0: 46046101 */ sub.s $f4,$f12,$f4
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/* 5ab4: 44c2f800 */ ctc1 $v0,$31
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/* 5ab8: 00000000 */ nop
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/* 5abc: 46002125 */ cvt.l.s $f4,$f4
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/* 5ac0: 4442f800 */ cfc1 $v0,$31
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/* 5ac4: 00000000 */ nop
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/* 5ac8: 30410004 */ andi $at,$v0,0x4
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/* 5acc: 30420078 */ andi $v0,$v0,0x78
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/* 5ad0: 14400006 */ bnez $v0,.L00005aec
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/* 5ad4: 00000000 */ nop
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/* 5ad8: 3c0f8000 */ lui $t7,0x8000
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/* 5adc: 000f783c */ dsll32 $t7,$t7,0x0
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/* 5ae0: 44222000 */ dmfc1 $v0,$f4
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/* 5ae4: 10000007 */ b .L00005b04
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/* 5ae8: 004f1025 */ or $v0,$v0,$t7
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.L00005aec:
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/* 5aec: 10000005 */ b .L00005b04
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/* 5af0: 2402ffff */ addiu $v0,$zero,-1
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.L00005af4:
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/* 5af4: 44222000 */ dmfc1 $v0,$f4
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/* 5af8: 00000000 */ nop
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/* 5afc: 0440fffb */ bltz $v0,.L00005aec
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/* 5b00: 00000000 */ nop
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.L00005b04:
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/* 5b04: 44cef800 */ ctc1 $t6,$31
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/* 5b08: 0002183c */ dsll32 $v1,$v0,0x0
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/* 5b0c: 0003183f */ dsra32 $v1,$v1,0x0
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/* 5b10: 03e00008 */ jr $ra
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/* 5b14: 0002103f */ dsra32 $v0,$v0,0x0
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);
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#else
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// Mismatch: Goal loads 0x80000000 then shifts it left by 32,
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// while the below stores it in .rodata and loads it.
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unsigned long long __f_to_ull(float f)
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{
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return f;
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}
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#endif
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double __ll_to_d(long long s)
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{
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return s;
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}
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#if VERSION < VERSION_NTSC_1_0
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float __ll_to_f(long long s)
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{
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return s;
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}
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#endif
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#if VERSION < VERSION_NTSC_1_0
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#if MATCHING
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GLOBAL_ASM(
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glabel __ull_to_d
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/* 5c40: afa40000 */ sw $a0,0x0($sp)
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/* 5c44: afa50004 */ sw $a1,0x4($sp)
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/* 5c48: dfae0000 */ ld $t6,0x0($sp)
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/* 5c4c: 44ae2000 */ dmtc1 $t6,$f4
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/* 5c50: 05c10005 */ bgez $t6,.NB00005c68
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/* 5c54: 46a02021 */ cvt.d.l $f0,$f4
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/* 5c58: 3c0141f0 */ lui $at,0x41f0
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/* 5c5c: 44813000 */ mtc1 $at,$f6
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/* 5c60: 00000000 */ sll $zero,$zero,0x0
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/* 5c64: 46260000 */ add.d $f0,$f0,$f6
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.NB00005c68:
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/* 5c68: 03e00008 */ jr $ra
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/* 5c6c: 00000000 */ sll $zero,$zero,0x0
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);
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#else
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double __ull_to_d(unsigned long long u)
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{
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return u;
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}
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#endif
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#endif
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float __ull_to_f(unsigned long long u)
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{
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return u;
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}
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#else
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// gcc
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/**
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* IDO's __f_to_ll is gcc's __fixsfdi
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* IDO's __f_to_ull is gcc's __fixunssfdi
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* IDO's __ll_to_d is gcc's __floatdidf
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* IDO's __ull_to_f is gcc's __floatundisf
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*/
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__asm__(" \n\
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.set push \n\
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.set noat \n\
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.set noreorder \n\
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.set gp=64 \n\
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\n\
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.global __fixsfdi \n\
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__fixsfdi: \n\
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.type __fixsfdi, @function \n\
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.ent __fixsfdi \n\
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trunc.l.s $f4, $f12 \n\
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dmfc1 $v0, $f4 \n\
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nop \n\
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dsll32 $v1, $v0, 0 \n\
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dsra32 $v1, $v1, 0 \n\
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jr $ra \n\
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dsra32 $v0, $v0, 0 \n\
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.end __fixsfdi \n\
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.size __fixsfdi, . - __fixsfdi \n\
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\n\
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.global __fixunssfdi \n\
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__fixunssfdi: \n\
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.type __fixunssfdi, @function \n\
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.ent __fixunssfdi \n\
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cfc1 $t6, $31 \n\
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addiu $v0, $zero, 1 \n\
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ctc1 $v0, $31 \n\
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nop \n\
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cvt.l.s $f4, $f12 \n\
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cfc1 $v0, $31 \n\
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nop \n\
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andi $at, $v0, 4 \n\
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andi $v0, $v0, 0x78 \n\
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beqz $v0, 2f \n\
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lui $at, 0x5f00 \n\
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mtc1 $at, $f4 \n\
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addiu $v0, $zero, 1 \n\
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sub.s $f4, $f12, $f4 \n\
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ctc1 $v0, $31 \n\
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nop \n\
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cvt.l.s $f4, $f4 \n\
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cfc1 $v0, $31 \n\
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nop \n\
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andi $at, $v0, 4 \n\
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andi $v0, $v0, 0x78 \n\
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bnez $v0, 1f \n\
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nop \n\
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lui $t7, 0x8000 \n\
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dsll32 $t7, $t7, 0 \n\
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dmfc1 $v0, $f4 \n\
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b 3f \n\
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or $v0, $v0, $t7 \n\
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1: \n\
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b 3f \n\
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addiu $v0, $zero, -1 \n\
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2: \n\
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dmfc1 $v0, $f4 \n\
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nop \n\
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bltz $v0, 1b \n\
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nop \n\
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3: \n\
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ctc1 $t6, $31 \n\
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dsll32 $v1, $v0, 0 \n\
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dsra32 $v1, $v1, 0 \n\
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jr $ra \n\
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dsra32 $v0, $v0, 0 \n\
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.end __fixunssfdi \n\
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.size __fixunssfdi, . - __fixunssfdi \n\
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\n\
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.global __floatdidf \n\
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__floatdidf: \n\
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.type __floatdidf, @function \n\
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.ent __floatdidf \n\
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sw $a0, 0($sp) \n\
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sw $a1, 4($sp) \n\
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ld $t6, 0($sp) \n\
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dmtc1 $t6, $f4 \n\
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jr $ra \n\
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cvt.d.l $f0, $f4 \n\
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.end __floatdidf \n\
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.size __floatdidf, . - __floatdidf \n\
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\n\
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.global __floatundisf \n\
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__floatundisf: \n\
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.type __floatundisf, @function \n\
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.ent __floatundisf \n\
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sw $a0, 0($sp) \n\
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sw $a1, 4($sp) \n\
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ld $t6, 0($sp) \n\
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dmtc1 $t6, $f4 \n\
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bgez $t6, 1f \n\
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cvt.s.l $f0, $f4 \n\
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lui $at, 0x4f80 \n\
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mtc1 $at, $f6 \n\
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nop \n\
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add.s $f0, $f0, $f6 \n\
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1: \n\
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jr $ra \n\
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nop \n\
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.end __floatundisf \n\
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.size __floatundisf, . - __floatundisf \n\
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\n\
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.set pop \n\
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\n");
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#endif
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214
src/lib/ultra/libc/llcvt.s
Normal file
214
src/lib/ultra/libc/llcvt.s
Normal file
@ -0,0 +1,214 @@
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#include "asm_helper.h"
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#include "macros.inc"
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#include "versions.h"
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/**
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* Rare almost certainly compiled a C version of this file
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* then patched the compiled assembly.
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*
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* __f_to_ull:
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*
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* The C version loads 0x8000000000000000 from rodata while Rare's does
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* lui 0x8000 and shifts left by 32. This is an optimisation that Rare made.
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*
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* __ull_to_d:
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*
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* Rare had to ASM patch some instructions due to Rare's use of the FPU's
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* native register mode (FR=1), which the assembler assumes is off.
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* However, Rare patched these wrong, and as a result calling __ull_to_d with
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* very large numbers can cause a crash. This function is never called though
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* and only exists in the beta version.
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*
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* __d_to_ull:
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*
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* This function contains both of the above. Like __ull_to_d, it is also
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* patched incorrectly and can cause a crash. It was also not used and only
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* exists in the beta version.
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*/
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.set noat
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.set noreorder
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.set gp=64
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.text
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#if VERSION < VERSION_NTSC_1_0
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glabel __d_to_ll
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trunc.l.d $f4, $f12
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dmfc1 $v0, $f4
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nop
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dsll32 $v1, $v0, 0
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dsra32 $v1, $v1, 0
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jr $ra
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dsra32 $v0, $v0, 0
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#endif
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glabel __f_to_ll
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glabel __fixsfdi
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trunc.l.s $f4, $f12
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dmfc1 $v0, $f4
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nop
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dsll32 $v1, $v0, 0
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dsra32 $v1, $v1, 0
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jr $ra
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dsra32 $v0, $v0, 0
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#if VERSION < VERSION_NTSC_1_0
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glabel __d_to_ull
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cfc1 $t6, $31
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li $v0, 1
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ctc1 $v0, $31
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nop
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cvt.l.d $f4, $f12
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cfc1 $v0, $31
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nop
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andi $at, $v0, 4
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andi $v0, $v0, 0x78
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beqz $v0, .NB00005b50
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# Same @bug as in __ull_to_d
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lui $at, 0x43e0
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mtc1 $at, $f4
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li $v0, 1
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sub.d $f4, $f12, $f4
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ctc1 $v0, $31
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nop
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cvt.l.d $f4, $f4
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cfc1 $v0, $31
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nop
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andi $at, $v0, 4
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andi $v0, $v0, 0x78
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bnez $v0, .NB00005b48
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nop
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lui $t7, 0x8000
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dsll32 $t7, $t7, 0
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dmfc1 $v0, $f4
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beqz $zero, .NB00005b60
|
||||
or $v0, $v0, $t7
|
||||
.NB00005b48:
|
||||
beqz $zero, .NB00005b60
|
||||
li $v0, -1
|
||||
.NB00005b50:
|
||||
dmfc1 $v0, $f4
|
||||
nop
|
||||
bltz $v0, .NB00005b48
|
||||
nop
|
||||
.NB00005b60:
|
||||
ctc1 $t6, $31
|
||||
dsll32 $v1, $v0, 0
|
||||
dsra32 $v1, $v1, 0
|
||||
jr $ra
|
||||
dsra32 $v0, $v0, 0
|
||||
#endif
|
||||
|
||||
glabel __f_to_ull
|
||||
glabel __fixunssfdi
|
||||
cfc1 $t6, $31
|
||||
li $v0, 1
|
||||
ctc1 $v0, $31
|
||||
nop
|
||||
cvt.l.s $f4, $f12
|
||||
cfc1 $v0, $31
|
||||
nop
|
||||
andi $at, $v0, 4
|
||||
andi $v0, $v0, 0x78
|
||||
beqz $v0, .L00005af4
|
||||
lui $at, 0x5f00
|
||||
mtc1 $at, $f4
|
||||
li $v0, 1
|
||||
sub.s $f4, $f12, $f4
|
||||
ctc1 $v0, $31
|
||||
nop
|
||||
cvt.l.s $f4, $f4
|
||||
cfc1 $v0, $31
|
||||
nop
|
||||
andi $at, $v0, 4
|
||||
andi $v0, $v0, 0x78
|
||||
bnez $v0, .L00005aec
|
||||
nop
|
||||
lui $t7, 0x8000
|
||||
dsll32 $t7, $t7, 0
|
||||
dmfc1 $v0, $f4
|
||||
b .L00005b04
|
||||
or $v0, $v0, $t7
|
||||
.L00005aec:
|
||||
b .L00005b04
|
||||
li $v0, -1
|
||||
.L00005af4:
|
||||
dmfc1 $v0, $f4
|
||||
nop
|
||||
bltz $v0, .L00005aec
|
||||
nop
|
||||
.L00005b04:
|
||||
ctc1 $t6, $31
|
||||
dsll32 $v1, $v0, 0
|
||||
dsra32 $v1, $v1, 0
|
||||
jr $ra
|
||||
dsra32 $v0, $v0, 0
|
||||
|
||||
glabel __ll_to_d
|
||||
glabel __floatdidf
|
||||
sw $a0, 0($sp)
|
||||
sw $a1, 4($sp)
|
||||
ld $t6, 0($sp)
|
||||
dmtc1 $t6, $f4
|
||||
jr $ra
|
||||
cvt.d.l $f0, $f4
|
||||
|
||||
#if VERSION < VERSION_NTSC_1_0
|
||||
glabel __ll_to_f
|
||||
sw $a0, 0($sp)
|
||||
sw $a1, 4($sp)
|
||||
ld $t6, 0($sp)
|
||||
dmtc1 $t6, $f4
|
||||
jr $ra
|
||||
cvt.s.l $f0, $f4
|
||||
#endif
|
||||
|
||||
#if VERSION < VERSION_NTSC_1_0
|
||||
glabel __ull_to_d
|
||||
sw $a0, 0($sp)
|
||||
sw $a1, 4($sp)
|
||||
ld $t6, 0($sp)
|
||||
dmtc1 $t6, $f4
|
||||
bgez $t6, .NB00005c68
|
||||
cvt.d.l $f0, $f4
|
||||
|
||||
# IDO emits:
|
||||
#
|
||||
# lui $at, 0x41f0
|
||||
# mtc1 $at, $f7
|
||||
# mtc1 $zero, $f6
|
||||
#
|
||||
# ...which is correct when FR=0. $f7 is the upper half of the 64-bit register.
|
||||
#
|
||||
# @bug: Rare patched this to account for FR=1, but did it incorrectly and
|
||||
# loaded the immediate into the lower half of the register.
|
||||
# They should have used dmtc1 to set the value for the entire $f6 register.
|
||||
|
||||
lui $at, 0x41f0
|
||||
mtc1 $at, $f6
|
||||
|
||||
nop
|
||||
add.d $f0, $f0, $f6
|
||||
.NB00005c68:
|
||||
jr $ra
|
||||
nop
|
||||
#endif
|
||||
|
||||
glabel __ull_to_f
|
||||
glabel __floatundisf
|
||||
sw $a0, 0($sp)
|
||||
sw $a1, 4($sp)
|
||||
ld $t6, 0($sp)
|
||||
dmtc1 $t6, $f4
|
||||
bgez $t6, .end
|
||||
cvt.s.l $f0, $f4
|
||||
lui $at, 0x4f80
|
||||
mtc1 $at, $f6
|
||||
nop
|
||||
add.s $f0, $f0, $f6
|
||||
.end:
|
||||
jr $ra
|
||||
nop
|
||||
Loading…
Reference in New Issue
Block a user