mirror of
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Convert osMapTLBRdb to ASM
This commit is contained in:
Ryan Dwyer
parent
96eb2d073b
commit
e967f581c2
704
src/include/PR/sys/asm.h
Executable file
704
src/include/PR/sys/asm.h
Executable file
@ -0,0 +1,704 @@
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/**************************************************************************
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* *
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* Copyright (C) 1990, Silicon Graphics, Inc. *
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* *
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* These coded instructions, statements, and computer programs contain *
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* unpublished proprietary information of Silicon Graphics, Inc., and *
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* are protected by Federal copyright law. They may not be disclosed *
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* to third parties or copied or duplicated in any form, in whole or *
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* in part, without the prior written consent of Silicon Graphics, Inc. *
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* *
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**************************************************************************/
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/*
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* Copyright 1985 by MIPS Computer Systems, Inc.
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*/
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#ifndef __SYS_ASM_H__
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#define __SYS_ASM_H__
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#ident "$Revision: 3.33 $"
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#include "sgidefs.h"
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/*
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* asm.h -- cpp definitions for assembler files
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*/
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/*
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* Notes on putting entry pt and frame info into symbol table for debuggers
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*
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* .ent name,lex-level # name is entry pt, lex-level is 0 for c
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* name: # actual entry point
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* .frame fp,framesize,saved_pc_reg
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* # fp -- register which is pointer to base
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* # of previous frame, debuggers are special
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* # cased if "sp" to add "framesize"
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* # (sp is usually used)
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* # framesize -- size of frame
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* # the expression:
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* # new_sp + framesize == old_sp
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* # should be true
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* # saved_pc_reg -- either a register which
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* # contains callers pc or $0, if $0
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* # saved pc is assumed to be in
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* # (fp)+framesize-4
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*
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* Notes regarding multiple entry points:
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* LEAF is used when including the profiling header is appropriate
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* XLEAF is used when the profiling header is in appropriate (e.g.
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* when a entry point is known by multiple names, the profiling call
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* should appear only once.) The correct ordering of ENTRY/XENTRY in this
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* case is:
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* LEAF(copyseg) # declare globl and emit profiling code
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* XLEAF(copypage) # declare globl and alternate entry
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*/
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/*
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* LEAF -- declare leaf routine
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*/
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#define LEAF(x) \
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.globl x; \
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.ent x,0; \
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x:; \
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.frame sp,0,ra
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/*
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* XLEAF -- declare alternate entry to leaf routine
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*/
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#define XLEAF(x) \
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.globl x; \
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.aent x,0; \
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x:
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/*
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* VECTOR -- declare exception routine entry
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*/
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#if _K32U32
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#define VECTOR(x, regmask) \
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.globl x; \
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.ent x,0; \
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x:; \
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.frame sp,EF_SIZE,$0; \
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.mask +(regmask)|M_EXCFRM,-(EF_SIZE-(EF_RA))
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#else
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#define VECTOR(x, regmask) \
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.globl x; \
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.ent x,0; \
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x:; \
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.frame sp,EF_SIZE,$0; \
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.mask +(regmask)|M_EXCFRM,-(EF_SIZE-(EF_RA+4))
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#endif
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/*
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* NESTED -- declare nested routine entry point
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*/
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#define NESTED(x, fsize, rpc) \
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.globl x; \
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.ent x,0; \
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x:; \
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.frame sp,fsize, rpc
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/*
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* XNESTED -- declare alternate entry point to nested routine
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*/
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#define XNESTED(x) \
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.globl x; \
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.aent x,0; \
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x:
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/*
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* END -- mark end of procedure
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*/
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#define END(proc) \
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.end proc
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/*
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* IMPORT -- import external symbol
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*/
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#define IMPORT(sym, size) \
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.extern sym,size
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/*
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* ABS -- declare absolute symbol
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*/
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#define ABS(x, y) \
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.globl x; \
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x = y
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/*
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* EXPORT -- export definition of symbol
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*/
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#define EXPORT(x) \
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.globl x; \
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x:
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/*
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* BSS -- allocate space in bss
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*/
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#define BSS(x,y) \
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.comm x,y
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/*
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* LBSS -- allocate static space in bss
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*/
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#define LBSS(x,y) \
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.lcomm x,y
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/*
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* Macros for writing PIC asm code
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*/
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#ifdef PIC
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#define PICOPT .option pic2
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/*
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* Set gp when at 1st instruction
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*/
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#define SETUP_GP \
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.set noreorder; \
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.cpload t9; \
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.set reorder
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/*
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* Set gp when not at 1st instruction
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*/
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#define SETUP_GPX(r) \
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.set noreorder; \
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move r, ra; /* save old ra */ \
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bal 10f; /* find addr of cpload */\
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nop; \
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10: \
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.cpload ra; \
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move ra, r; \
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.set reorder;
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#define SAVE_GP(x) \
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.cprestore x; /* save gp trigger t9/jalr conversion */
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#else /* PIC */
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#define PICOPT
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#define SETUP_GP
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#define SETUP_GPX(r)
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#define SAVE_GP(x)
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#endif /* PIC */
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/*
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* Stack Frame Definitions
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*/
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#if (_MIPS_SIM == _MIPS_SIM_ABI32)
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#define NARGSAVE 4 /* space for 4 arg regs must be allocated */
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#define ALSZ 7 /* align on 8 byte boundary */
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#define ALMASK ~7
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#endif
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#if (_MIPS_SIM == _MIPS_SIM_ABI64)
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#define NARGSAVE 0 /* no caller responsibilities */
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#define ALSZ 15 /* align on 16 byte boundary */
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#define ALMASK ~0xf
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#endif
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#if _KERNEL
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/* Round the size of a stack frame to fit compiler conventions. */
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#define FRAMESZ(size) (((size)+ALSZ) & ALMASK)
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#endif
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#if (_MIPS_ISA == _MIPS_ISA_MIPS1 || _MIPS_ISA == _MIPS_ISA_MIPS2)
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#define SZREG 4
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#endif
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#if (_MIPS_ISA == _MIPS_ISA_MIPS3 || _MIPS_ISA == _MIPS_ISA_MIPS4)
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#define SZREG 8
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#endif
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/*
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* The following macros reserve the usage of the local label '9'
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* By convention the caller should put the return addr in a2
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* so that the stack backtrace can trace from a leaf
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*/
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#if defined(STANDALONE) || defined(LOCORE)
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#define PANIC(msg) \
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sw zero,waittime; \
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la a0,9f; \
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jal panic; \
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MSG(msg)
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#define PRINTF(msg) \
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la a0,9f; \
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jal printf; \
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MSG(msg)
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#else /* the kernel */
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#define PANIC(msg) \
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li a0,CE_PANIC; \
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la a1,9f; \
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jal cmn_err; \
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MSG(msg)
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#define SPPANIC(msg) \
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/* make sure a good frame */\
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lw sp,VPDA_LBOOTSTACK(zero); \
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li a0,CE_PANIC; \
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la a1,9f; \
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jal cmn_err; \
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MSG(msg)
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#define ASMASSFAIL(msg) \
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la a0,9f; \
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la a1,lmsg; \
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move a2,zero; \
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j assfail; \
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MSG(msg)
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#define PRINTF(msg) \
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la a0,9f; \
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jal dprintf; \
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MSG(msg)
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#endif /* defined(STANDALONE) || defined(LOCORE) */
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#define MSG(msg) \
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.data; \
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9: .asciiz msg; \
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.text
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#define SYSMAP(mname, vname, page, len) \
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.globl mname; \
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mname: \
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.space len*4; \
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.globl vname; \
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vname = ((page)*NBPG)
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#if !defined(_MIPSEB) && !defined(_MIPSEL)
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.error Must define either _MIPSEB or _MIPSEL
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#endif
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#if defined(_MIPSEB) && defined(_MIPSEL)
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.error Only one of _MIPSEB and _MIPSEL may be defined
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#endif
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/*
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* The following macros deal with the coprocessor 0 scheduling
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* hazards, which are different for the R3000 and R4000.
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* The first digit in the name refers to the number
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* of NOPs in the R2000/R3000 case, while the second digit
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* refers to the number of NOPs in the R4000 case.
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* NOTE: For now use R4000 values for TFP too. This at least
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* lets us make the kernel.
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*/
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#if R4000
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#define NOP_0_1 nop
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#define NOP_0_2 nop; nop
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#define NOP_0_3 nop; nop; nop
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#define NOP_0_4 nop; nop; nop; nop
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#define NOP_1_0
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#define NOP_1_1 nop
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#define NOP_1_2 nop; nop
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#define NOP_1_3 nop; nop; nop
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#define NOP_1_4 nop; nop; nop; nop
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#endif
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#if TFP
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#define NOP_0_1
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#define NOP_0_2
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#define NOP_0_3
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#define NOP_0_4
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#define NOP_1_0
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#define NOP_1_1 NOP_SSNOP
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#define NOP_1_2 NOP_SSNOP
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#define NOP_1_3 NOP_SSNOP
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#define NOP_1_4 NOP_SSNOP
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/* TFP has the following kinds of nops:
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*
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* NOP_NOP regular old nop -- takes a dispatch slot, but another
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* integer instruction could be issued with it. But since
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* TFP has only one shifter, two consecutive NOP_NOPs would
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* go in separate cycles
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* NOP_SSNOP nop which breaks superscalar dispatch. Will be the last
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* instruction issued in a cycle. Instruction following
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* will be first instruction issued in next cycle.
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* NOP_NADA more than one of these can be scheduled per cycle
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* since it does not use the shifter
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*/
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#define NOP_NOP sll zero,zero,0
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#define NOP_SSNOP sll zero,zero,1
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#define NOP_NADA addu zero,zero,zero
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/*
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* The following hazards are intended to be the maximum needed so that we
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* do not have to worry about the instructions which follow. You may make
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* use of the actual restrictions in order to optimize the code.
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*
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* Theoretically, NOP_MFC1_HAZ and NOP_MTC1_HAZ should not be needed but they
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* are here just in case.
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*
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* NOP_MFC0_HAZ hazard after loading from C0
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* NOP_MTC0_HAZ hazard after storing to C0
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* NOP_ERET_HAZ hazard before eret after storing C0 registers
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* NOP_COM_HAZ hazard following a COM operation -- TLBW, TLBR, etc.
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* NOP_MFC1_HAZ hazard after loading from C1
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* NOP_MTC1_HAZ hazard after storing to C1
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*
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* Actual restrictions:
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* MFC0
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* - two dmfc0 should not be executed in same cycle
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* - a dmfc0 should not be issued in cycle following a dmtc0
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* MTC0
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* - in cycle after dmtc0 VAddr a COM will not correctly execute
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* - in cycle after dmtc0 status a COM will not correctly execute
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* - in same cycle as dmtc0 TLBSet a COM will not correctly execute
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* - integer store should not be execute in same cycle as dmtc0 VAddr
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* - two dmtc0 should not be executed in the same cycle
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* - a dmfc0 should not be issued in cycle following a dmtc0
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*
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* - there should be three SSNOPs following a MTC0 which
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* is enabling/disabling interrupts in the SR before new mask is
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* effective
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* - there should be three SSNOPs between a MTC0 which enables a CU
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* field (like the FP) before issuing an instruction which uses the
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* the FP.
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* COM
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* - 2 cycles after a COM a memory instruction will not execute properly
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* - a TLBR/DCTR followed by a dmfc0 of EntryHi/EntryLo/DCache should
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* leave two cycles between TLBR and dmfc0
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*
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* Additional restriction found executing kernel on RTL simulator:
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*--------------------------------------------------------------------------
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* jr r31
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* dmtc0 r2,sr
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* The jr happens to jump to 0x801b9204. However, the jal didn't store the
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* proper value (pc + 8) into r31.
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* The reason for this behavior is that mtc0's require an internal bus
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* (MiscBus to be specific), in the W cycle. However, the jal also requires
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* the MiscBus in its E cycle. Thus, the mux select lines for selecting
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* the data to go into the GPR was incorrect.
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* To make sure something like this won't occur again, it's probably a good
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* idea not to have mtc0's in the delay slot, unless you are sure that the
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* target quadword of instructions won't cause this internal bus collision.
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*--------------------------------------------------------------------------
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*/
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#define NOP_MFC0_HAZ NOP_SSNOP
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#define NOP_MTC0_HAZ NOP_SSNOP; NOP_SSNOP; NOP_SSNOP; NOP_SSNOP
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#define NOP_ERET_HAZ
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#define NOP_COM_HAZ NOP_SSNOP; NOP_SSNOP; NOP_SSNOP; NOP_SSNOP
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/*
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* The NOP_MFC1_HAZ and NOP_MTC1_HAZ are here only due to paranoia.
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* I am also defining DMFC1 and DMTC1 which use these macros (in ip21prom.h).
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* All this will exist until there is established confidence in FPU.
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*/
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#define NOP_MFC1_HAZ NOP_SSNOP; NOP_SSNOP; NOP_SSNOP; NOP_SSNOP
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#define NOP_MTC1_HAZ NOP_SSNOP; NOP_SSNOP; NOP_SSNOP; NOP_SSNOP
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#endif
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#if R3000
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#define NOP_0_1
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#define NOP_0_2
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#define NOP_0_3
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#define NOP_0_4
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#define NOP_1_0 nop
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#define NOP_1_1 nop
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#define NOP_1_2 nop
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#define NOP_1_3 nop
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#define NOP_1_4 nop
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#endif
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/*
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* register mask bit definitions
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*/
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#define M_EXCFRM 0x00000001
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#define M_AT 0x00000002
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#define M_V0 0x00000004
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#define M_V1 0x00000008
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#define M_A0 0x00000010
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#define M_A1 0x00000020
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#define M_A2 0x00000040
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#define M_A3 0x00000080
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#define M_T0 0x00000100
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#define M_T1 0x00000200
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#define M_T2 0x00000400
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#define M_T3 0x00000800
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#define M_T4 0x00001000
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||||
#define M_T5 0x00002000
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#define M_T6 0x00004000
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#define M_T7 0x00008000
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#define M_S0 0x00010000
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#define M_S1 0x00020000
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#define M_S2 0x00040000
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#define M_S3 0x00080000
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#define M_S4 0x00100000
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#define M_S5 0x00200000
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#define M_S6 0x00400000
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#define M_S7 0x00800000
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#define M_T8 0x01000000
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#define M_T9 0x02000000
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#define M_K0 0x04000000
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#define M_K1 0x08000000
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#define M_GP 0x10000000
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#define M_SP 0x20000000
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#define M_FP 0x40000000
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#define M_RA 0x80000000
|
||||
|
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|
||||
/*
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||||
* Macros for dealing with 64/32 bit asm files
|
||||
*/
|
||||
|
||||
/*
|
||||
* Basic register save and restore
|
||||
*/
|
||||
#if (_MIPS_ISA == _MIPS_ISA_MIPS1 || _MIPS_ISA == _MIPS_ISA_MIPS2)
|
||||
#define REG_L lw
|
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#define REG_S sw
|
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#endif
|
||||
|
||||
#if (_MIPS_ISA == _MIPS_ISA_MIPS3 || _MIPS_ISA == _MIPS_ISA_MIPS4)
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#define REG_L ld
|
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#define REG_S sd
|
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#endif
|
||||
|
||||
#if (_MIPS_SZINT == 32)
|
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#define INT_L lw
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||||
#define INT_S sw
|
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#define INT_LLEFT lwl /* load left */
|
||||
#define INT_SLEFT swl /* store left */
|
||||
#define INT_LRIGHT lwr /* load right */
|
||||
#define INT_SRIGHT swr /* store right */
|
||||
#define INT_ADD add
|
||||
#define INT_ADDI addi
|
||||
#define INT_ADDIU addiu
|
||||
#define INT_ADDU addu
|
||||
#define INT_SUB sub
|
||||
#define INT_SUBI subi
|
||||
#define INT_SUBIU subiu
|
||||
#define INT_SUBU subu
|
||||
#define INT_SLL sll
|
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#define INT_SRL srl
|
||||
#define INT_SRA sra
|
||||
#define INT_SLLV sllv
|
||||
#define INT_SRLV srlv
|
||||
#define INT_SRAV srav
|
||||
#define INT_LL ll
|
||||
#define INT_SC sc
|
||||
#endif /* _MIPS_SZINT == 32 */
|
||||
|
||||
#if (_MIPS_SZINT == 64)
|
||||
#define INT_L ld
|
||||
#define INT_S sd
|
||||
#define INT_LLEFT ldl /* load left */
|
||||
#define INT_SLEFT sdl /* store left */
|
||||
#define INT_LRIGHT ldr /* load right */
|
||||
#define INT_SRIGHT sdr /* store right */
|
||||
#define INT_ADD dadd
|
||||
#define INT_ADDI daddi
|
||||
#define INT_ADDIU daddiu
|
||||
#define INT_ADDU daddu
|
||||
#define INT_SUB dsub
|
||||
#define INT_SUBI dsubi
|
||||
#define INT_SUBIU dsubiu
|
||||
#define INT_SUBU dsubu
|
||||
#define INT_SLL dsll
|
||||
#define INT_SRL dsrl
|
||||
#define INT_SRA dsra
|
||||
#define INT_SLLV dsllv
|
||||
#define INT_SRLV dsrlv
|
||||
#define INT_SRAV dsrav
|
||||
#define INT_LL lld
|
||||
#define INT_SC scd
|
||||
#endif /* _MIPS_SZINT == 64 */
|
||||
|
||||
#if (_MIPS_SZLONG == 32)
|
||||
#define LONG_L lw
|
||||
#define LONG_S sw
|
||||
#define LONG_LLEFT lwl /* load left */
|
||||
#define LONG_SLEFT swl /* store left */
|
||||
#define LONG_LRIGHT lwr /* load right */
|
||||
#define LONG_SRIGHT swr /* store right */
|
||||
#define LONG_ADD add
|
||||
#define LONG_ADDI addi
|
||||
#define LONG_ADDIU addiu
|
||||
#define LONG_ADDU addu
|
||||
#define LONG_SUB sub
|
||||
#define LONG_SUBI subi
|
||||
#define LONG_SUBIU subiu
|
||||
#define LONG_SUBU subu
|
||||
#define LONG_SLL sll
|
||||
#define LONG_SRL srl
|
||||
#define LONG_SRA sra
|
||||
#define LONG_SLLV sllv
|
||||
#define LONG_SRLV srlv
|
||||
#define LONG_SRAV srav
|
||||
#define LONG_LL ll
|
||||
#define LONG_SC sc
|
||||
#endif /* _MIPS_SZLONG == 32 */
|
||||
|
||||
#if (_MIPS_SZLONG == 64)
|
||||
#define LONG_L ld
|
||||
#define LONG_S sd
|
||||
#define LONG_LLEFT ldl /* load left */
|
||||
#define LONG_SLEFT sdl /* store left */
|
||||
#define LONG_LRIGHT ldr /* load right */
|
||||
#define LONG_SRIGHT sdr /* store right */
|
||||
#define LONG_ADD dadd
|
||||
#define LONG_ADDI daddi
|
||||
#define LONG_ADDIU daddiu
|
||||
#define LONG_ADDU daddu
|
||||
#define LONG_SUB dsub
|
||||
#define LONG_SUBI dsubi
|
||||
#define LONG_SUBIU dsubiu
|
||||
#define LONG_SUBU dsubu
|
||||
#define LONG_SLL dsll
|
||||
#define LONG_SRL dsrl
|
||||
#define LONG_SRA dsra
|
||||
#define LONG_SLLV dsllv
|
||||
#define LONG_SRLV dsrlv
|
||||
#define LONG_SRAV dsrav
|
||||
#define LONG_LL lld
|
||||
#define LONG_SC scd
|
||||
#endif /* _MIPS_SZLONG == 64 */
|
||||
|
||||
#if (_MIPS_SZPTR == 32)
|
||||
#define PTR_L lw
|
||||
#define PTR_S sw
|
||||
#define PTR_LLEFT lwl /* load left */
|
||||
#define PTR_SLEFT swl /* store left */
|
||||
#define PTR_LRIGHT lwr /* load right */
|
||||
#define PTR_SRIGHT swr /* store right */
|
||||
#define PTR_ADD add
|
||||
#define PTR_ADDI addi
|
||||
#define PTR_ADDIU addiu
|
||||
#define PTR_ADDU addu
|
||||
#define PTR_SUB sub
|
||||
#define PTR_SUBI subi
|
||||
#define PTR_SUBIU subiu
|
||||
#define PTR_SUBU subu
|
||||
#define PTR_SLL sll
|
||||
#define PTR_SRL srl
|
||||
#define PTR_SRA sra
|
||||
#define PTR_SLLV sllv
|
||||
#define PTR_SRLV srlv
|
||||
#define PTR_SRAV srav
|
||||
#define PTR_LL ll
|
||||
#define PTR_SC sc
|
||||
|
||||
#define PTR_WORD .word /* psuedo-op to reserve space for a ptr */
|
||||
#define PTR_SCALESHIFT 2
|
||||
|
||||
#define LI li
|
||||
#define LA la
|
||||
#endif /* _MIPS_SZPTR == 32 */
|
||||
|
||||
#if (_MIPS_SZPTR == 64)
|
||||
#define PTR_L ld
|
||||
#define PTR_S sd
|
||||
#define PTR_LLEFT ldl /* load left */
|
||||
#define PTR_SLEFT sdl /* store left */
|
||||
#define PTR_LRIGHT ldr /* load right */
|
||||
#define PTR_SRIGHT sdr /* store right */
|
||||
#define PTR_ADD dadd
|
||||
#define PTR_ADDI daddi
|
||||
#define PTR_ADDIU daddiu
|
||||
#define PTR_ADDU daddu
|
||||
#define PTR_SUB dsub
|
||||
#define PTR_SUBI dsubi
|
||||
#define PTR_SUBIU dsubiu
|
||||
#define PTR_SUBU dsubu
|
||||
#define PTR_SLL dsll
|
||||
#define PTR_SRL dsrl
|
||||
#define PTR_SRA dsra
|
||||
#define PTR_SLLV dsllv
|
||||
#define PTR_SRLV dsrlv
|
||||
#define PTR_SRAV dsrav
|
||||
#define PTR_LL lld
|
||||
#define PTR_SC scd
|
||||
|
||||
#define PTR_WORD .dword /* psuedo-op to reserve space for a ptr */
|
||||
#define PTR_SCALESHIFT 3
|
||||
|
||||
#define LI dli
|
||||
#define LA dla
|
||||
#endif /* _MIPS_SZPTR == 64 */
|
||||
|
||||
#if (_MIPS_ISA == _MIPS_ISA_MIPS1 || _MIPS_ISA == _MIPS_ISA_MIPS2)
|
||||
#define MFC0 mfc0
|
||||
#define MTC0 mtc0
|
||||
#endif
|
||||
|
||||
#if (_MIPS_ISA == _MIPS_ISA_MIPS3 || _MIPS_ISA == _MIPS_ISA_MIPS4)
|
||||
#define MFC0 dmfc0
|
||||
#define MTC0 dmtc0
|
||||
#endif
|
||||
#if TFP
|
||||
#define DMTC0(r,c) dmtc0 r,c; \
|
||||
NOP_MTC0_HAZ
|
||||
#define DMFC0(c,r) dmfc0 c,r; \
|
||||
NOP_MFC0_HAZ
|
||||
#if _K32U32 || _K32U64
|
||||
# This code only works for SABLE
|
||||
# We need to avoid a tlbmiss on the PC address (our pseudo-K0 space)
|
||||
# because such a fault destroys values loaded into BADVADDR,
|
||||
# TLBHI, etc.
|
||||
#define SABLE_GOTO_KP64(reg1,reg2) \
|
||||
lui reg2,0xa000; \
|
||||
dsll reg2,32; \
|
||||
la reg1,1f; \
|
||||
dsll reg1,35; \
|
||||
dsrl reg1,35; \
|
||||
dadd reg1,reg2; \
|
||||
NOP_SSNOP; \
|
||||
j reg1; \
|
||||
NOP_SSNOP; \
|
||||
NOP_SSNOP; \
|
||||
1: NOP_SSNOP \
|
||||
# Now we're executing in Kernel Physical (KP) space
|
||||
#else
|
||||
#define SABLE_GOTO_KP64(reg1,reg2)
|
||||
#endif /* !_K32U32 && ! _K32U64 */
|
||||
|
||||
#endif /* TFP */
|
||||
#if R3000 || R4000
|
||||
/* These macros let us replace existing mtc0/mfc0 instructions with macros
|
||||
* that have no additional overhead for non-TFP machines but have the required
|
||||
* number of scheduling NOPS for TFP.
|
||||
*/
|
||||
#define DMTC0(r,c) mtc0 r,c
|
||||
#define DMFC0(c,r) mfc0 c,r
|
||||
#define SABLE_GOTO_KP64(reg1,reg2)
|
||||
#endif /* R3000 || R4000 */
|
||||
|
||||
#if TFP_TLBCACHE_WAR
|
||||
/*
|
||||
* This problem occurs when there is an I-Cache miss within two cycles of
|
||||
* a valid tlb or dct (data cache tag) instruction. If the previous contents
|
||||
* of the I-Cache contained a store instruction, the data cache can be
|
||||
* corrupted.
|
||||
*
|
||||
* This problem can be worked around by putting all tlb/dct instructions on a
|
||||
* 16-byte boundary. And, the three instructions that follow the tlb/dct
|
||||
* must be ssnops (super-scalar no-ops). This guarantees that for the two
|
||||
* cycles following the tlb/dct instruction, there can only be noops in the
|
||||
* pipeline.
|
||||
*/
|
||||
#define TLB_READ .align 4; \
|
||||
c0 C0_READ; \
|
||||
NOP_SSNOP; \
|
||||
NOP_SSNOP; \
|
||||
NOP_SSNOP
|
||||
#define TLB_WRITER .align 4; \
|
||||
c0 C0_WRITER; \
|
||||
NOP_SSNOP; \
|
||||
NOP_SSNOP; \
|
||||
NOP_SSNOP
|
||||
#define TLB_PROBE .align 4; \
|
||||
c0 C0_PROBE; \
|
||||
NOP_SSNOP; \
|
||||
NOP_SSNOP; \
|
||||
NOP_SSNOP
|
||||
#else /* !TFP_TLBCACHE_WAR */
|
||||
#if TFP
|
||||
#define TLB_READ c0 C0_READ; \
|
||||
NOP_COM_HAZ
|
||||
#define TLB_WRITER c0 C0_WRITER; \
|
||||
NOP_COM_HAZ
|
||||
#define TLB_PROBE c0 C0_PROBE; \
|
||||
NOP_COM_HAZ
|
||||
#else
|
||||
#define TLB_READ c0 C0_READ
|
||||
#define TLB_WRITER c0 C0_WRITER
|
||||
#endif
|
||||
#endif /* !TFP_TLBCACHE_WAR */
|
||||
#endif /* __SYS_ASM_H__ */
|
||||
104
src/include/PR/sys/regdef.h
Executable file
104
src/include/PR/sys/regdef.h
Executable file
@ -0,0 +1,104 @@
|
||||
/**************************************************************************
|
||||
* *
|
||||
* Copyright (C) 1990-1992, Silicon Graphics, Inc. *
|
||||
* *
|
||||
* These coded instructions, statements, and computer programs contain *
|
||||
* unpublished proprietary information of Silicon Graphics, Inc., and *
|
||||
* are protected by Federal copyright law. They may not be disclosed *
|
||||
* to third parties or copied or duplicated in any form, in whole or *
|
||||
* in part, without the prior written consent of Silicon Graphics, Inc. *
|
||||
* *
|
||||
**************************************************************************/
|
||||
/*
|
||||
* Copyright 1985 by MIPS Computer Systems, Inc.
|
||||
*/
|
||||
#ifndef __SYS_REGDEF_H__
|
||||
#define __SYS_REGDEF_H__
|
||||
|
||||
#ident "$Revision: 3.7 $"
|
||||
|
||||
#include "sgidefs.h"
|
||||
|
||||
#if (_MIPS_SIM == _MIPS_SIM_ABI32)
|
||||
#define zero $0 /* wired zero */
|
||||
#define AT $at /* assembler temp */
|
||||
#define v0 $2 /* return value */
|
||||
#define v1 $3
|
||||
#define a0 $4 /* argument registers */
|
||||
#define a1 $5
|
||||
#define a2 $6
|
||||
#define a3 $7
|
||||
#define t0 $8 /* caller saved */
|
||||
#define t1 $9
|
||||
#define t2 $10
|
||||
#define t3 $11
|
||||
#define t4 $12 /* caller saved - 32 bit env arg reg 64 bit */
|
||||
#define ta0 $12 /* caller saved in 32 bit - arg regs in 64 bit */
|
||||
#define t5 $13
|
||||
#define ta1 $13
|
||||
#define t6 $14
|
||||
#define ta2 $14
|
||||
#define t7 $15
|
||||
#define ta3 $15
|
||||
#define s0 $16 /* callee saved */
|
||||
#define s1 $17
|
||||
#define s2 $18
|
||||
#define s3 $19
|
||||
#define s4 $20
|
||||
#define s5 $21
|
||||
#define s6 $22
|
||||
#define s7 $23
|
||||
#define t8 $24 /* code generator */
|
||||
#define t9 $25
|
||||
#define jp $25 /* PIC jump register */
|
||||
#define k0 $26 /* kernel temporary */
|
||||
#define k1 $27
|
||||
#define gp $28 /* global pointer */
|
||||
#define sp $29 /* stack pointer */
|
||||
#define fp $30 /* frame pointer */
|
||||
#define s8 $30 /* calle saved */
|
||||
#define ra $31 /* return address */
|
||||
#endif
|
||||
|
||||
#if (_MIPS_SIM == _MIPS_SIM_ABI64)
|
||||
#define zero $0 /* wired zero */
|
||||
#define AT $at /* assembler temp */
|
||||
#define v0 $2 /* return value - caller saved */
|
||||
#define v1 $3
|
||||
#define a0 $4 /* argument registers */
|
||||
#define a1 $5
|
||||
#define a2 $6
|
||||
#define a3 $7
|
||||
#define a4 $8 /* arg reg 64 bit; caller saved in 32 bit */
|
||||
#define ta0 $8
|
||||
#define a5 $9
|
||||
#define ta1 $9
|
||||
#define a6 $10
|
||||
#define ta2 $10
|
||||
#define a7 $11
|
||||
#define ta3 $11
|
||||
#define t0 $12 /* caller saved */
|
||||
#define t1 $13
|
||||
#define t2 $14
|
||||
#define t3 $15
|
||||
#define s0 $16 /* callee saved */
|
||||
#define s1 $17
|
||||
#define s2 $18
|
||||
#define s3 $19
|
||||
#define s4 $20
|
||||
#define s5 $21
|
||||
#define s6 $22
|
||||
#define s7 $23
|
||||
#define t8 $24 /* caller saved */
|
||||
#define t9 $25 /* callee address for PIC/temp */
|
||||
#define jp $25 /* PIC jump register */
|
||||
#define k0 $26 /* kernel temporary */
|
||||
#define k1 $27
|
||||
#define gp $28 /* global pointer - caller saved for PIC */
|
||||
#define sp $29 /* stack pointer */
|
||||
#define fp $30 /* frame pointer */
|
||||
#define s8 $30 /* callee saved */
|
||||
#define ra $31 /* return address */
|
||||
#endif
|
||||
|
||||
#endif /* __SYS_REGDEF_H__ */
|
||||
@ -12,6 +12,8 @@
|
||||
#define OS_TV_NTSC 1
|
||||
#define OS_TV_MPAL 2
|
||||
|
||||
#if defined(_LANGUAGE_C) || defined(_LANGUAGE_C_PLUS_PLUS)
|
||||
|
||||
typedef signed char s8;
|
||||
typedef unsigned char u8;
|
||||
typedef signed short int s16;
|
||||
@ -36,3 +38,5 @@ typedef double f64;
|
||||
typedef unsigned long size_t;
|
||||
|
||||
#endif
|
||||
|
||||
#endif
|
||||
|
||||
13
src/include/asm_helper.h
Normal file
13
src/include/asm_helper.h
Normal file
@ -0,0 +1,13 @@
|
||||
#ifndef _ASM_HELPER_H
|
||||
#define _ASM_HELPER_H
|
||||
#include "PR/R4300.h"
|
||||
#include "PR/sys/regdef.h"
|
||||
#include "PR/sys/asm.h"
|
||||
#include "PR/rcp.h"
|
||||
|
||||
#define STAY1(stmnt) .set noreorder; stmnt; .set reorder;
|
||||
#define STAY2(stmnt, arg1) .set noreorder; stmnt, arg1; .set reorder;
|
||||
#define STAY3(stmnt, arg1, arg2) .set noreorder; stmnt, arg1, arg2; .set reorder;
|
||||
#define NOP .set noreorder; nop; .set reorder;
|
||||
#define CACHE(op, reg) .set noreorder; cache op, reg; .set reorder;
|
||||
#endif
|
||||
189
src/include/sgidefs.h
Executable file
189
src/include/sgidefs.h
Executable file
@ -0,0 +1,189 @@
|
||||
/**************************************************************************
|
||||
* *
|
||||
* Copyright (C) 1991-1992 Silicon Graphics, Inc. *
|
||||
* *
|
||||
* These coded instructions, statements, and computer programs contain *
|
||||
* unpublished proprietary information of Silicon Graphics, Inc., and *
|
||||
* are protected by Federal copyright law. They may not be disclosed *
|
||||
* to third parties or copied or duplicated in any form, in whole or *
|
||||
* in part, without the prior written consent of Silicon Graphics, Inc. *
|
||||
* *
|
||||
**************************************************************************/
|
||||
#ifndef __SGIDEFS_H__
|
||||
#define __SGIDEFS_H__
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#ident "$Revision: 1.5 $"
|
||||
|
||||
/*
|
||||
* sgidefs.h - SGI/MIPS basic software generation system constants & types
|
||||
*
|
||||
* This file MUST be includable in any language
|
||||
* and in the 'C' case must be ANSI compliant
|
||||
* In particular this means NO long long ...
|
||||
*
|
||||
* Constants and types defined here are to support
|
||||
* multi-isa (instruction set architecture) coding
|
||||
*
|
||||
* Each catagory has a define that the compilation system will set
|
||||
* based on the environment the compile is initiated in. Programs
|
||||
* can test the define using the manifest constants defined here.
|
||||
* (e.g. #if (_MIPS_FPSET == 16) )
|
||||
*/
|
||||
|
||||
/*
|
||||
* Floating Point register set
|
||||
* Define:
|
||||
* _MIPS_FPSET
|
||||
* Can take on the values 16 or 32
|
||||
*/
|
||||
|
||||
/*
|
||||
* Instruction Set Architecture
|
||||
* Define:
|
||||
* _MIPS_ISA
|
||||
*/
|
||||
#define _MIPS_ISA_MIPS1 1 /* R2/3K */
|
||||
#define _MIPS_ISA_MIPS2 2 /* R4K/6K */
|
||||
#define _MIPS_ISA_MIPS3 3 /* R4K */
|
||||
#define _MIPS_ISA_MIPS4 4 /* TFP */
|
||||
|
||||
/*
|
||||
* Subprogram Interface Model
|
||||
* Define:
|
||||
* _MIPS_SIM
|
||||
*/
|
||||
#define _MIPS_SIM_ABI32 1 /* MIPS MSIG calling convention */
|
||||
#define _MIPS_SIM_NABI32 2 /* MIPS new 32-bit abi */
|
||||
/* NABI32 is 64bit calling convention but 32bit type sizes) */
|
||||
#define _MIPS_SIM_ABI64 3 /* MIPS 64 calling convention */
|
||||
|
||||
/*
|
||||
* Data Types Sizes (C and C++)
|
||||
* Defines:
|
||||
* _MIPS_SZINT
|
||||
* _MIPS_SZLONG
|
||||
* _MIPS_SZPTR
|
||||
*
|
||||
* These can take on the values: 32, 64, 128
|
||||
*/
|
||||
|
||||
/*
|
||||
* Compilation Environments
|
||||
* various compilers may offer a set of different compilation environments
|
||||
* each one will pre-define the above defines appropriately.
|
||||
* The MIPS ABI environment will pre-define the following:
|
||||
* (cc -systype=XXX)
|
||||
*
|
||||
* -D_MIPS_FPSET=16 -D_MIPS_ISA=_MIPS_ISA_MIPS1
|
||||
* -D_MIPS_SIM=_MIPS_SIM_ABI32 -D_MIPS_SZINT=32
|
||||
* -D_MIPS_SZLONG=32 -D_MIPS_SZPTR=32
|
||||
*
|
||||
* The new MIPS 32-bit ABI environment will pre-define the following
|
||||
* (cc -systype=XXX)
|
||||
* -D_MIPS_FPSET=32 -D_MIPS_ISA=_MIPS_ISA_MIPS3
|
||||
* -D_MIPS_SIM=_MIPS_SIM_NABI32 -D_MIPS_SZINT=32
|
||||
* -D_MIPS_SZLONG=32 -D_MIPS_SZPTR=32
|
||||
*
|
||||
* The MIPS 64 bit environment will pre-define the following
|
||||
* (cc -systype=XXX)
|
||||
* -D_MIPS_FPSET=32 -D_MIPS_ISA=_MIPS_ISA_MIPS3
|
||||
* -D_MIPS_SIM=_MIPS_SIM_ABI64 -D_MIPS_SZINT=32
|
||||
* -D_MIPS_SZLONG=64 -D_MIPS_SZPTR=64
|
||||
*
|
||||
*/
|
||||
|
||||
/*
|
||||
* Language Specific
|
||||
* Type __psint_t - a pointer sized int - this can be used:
|
||||
* a) when casting a pointer so can perform e.g. a bit operation
|
||||
* b) as a return code for functions incorrectly typed as int but
|
||||
* return a pointer.
|
||||
* User level code can also use the ANSI std ptrdiff_t, defined in stddef.h
|
||||
* in place of __psint_t
|
||||
* Type __scint_t - a 'scaling' int - used when in fact one wants an 'int'
|
||||
* that scales when moving to say 64 bit. (e.g. byte counts, bit lens)
|
||||
*/
|
||||
|
||||
#if (defined(_LANGUAGE_C) || defined(_LANGUAGE_C_PLUS_PLUS))
|
||||
|
||||
/*
|
||||
* assumes int is 32 -
|
||||
* otherwise there must be some other compiler basic type
|
||||
*/
|
||||
#if (_MIPS_SZINT != 32)
|
||||
#ifdef _MIPS_SZINT
|
||||
ERROR -- the macro "_MIPS_SZINT" is set to _MIPS_SZINT -- should be 32
|
||||
#else
|
||||
ERROR -- the macro "_MIPS_SZINT" is unset (currently, must be set to 32)
|
||||
#endif
|
||||
#endif
|
||||
|
||||
typedef int __int32_t;
|
||||
typedef unsigned __uint32_t;
|
||||
|
||||
#if (_MIPS_SZLONG == 64)
|
||||
|
||||
typedef long __int64_t;
|
||||
typedef unsigned long __uint64_t;
|
||||
|
||||
#else
|
||||
|
||||
#if defined(_LONGLONG)
|
||||
|
||||
typedef long long __int64_t;
|
||||
typedef unsigned long long __uint64_t;
|
||||
|
||||
#else
|
||||
|
||||
typedef struct {
|
||||
int hi32;
|
||||
int lo32;
|
||||
} __int64_t;
|
||||
typedef struct {
|
||||
unsigned int hi32;
|
||||
unsigned int lo32;
|
||||
} __uint64_t;
|
||||
|
||||
#endif /* _LONGLONG */
|
||||
|
||||
#endif /* _MIPS_SZLONG */
|
||||
|
||||
#if (_MIPS_SZPTR == 32)
|
||||
typedef __int32_t __psint_t;
|
||||
typedef __uint32_t __psunsigned_t;
|
||||
#endif
|
||||
|
||||
#if (_MIPS_SZPTR == 64)
|
||||
typedef __int64_t __psint_t;
|
||||
typedef __uint64_t __psunsigned_t;
|
||||
#endif
|
||||
|
||||
/*
|
||||
* If any fundamental type is 64 bit, then set the scaling type
|
||||
* to 64 bit
|
||||
*/
|
||||
#if (_MIPS_SZPTR == 64) || (_MIPS_SZLONG == 64) || (_MIPS_SZINT == 64)
|
||||
|
||||
/* there exists some large fundamental type */
|
||||
typedef __int64_t __scint_t;
|
||||
typedef __uint64_t __scunsigned_t;
|
||||
|
||||
#else
|
||||
|
||||
/* a 32 bit world */
|
||||
typedef __int32_t __scint_t;
|
||||
typedef __uint32_t __scunsigned_t;
|
||||
|
||||
#endif
|
||||
|
||||
#endif /* C || C++ */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* !__SGIDEFS_H__ */
|
||||
@ -1,29 +0,0 @@
|
||||
#include <libultra_internal.h>
|
||||
|
||||
GLOBAL_ASM(
|
||||
glabel osMapTLBRdb
|
||||
/* 2ff0: 40085000 */ mfc0 $t0,$10
|
||||
/* 2ff4: 24090001 */ addiu $t1,$zero,0x1
|
||||
/* 2ff8: 40890000 */ mtc0 $t1,$0
|
||||
/* 2ffc: 40802800 */ mtc0 $zero,$5
|
||||
/* 3000: 240a0017 */ addiu $t2,$zero,0x17
|
||||
/* 3004: 3c09c000 */ lui $t1,0xc000
|
||||
/* 3008: 40895000 */ mtc0 $t1,$10
|
||||
/* 300c: 3c098000 */ lui $t1,0x8000
|
||||
/* 3010: 00095982 */ srl $t3,$t1,0x6
|
||||
/* 3014: 016a5825 */ or $t3,$t3,$t2
|
||||
/* 3018: 408b1000 */ mtc0 $t3,$2
|
||||
/* 301c: 24090001 */ addiu $t1,$zero,0x1
|
||||
/* 3020: 40891800 */ mtc0 $t1,$3
|
||||
/* 3024: 00000000 */ nop
|
||||
/* 3028: 42000002 */ tlbwi
|
||||
/* 302c: 00000000 */ nop
|
||||
/* 3030: 00000000 */ nop
|
||||
/* 3034: 00000000 */ nop
|
||||
/* 3038: 00000000 */ nop
|
||||
/* 303c: 40885000 */ mtc0 $t0,$10
|
||||
/* 3040: 03e00008 */ jr $ra
|
||||
/* 3044: 00000000 */ nop
|
||||
/* 3048: 00000000 */ nop
|
||||
/* 304c: 00000000 */ nop
|
||||
);
|
||||
29
src/lib/ultra/os/maptlbrdb.s
Normal file
29
src/lib/ultra/os/maptlbrdb.s
Normal file
@ -0,0 +1,29 @@
|
||||
#include "asm_helper.h"
|
||||
.set noat
|
||||
.set noreorder
|
||||
|
||||
.text
|
||||
LEAF(osMapTLBRdb)
|
||||
mfc0 t0, C0_ENTRYHI
|
||||
li t1, 1
|
||||
mtc0 t1, C0_INX
|
||||
mtc0 zero, C0_PAGEMASK
|
||||
li t2, TLBLO_UNCACHED | TLBLO_D | TLBLO_V | TLBLO_G
|
||||
li t1, K2BASE
|
||||
mtc0 t1, C0_ENTRYHI
|
||||
li t1, KUSIZE
|
||||
srl t3, t1,TLBLO_PFNSHIFT
|
||||
or t3, t3,t2
|
||||
mtc0 t3, C0_ENTRYLO0
|
||||
li t1, TLBLO_G
|
||||
mtc0 t1, C0_ENTRYLO1
|
||||
nop
|
||||
tlbwi
|
||||
nop
|
||||
nop
|
||||
nop
|
||||
nop
|
||||
mtc0 t0, C0_ENTRYHI
|
||||
jr ra
|
||||
nop
|
||||
END(osMapTLBRdb)
|
||||
BIN
tools/irix/root/usr/bin/as
Executable file
BIN
tools/irix/root/usr/bin/as
Executable file
Binary file not shown.
Loading…
Reference in New Issue
Block a user