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69 lines
2.2 KiB
C
69 lines
2.2 KiB
C
/*
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* Copyright (c) 1995, Silicon Graphics, Inc. All Rights Reserved.
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*
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* This is UNPUBLISHED PROPRIETARY SOURCE CODE of Silicon Graphics, Inc.;
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* the contents of this file may not be disclosed to third parties, copied
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* or duplicated in any form, in whole or in part, without the prior written
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* permission of Silicon Graphics, Inc.
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*
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* RESTRICTED RIGHTS LEGEND:
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* Use, duplication or disclosure by the Government is subject to restrictions
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* as set forth in subdivision (c)(1)(ii) of the Rights in Technical Data
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* and Computer Software clause at DFARS 252.227-7013, and/or in similar or
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* successor clauses in the FAR, DOD or NASA FAR Supplement. Unpublished
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* rights reserved under the Copyright Laws of the United States.
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*
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* Module: tinymon.h: constants for use with the tinymon family of debug servers
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*/
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#define GIO_BASE_REG_UPPER 0x1800
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#define GIO_BASE_REG_UPPER_K1 0xb800
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#define GIO_INTR_REG_OFFSET 0x0
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#define GIO_SYNC_REG_OFFSET 0x400
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#define CART_INTR_REG_OFFSET 0x800
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#define RAMROM_BASE_UPPER 0x1000
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#define RAMROM_BASE_UPPER_K1 0xb000
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/*
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* jal will or in the upper four bits of 0xb0000000 whenever we invoke these
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* routines.
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*/
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#define PIFMON_WRITE_ADDR 0xfc00030
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#define PI_BASE_REG_UPPER 0x0460
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#define PI_BASE_REG_UPPER_K1 0xa460
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#define PI_STATUS_REG_OFFSET 0x10
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/*
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* PI status register has 3 bits active when read from (PI_STATUS_REG - read)
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* Bit 0: DMA busy - set when DMA is in progress
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* Bit 1: IO busy - set when IO is in progress
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* Bit 2: Error - set when R4300 issues IO request while DMA is busy
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*/
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#define PI_STATUS_ERROR 0x04
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#define PI_STATUS_IO_BUSY 0x02
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#define PI_STATUS_DMA_BUSY 0x01
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/*
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* Host to R4300 protocol definitions.
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*
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* Host writes DG_RAMROM_REQUEST, DG_RAMROM_CMD_READY to the cartridge
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* interrupt register (which the R4300 can poll),
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*
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* R4300 writes DG_RAMROM_GRANT, DG_RAMROM_CMD_DONE to the gio sync register
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* (which the host can poll).
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*/
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#define DG_CARTREG_MASK 0x3f
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#define DG_RAMROM_REQUEST 1
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#define DG_RAMROM_GRANT 2
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#define DG_RAMROM_CMD_READY 3
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#define DG_RAMROM_CMD_DONE 4
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#define DG_TINYMON_READ_OP 1
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#define DG_TINYMON_WRITE_OP 2
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#define DG_TINYMON_DMA_READ_OP 3
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#define DG_TINYMON_DMA_WRITE_OP 4
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