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sceptillion 2017-12-10 22:41:46 -08:00
commit d07afbc081
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.gitattributes vendored Normal file
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*.pal text eol=crlf
*.s text eol=lf
*.txt text eol=lf
Makefile text eol=lf
*.mk text eol=lf
*.c text eol=lf
*.h text eol=lf
*.pl text eol=lf
*.inc text eol=lf
*.sha1 text eol=lf
*.sed text eol=lf
*.png binary
*.bin binary

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*.exe
*.o
*.i
*.elf
*.gba
*.1bpp
*.4bpp
*.8bpp
*.gbapal
*.lz
*.rl
*.pcm
*.latfont
*.hwjpnfont
*.fwjpnfont
*.bat
sound/**/*.bin
src/*.s
tools/agbcc
ld_script_ruby.txt
ld_script_sapphire.txt
*.map
*.id0
*.id1
*.id2
*.nam
*.til
*.ld
tags
types_*.taghl
*.swp
*.swo
*.s.old
*.s.old2
*.dump
*.sa*
Thumbs.db
build/
.idea/
*.DS_Store
*.pl
tools/

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Makefile Normal file
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AS := $(DEVKITARM)/bin/arm-none-eabi-as
ASFLAGS := -mcpu=arm7tdmi
CC1 := tools/agbcc/bin/agbcc
override CFLAGS += -mthumb-interwork -Wimplicit -Wparentheses -Wunused -Werror -O2 -fhex-asm
CPP := $(DEVKITARM)/bin/arm-none-eabi-cpp
CPPFLAGS := -I tools/agbcc/include -iquote include -nostdinc -undef
LD := $(DEVKITARM)/bin/arm-none-eabi-ld
OBJCOPY := $(DEVKITARM)/bin/arm-none-eabi-objcopy
LIBGCC := tools/agbcc/lib/libgcc.a
MD5 := md5sum -c
GFX := tools/gbagfx/gbagfx
AIF := tools/aif2pcm/aif2pcm
MID := tools/mid2agb/mid2agb
SCANINC := tools/scaninc/scaninc
PREPROC := tools/preproc/preproc
RAMSCRGEN := tools/ramscrgen/ramscrgen
# Clear the default suffixes.
.SUFFIXES:
# Secondary expansion is required for dependency variables in object rules.
.SECONDEXPANSION:
.PRECIOUS: %.1bpp %.4bpp %.8bpp %.gbapal %.lz %.rl %.pcm %.bin
.PHONY: all clean tidy
C_SRCS := $(wildcard src/*.c)
C_OBJS := $(C_SRCS:%.c=%.o)
ASM_SRCS := $(wildcard asm/*.s)
ASM_OBJS := $(ASM_SRCS:%.s=%.o)
DATA_ASM_SRCS := $(wildcard data/*.s)
DATA_ASM_OBJS := $(DATA_ASM_SRCS:%.s=%.o)
OBJS := $(C_OBJS) $(ASM_OBJS) $(DATA_ASM_OBJS)
all: pmd_red.gba
# For contributors to make sure a change didn't affect the contents of the ROM.
compare: all
@$(MD5) rom.md5
clean: tidy
tidy:
rm -f pmd_red.gba pmd_red.elf pmd_red.map
rm -f $(ASM_OBJS)
rm -f $(DATA_ASM_OBJS)
rm -f $(C_OBJS)
rm -f $(ASM_OBJS)
rm -f $(DATA_ASM_OBJS)
rm -f $(C_SRCS:%.c=%.i)
rm -f $(C_SRCS:%.c=%.s)
rm -f *.ld
src/agb_flash.o: CFLAGS := -O -mthumb-interwork
src/agb_flash_1m.o: CFLAGS := -O -mthumb-interwork
src/agb_flash_mx.o: CFLAGS := -O -mthumb-interwork
$(C_OBJS): %.o : %.c
@$(CPP) $(CPPFLAGS) $< -o $*.i
@$(CC1) $(CFLAGS) $*.i -o $*.s
@printf ".text\n\t.align\t2, 0\n" >> $*.s
$(AS) $(ASFLAGS) -o $@ $*.s
$(ASM_OBJS): %.o: %.s
$(AS) $(ASFLAGS) -o $@ $<
$(DATA_ASM_OBJS): %.o: %.s
$(AS) $(ASFLAGS) -o $@ $<
sym_ewram.ld: sym_ewram.txt
$(RAMSCRGEN) ewram_data sym_ewram.txt ENGLISH >$@
sym_ewram2.ld: sym_ewram2.txt
$(RAMSCRGEN) ewram_data sym_ewram2.txt ENGLISH >$@
sym_iwram.ld: sym_iwram.txt
$(RAMSCRGEN) iwram_data sym_iwram.txt ENGLISH >$@
ld_script.ld: ld_script.txt sym_ewram.ld sym_ewram2.ld sym_iwram.ld
sed -f ld_script.sed ld_script.txt >ld_script.ld
pmd_red.elf: ld_script.ld $(OBJS)
$(LD) -T ld_script.ld -Map pmd_red.map -o $@ $(OBJS) $(LIBGCC)
pmd_red.gba: pmd_red.elf
$(OBJCOPY) -O binary --gap-fill 0xFF --pad-to 0xA000000 $< $@

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.include "constants/gba_constants.inc"
.include "asm/macros.inc"
.syntax unified
.section .rodata
.space 0x3C
.text
thumb_func_start _08272760
_08272760:
push {lr}
adds r1, r0, 0
ldr r0, _08272770
bl _08272774
pop {r0}
bx r0
.align 2, 0
_08272770: .4byte 0x02027370
thumb_func_end _08272760
thumb_func_start _08272774
_08272774:
push {r4-r7,lr}
mov r7, r10
mov r6, r9
mov r5, r8
push {r5-r7}
sub sp, 0x10
lsls r2, r1, 3
adds r2, r1
lsls r2, 3
adds r4, r0, r2
movs r1, 0x8
ldrsh r0, [r4, r1]
cmp r0, 0
ble _08272860
ldr r0, [r4, 0xC]
cmp r0, 0x6
bne _082727B0
movs r2, 0x4
ldrsh r1, [r4, r2]
ldr r0, [r4, 0x24]
adds r0, 0x2
lsls r0, 3
muls r0, r1
lsls r0, 2
ldr r1, [r4, 0x18]
adds r1, r0
movs r3, 0x8
ldrsh r0, [r4, r3]
subs r2, r0, 0x2
b _082727B6
_082727B0:
ldr r1, [r4, 0x18]
movs r5, 0x8
ldrsh r2, [r4, r5]
_082727B6:
ldr r0, [r4, 0x20]
adds r3, r0, 0
adds r3, 0x8
str r3, [sp]
adds r0, 0x9
mov r10, r0
movs r3, 0
movs r5, 0x4
ldrsh r0, [r4, r5]
ldr r5, [r4, 0x28]
str r5, [sp, 0x8]
ldr r5, [r4, 0x1C]
str r5, [sp, 0x4]
adds r5, r4, 0
adds r5, 0x44
str r5, [sp, 0xC]
cmp r3, r0
bge _0827284E
subs r7, r2, 0x1
mov r9, r3
_082727DE:
adds r2, r1, 0
movs r0, 0x20
adds r0, r2
mov r12, r0
adds r3, 0x1
mov r8, r3
cmp r7, 0
ble _08272824
ldr r1, [sp]
lsls r6, r1, 2
adds r3, r7, 0
mov r0, r10
lsls r5, r0, 2
_082727F8:
ldr r0, [r2, 0x8]
str r0, [r2]
ldr r0, [r2, 0xC]
str r0, [r2, 0x4]
ldr r0, [r2, 0x10]
str r0, [r2, 0x8]
ldr r0, [r2, 0x14]
str r0, [r2, 0xC]
ldr r0, [r2, 0x18]
str r0, [r2, 0x10]
ldr r0, [r2, 0x1C]
str r0, [r2, 0x14]
adds r1, r6, r2
ldr r0, [r1]
str r0, [r2, 0x18]
adds r0, r5, r2
ldr r0, [r0]
str r0, [r2, 0x1C]
adds r2, r1, 0
subs r3, 0x1
cmp r3, 0
bne _082727F8
_08272824:
ldr r0, [r2, 0x8]
str r0, [r2]
ldr r0, [r2, 0xC]
str r0, [r2, 0x4]
ldr r0, [r2, 0x10]
str r0, [r2, 0x8]
ldr r0, [r2, 0x14]
str r0, [r2, 0xC]
ldr r0, [r2, 0x18]
str r0, [r2, 0x10]
ldr r0, [r2, 0x1C]
str r0, [r2, 0x14]
mov r1, r9
str r1, [r2, 0x18]
str r1, [r2, 0x1C]
mov r1, r12
mov r3, r8
movs r2, 0x4
ldrsh r0, [r4, r2]
cmp r3, r0
blt _082727DE
_0827284E:
ldr r3, [sp, 0x8]
str r3, [r4, 0x30]
ldr r5, [sp, 0x4]
str r5, [r4, 0x34]
ldr r0, [r4, 0x2C]
str r0, [r4, 0x38]
movs r0, 0x1
ldr r1, [sp, 0xC]
strb r0, [r1]
_08272860:
add sp, 0x10
pop {r3-r5}
mov r8, r3
mov r9, r4
mov r10, r5
pop {r4-r7}
pop {r0}
bx r0
thumb_func_end _08272774
thumb_func_start _08272870
_08272870:
push {lr}
adds r1, r0, 0
ldr r0, _08272880
bl _08272884
pop {r0}
bx r0
.align 2, 0
_08272880: .4byte 0x02027370
thumb_func_end _08272870
thumb_func_start _08272884
_08272884:
push {r4-r7,lr}
mov r7, r10
mov r6, r9
mov r5, r8
push {r5-r7}
sub sp, 0xC
lsls r2, r1, 3
adds r2, r1
lsls r2, 3
adds r5, r0, r2
movs r1, 0x8
ldrsh r0, [r5, r1]
cmp r0, 0
ble _08272994
ldr r0, [r5, 0xC]
cmp r0, 0x6
bne _082728B0
movs r2, 0x8
ldrsh r0, [r5, r2]
subs r0, 0x2
mov r9, r0
b _082728B6
_082728B0:
movs r0, 0x8
ldrsh r3, [r5, r0]
mov r9, r3
_082728B6:
movs r1, 0x8
ldrsh r0, [r5, r1]
subs r0, 0x1
movs r3, 0x4
ldrsh r2, [r5, r3]
muls r0, r2
lsls r0, 5
ldr r1, [r5, 0x18]
adds r1, r0
ldr r0, [r5, 0x20]
adds r0, 0x8
mov r10, r0
movs r4, 0
ldr r0, [r5, 0x28]
str r0, [sp]
ldr r3, [r5, 0x1C]
str r3, [sp, 0x8]
adds r0, r5, 0
adds r0, 0x44
str r0, [sp, 0x4]
cmp r4, r2
bge _08272982
mov r12, r4
movs r2, 0x1
negs r2, r2
add r2, r9
mov r8, r2
_082728EC:
adds r2, r1, 0
mov r3, r9
cmp r3, 0x1
bgt _0827291A
ldr r0, [r1, 0x14]
str r0, [r1, 0x1C]
ldr r0, [r1, 0x10]
str r0, [r1, 0x18]
ldr r0, [r1, 0xC]
str r0, [r1, 0x14]
ldr r0, [r1, 0x8]
str r0, [r1, 0x10]
ldr r0, [r1, 0x4]
str r0, [r1, 0xC]
ldr r0, [r1]
str r0, [r1, 0x8]
mov r0, r12
str r0, [r1, 0x4]
str r0, [r1]
adds r7, r1, 0
adds r7, 0x20
adds r6, r4, 0x1
b _08272976
_0827291A:
mov r3, r10
lsls r0, r3, 2
subs r3, r1, r0
adds r7, r1, 0
adds r7, 0x20
adds r6, r4, 0x1
mov r1, r8
cmp r1, 0
ble _08272958
adds r4, r0, 0
_0827292E:
ldr r0, [r2, 0x14]
str r0, [r2, 0x1C]
ldr r0, [r2, 0x10]
str r0, [r2, 0x18]
ldr r0, [r2, 0xC]
str r0, [r2, 0x14]
ldr r0, [r2, 0x8]
str r0, [r2, 0x10]
ldr r0, [r2, 0x4]
str r0, [r2, 0xC]
ldr r0, [r2]
str r0, [r2, 0x8]
ldr r0, [r3, 0x1C]
str r0, [r2, 0x4]
ldr r0, [r3, 0x18]
str r0, [r2]
subs r2, r4
subs r3, r4
subs r1, 0x1
cmp r1, 0
bne _0827292E
_08272958:
ldr r0, [r2, 0x14]
str r0, [r2, 0x1C]
ldr r0, [r2, 0x10]
str r0, [r2, 0x18]
ldr r0, [r2, 0xC]
str r0, [r2, 0x14]
ldr r0, [r2, 0x8]
str r0, [r2, 0x10]
ldr r0, [r2, 0x4]
str r0, [r2, 0xC]
ldr r0, [r2]
str r0, [r2, 0x8]
mov r3, r12
str r3, [r2, 0x4]
str r3, [r2]
_08272976:
adds r1, r7, 0
adds r4, r6, 0
movs r2, 0x4
ldrsh r0, [r5, r2]
cmp r4, r0
blt _082728EC
_08272982:
ldr r3, [sp]
str r3, [r5, 0x30]
ldr r0, [sp, 0x8]
str r0, [r5, 0x34]
ldr r0, [r5, 0x2C]
str r0, [r5, 0x38]
movs r0, 0x1
ldr r1, [sp, 0x4]
strb r0, [r1]
_08272994:
add sp, 0xC
pop {r3-r5}
mov r8, r3
mov r9, r4
mov r10, r5
pop {r4-r7}
pop {r0}
bx r0
thumb_func_end _08272884
thumb_func_start _082729A4
_082729A4:
push {lr}
adds r1, r0, 0
ldr r0, _082729B4
bl _082729B8
pop {r0}
bx r0
.align 2, 0
_082729B4: .4byte 0x02027370
thumb_func_end _082729A4
thumb_func_start _082729B8
_082729B8:
push {r4-r7,lr}
mov r7, r8
push {r7}
lsls r2, r1, 3
adds r2, r1
lsls r2, 3
adds r4, r0, r2
ldr r2, [r4, 0x18]
ldr r0, [r4, 0x20]
adds r1, r0, 0
adds r1, 0x8
adds r5, r0, 0
adds r5, 0x9
movs r3, 0
movs r6, 0x4
ldrsh r0, [r4, r6]
cmp r3, r0
bge _08272A5A
lsls r1, 2
mov r8, r1
lsls r6, r5, 2
movs r5, 0
_082729E4:
ldr r0, [r2, 0x14]
str r0, [r2, 0xC]
ldr r0, [r2, 0x18]
str r0, [r2, 0x10]
ldr r0, [r2, 0x1C]
str r0, [r2, 0x14]
mov r0, r8
adds r1, r0, r2
ldr r0, [r1]
str r0, [r2, 0x18]
adds r0, r6, r2
ldr r0, [r0]
str r0, [r2, 0x1C]
adds r7, r2, 0
adds r7, 0x20
adds r3, 0x1
mov r12, r3
movs r3, 0x4
_08272A08:
ldr r0, [r1, 0x8]
str r0, [r1]
ldr r0, [r1, 0xC]
str r0, [r1, 0x4]
ldr r0, [r1, 0x10]
str r0, [r1, 0x8]
ldr r0, [r1, 0x14]
str r0, [r1, 0xC]
ldr r0, [r1, 0x18]
str r0, [r1, 0x10]
ldr r0, [r1, 0x1C]
str r0, [r1, 0x14]
mov r0, r8
adds r2, r0, r1
ldr r0, [r2]
str r0, [r1, 0x18]
adds r0, r6, r1
ldr r0, [r0]
str r0, [r1, 0x1C]
adds r1, r2, 0
subs r3, 0x1
cmp r3, 0
bge _08272A08
ldr r0, [r2, 0x8]
str r0, [r2]
ldr r0, [r2, 0xC]
str r0, [r2, 0x4]
ldr r0, [r2, 0x10]
str r0, [r2, 0x8]
ldr r0, [r2, 0x14]
str r0, [r2, 0xC]
str r5, [r2, 0x10]
str r5, [r2, 0x14]
str r5, [r2, 0x18]
str r5, [r2, 0x1C]
adds r2, r7, 0
mov r3, r12
movs r1, 0x4
ldrsh r0, [r4, r1]
cmp r3, r0
blt _082729E4
_08272A5A:
ldr r0, [r4, 0x28]
str r0, [r4, 0x30]
ldr r0, [r4, 0x1C]
str r0, [r4, 0x34]
ldr r0, [r4, 0x2C]
str r0, [r4, 0x38]
adds r1, r4, 0
adds r1, 0x44
movs r0, 0x1
strb r0, [r1]
pop {r3}
mov r8, r3
pop {r4-r7}
pop {r0}
bx r0
thumb_func_end _082729B8
thumb_func_start _08272A78
_08272A78:
push {lr}
adds r1, r0, 0
ldr r0, _08272A88
bl _08272A8C
pop {r0}
bx r0
.align 2, 0
_08272A88: .4byte 0x02027370
thumb_func_end _08272A78
thumb_func_start _08272A8C
_08272A8C:
push {r4-r7,lr}
lsls r2, r1, 3
adds r2, r1
lsls r2, 3
adds r4, r0, r2
ldr r2, [r4, 0x18]
ldr r0, [r4, 0x20]
adds r1, r0, 0
adds r1, 0x8
movs r3, 0
movs r5, 0x4
ldrsh r0, [r4, r5]
cmp r3, r0
bge _08272B20
mov r12, r3
lsls r5, r1, 2
_08272AAC:
mov r0, r12
str r0, [r2, 0xC]
ldr r0, [r2, 0x14]
str r0, [r2, 0x10]
ldr r0, [r2, 0x18]
str r0, [r2, 0x14]
ldr r0, [r2, 0x1C]
str r0, [r2, 0x18]
adds r1, r5, r2
ldr r0, [r1]
str r0, [r2, 0x1C]
adds r6, r2, 0
adds r6, 0x20
adds r7, r3, 0x1
movs r3, 0x4
_08272ACA:
ldr r0, [r1, 0x4]
str r0, [r1]
ldr r0, [r1, 0x8]
str r0, [r1, 0x4]
ldr r0, [r1, 0xC]
str r0, [r1, 0x8]
ldr r0, [r1, 0x10]
str r0, [r1, 0xC]
ldr r0, [r1, 0x14]
str r0, [r1, 0x10]
ldr r0, [r1, 0x18]
str r0, [r1, 0x14]
ldr r0, [r1, 0x1C]
str r0, [r1, 0x18]
adds r2, r5, r1
ldr r0, [r2]
str r0, [r1, 0x1C]
adds r1, r2, 0
subs r3, 0x1
cmp r3, 0
bge _08272ACA
ldr r0, [r2, 0x4]
str r0, [r2]
ldr r0, [r2, 0x8]
str r0, [r2, 0x4]
ldr r0, [r2, 0xC]
str r0, [r2, 0x8]
ldr r0, [r2, 0x10]
str r0, [r2, 0xC]
ldr r0, [r2, 0x14]
str r0, [r2, 0x10]
ldr r0, [r2, 0x18]
str r0, [r2, 0x14]
ldr r0, [r2, 0x1C]
str r0, [r2, 0x18]
mov r1, r12
str r1, [r2, 0x1C]
adds r2, r6, 0
adds r3, r7, 0
movs r1, 0x4
ldrsh r0, [r4, r1]
cmp r3, r0
blt _08272AAC
_08272B20:
ldr r0, [r4, 0x28]
str r0, [r4, 0x30]
ldr r0, [r4, 0x1C]
str r0, [r4, 0x34]
ldr r0, [r4, 0x2C]
str r0, [r4, 0x38]
adds r1, r4, 0
adds r1, 0x44
movs r0, 0x1
strb r0, [r1]
pop {r4-r7}
pop {r0}
bx r0
thumb_func_end _08272A8C
.align 2, 0 @ Don't pad with nop.

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.include "constants/gba_constants.inc"
.syntax unified
.global Start
.text
.arm
Start: @ 8000000
b Init
.include "asm/rom_header.inc"
.arm
.align 2, 0
.global Init
Init: @ 80000C0
mov r0, PSR_IRQ_MODE
msr cpsr_cf, r0
ldr sp, sp_irq
mov r0, PSR_SYS_MODE
msr cpsr_cf, r0
ldr sp, sp_sys
ldr r1, =INTR_VECTOR
adr r0, IntrMain
str r0, [r1]
ldr r1, =AgbMain
mov lr, pc
bx r1
b Init
.align 2, 0
sp_sys: .word IWRAM_END - 0x100
sp_irq: .word IWRAM_END - 0x60
.pool
.arm
.align 2, 0
.global IntrMain
IntrMain: @ 8000104
mov r3, REG_BASE
add r3, r3, 0x200
ldr r2, [r3, OFFSET_REG_IE - 0x200]
ldrh r1, [r3, OFFSET_REG_IME - 0x200]
mrs r0, spsr
stmdb sp!, {r0-r3,lr}
mov r0, 1
strh r0, [r3, OFFSET_REG_IME - 0x200]
and r1, r2, r2, lsr 16
mov r12, 0
ands r0, r1, INTR_FLAG_SERIAL | INTR_FLAG_TIMER3
bne IntrMain_FoundIntr
add r12, r12, 0x4
ands r0, r1, INTR_FLAG_VBLANK
bne IntrMain_FoundIntr
add r12, r12, 0x4
ands r0, r1, INTR_FLAG_VCOUNT
bne IntrMain_FoundIntr
add r12, r12, 0x4
ands r0, r1, INTR_FLAG_TIMER2
bne IntrMain_FoundIntr
add r12, r12, 0x4
ands r0, r1, INTR_FLAG_TIMER3
bne IntrMain_FoundIntr
add r12, r12, 0x4
ands r0, r1, INTR_FLAG_GAMEPAK
strbne r0, [r3, OFFSET_REG_SOUNDCNT_X - 0x200]
IntrMain_Loop:
bne IntrMain_Loop
IntrMain_FoundIntr:
strh r0, [r3, OFFSET_REG_IF - 0x200]
mov r1, INTR_FLAG_GAMEPAK | INTR_FLAG_SERIAL
bic r2, r2, r0
and r1, r1, r2
strh r1, [r3, OFFSET_REG_IE - 0x200]
mrs r3, cpsr
bic r3, r3, PSR_I_BIT | PSR_F_BIT | PSR_MODE_MASK
orr r3, r3, PSR_SYS_MODE
msr cpsr_cf, r3
ldr r1, =gIntrTable
add r1, r1, r12
ldr r0, [r1]
stmdb sp!, {lr}
adr lr, IntrMain_RetAddr
bx r0
IntrMain_RetAddr:
ldmia sp!, {lr}
mrs r3, cpsr
bic r3, r3, PSR_I_BIT | PSR_F_BIT | PSR_MODE_MASK
orr r3, r3, PSR_I_BIT | PSR_IRQ_MODE
msr cpsr_cf, r3
ldmia sp!, {r0-r3,lr}
strh r2, [r3, OFFSET_REG_IE - 0x200]
strh r1, [r3, OFFSET_REG_IME - 0x200]
msr spsr_cf, r0
bx lr
.pool
.align 2, 0 @ Don't pad with nop.

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asm/libc.s Normal file
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asm/m4a.s Normal file
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asm/macros.inc Normal file
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.include "asm/macros/function.inc"

29
asm/macros/function.inc Normal file
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.macro arm_func_start name
.align 2, 0
.global \name
.arm
.type \name, function
.endm
.macro arm_func_end name
.size \name, .-\name
.endm
.macro thumb_func_start name
.align 2, 0
.global \name
.thumb
.thumb_func
.type \name, function
.endm
.macro non_word_aligned_thumb_func_start name
.global \name
.thumb
.thumb_func
.type \name, function
.endm
.macro thumb_func_end name
.size \name, .-\name
.endm

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asm/rom_header.inc Normal file
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.global RomHeaderNintendoLogo
RomHeaderNintendoLogo:
.byte 0x24,0xff,0xae,0x51,0x69,0x9a,0xa2,0x21
.byte 0x3d,0x84,0x82,0x0a,0x84,0xe4,0x09,0xad
.byte 0x11,0x24,0x8b,0x98,0xc0,0x81,0x7f,0x21
.byte 0xa3,0x52,0xbe,0x19,0x93,0x09,0xce,0x20
.byte 0x10,0x46,0x4a,0x4a,0xf8,0x27,0x31,0xec
.byte 0x58,0xc7,0xe8,0x33,0x82,0xe3,0xce,0xbf
.byte 0x85,0xf4,0xdf,0x94,0xce,0x4b,0x09,0xc1
.byte 0x94,0x56,0x8a,0xc0,0x13,0x72,0xa7,0xfc
.byte 0x9f,0x84,0x4d,0x73,0xa3,0xca,0x9a,0x61
.byte 0x58,0x97,0xa3,0x27,0xfc,0x03,0x98,0x76
.byte 0x23,0x1d,0xc7,0x61,0x03,0x04,0xae,0x56
.byte 0xbf,0x38,0x84,0x00,0x40,0xa7,0x0e,0xfd
.byte 0xff,0x52,0xfe,0x03,0x6f,0x95,0x30,0xf1
.byte 0x97,0xfb,0xc0,0x85,0x60,0xd6,0x80,0x25
.byte 0xa9,0x63,0xbe,0x03,0x01,0x4e,0x38,0xe2
.byte 0xf9,0xa2,0x34,0xff,0xbb,0x3e,0x03,0x44
.byte 0x78,0x00,0x90,0xcb,0x88,0x11,0x3a,0x94
.byte 0x65,0xc0,0x7c,0x63,0x87,0xf0,0x3c,0xaf
.byte 0xd6,0x25,0xe4,0x8b,0x38,0x0a,0xac,0x72
.byte 0x21,0xd4,0xf8,0x07
RomHeaderGameTitle:
.ascii "POKE DUNGEON"
RomHeaderGameCode:
.ascii "B24E"
RomHeaderMakerCode:
.ascii "01"
RomHeaderMagic:
.byte 0x96
RomHeaderMainUnitCode:
.byte 0
RomHeaderDeviceType:
.byte 0
RomHeaderReserved1:
.space 7
RomHeaderSoftwareVersion:
.byte 0
RomHeaderChecksum:
.byte 0xA4
RomHeaderReserved2:
.space 2

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asm/syscall.s Normal file
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.include "asm/macros.inc"
.syntax unified
.text
thumb_func_start CpuSet
CpuSet:
swi 0xB
bx lr
thumb_func_end CpuSet
thumb_func_start SoundBiasReset
SoundBiasReset:
movs r0, 0
swi 0x19
bx lr
thumb_func_end SoundBiasReset
thumb_func_start SoundBiasSet
SoundBiasSet:
movs r0, 0x1
swi 0x19
bx lr
thumb_func_end SoundBiasSet
thumb_func_start VBlankIntrWait
VBlankIntrWait:
movs r2, 0
swi 0x5
bx lr
thumb_func_end VBlankIntrWait
.align 2, 0 @ Don't pad with nop.

490
constants/gba_constants.inc Normal file
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.set PSR_USR_MODE, 0x00000010
.set PSR_FIQ_MODE, 0x00000011
.set PSR_IRQ_MODE, 0x00000012
.set PSR_SVC_MODE, 0x00000013
.set PSR_ABT_MODE, 0x00000017
.set PSR_UND_MODE, 0x0000001b
.set PSR_SYS_MODE, 0x0000001f
.set PSR_MODE_MASK, 0x0000001f
.set PSR_T_BIT, 0x00000020
.set PSR_F_BIT, 0x00000040
.set PSR_I_BIT, 0x00000080
.set EWRAM_START, 0x02000000
.set EWRAM_END, EWRAM_START + 0x40000
.set IWRAM_START, 0x03000000
.set IWRAM_END, IWRAM_START + 0x8000
.set PLTT, 0x5000000
.set BG_PLTT, PLTT
.set OBJ_PLTT, PLTT + 0x200
.set VRAM, 0x6000000
.set BG_VRAM, VRAM
.set OBJ_VRAM0, VRAM + 0x10000 @ text-mode BG
.set OBJ_VRAM1, VRAM + 0x14000 @ bitmap-mode BG
.set OAM, 0x7000000
.set SOUND_INFO_PTR, 0x3007FF0
.set INTR_CHECK, 0x3007FF8
.set INTR_VECTOR, 0x3007FFC
.set INTR_FLAG_VBLANK, 1 << 0
.set INTR_FLAG_HBLANK, 1 << 1
.set INTR_FLAG_VCOUNT, 1 << 2
.set INTR_FLAG_TIMER0, 1 << 3
.set INTR_FLAG_TIMER1, 1 << 4
.set INTR_FLAG_TIMER2, 1 << 5
.set INTR_FLAG_TIMER3, 1 << 6
.set INTR_FLAG_SERIAL, 1 << 7
.set INTR_FLAG_DMA0, 1 << 8
.set INTR_FLAG_DMA1, 1 << 9
.set INTR_FLAG_DMA2, 1 << 10
.set INTR_FLAG_DMA3, 1 << 11
.set INTR_FLAG_KEYPAD, 1 << 12
.set INTR_FLAG_GAMEPAK, 1 << 13
.set VCOUNT_VBLANK, 160
.set TOTAL_SCANLINES, 228
.set REG_BASE, 0x4000000 @ I/O register base address
@ I/O register offsets
.set OFFSET_REG_DISPCNT, 0x0
.set OFFSET_REG_DISPSTAT, 0x4
.set OFFSET_REG_VCOUNT, 0x6
.set OFFSET_REG_BG0CNT, 0x8
.set OFFSET_REG_BG1CNT, 0xa
.set OFFSET_REG_BG2CNT, 0xc
.set OFFSET_REG_BG3CNT, 0xe
.set OFFSET_REG_BG0HOFS, 0x10
.set OFFSET_REG_BG0VOFS, 0x12
.set OFFSET_REG_BG1HOFS, 0x14
.set OFFSET_REG_BG1VOFS, 0x16
.set OFFSET_REG_BG2HOFS, 0x18
.set OFFSET_REG_BG2VOFS, 0x1a
.set OFFSET_REG_BG3HOFS, 0x1c
.set OFFSET_REG_BG3VOFS, 0x1e
.set OFFSET_REG_BG2PA, 0x20
.set OFFSET_REG_BG2PB, 0x22
.set OFFSET_REG_BG2PC, 0x24
.set OFFSET_REG_BG2PD, 0x26
.set OFFSET_REG_BG2X_L, 0x28
.set OFFSET_REG_BG2X_H, 0x2a
.set OFFSET_REG_BG2Y_L, 0x2c
.set OFFSET_REG_BG2Y_H, 0x2e
.set OFFSET_REG_BG3PA, 0x30
.set OFFSET_REG_BG3PB, 0x32
.set OFFSET_REG_BG3PC, 0x34
.set OFFSET_REG_BG3PD, 0x36
.set OFFSET_REG_BG3X_L, 0x38
.set OFFSET_REG_BG3X_H, 0x3a
.set OFFSET_REG_BG3Y_L, 0x3c
.set OFFSET_REG_BG3Y_H, 0x3e
.set OFFSET_REG_WIN0H, 0x40
.set OFFSET_REG_WIN1H, 0x42
.set OFFSET_REG_WIN0V, 0x44
.set OFFSET_REG_WIN1V, 0x46
.set OFFSET_REG_WININ, 0x48
.set OFFSET_REG_WINOUT, 0x4a
.set OFFSET_REG_MOSAIC, 0x4c
.set OFFSET_REG_BLDCNT, 0x50
.set OFFSET_REG_BLDALPHA, 0x52
.set OFFSET_REG_BLDY, 0x54
.set OFFSET_REG_SOUND1CNT, 0x60
.set OFFSET_REG_SOUND1CNT_L, 0x60
.set OFFSET_REG_NR10, 0x60
.set OFFSET_REG_SOUND1CNT_H, 0x62
.set OFFSET_REG_NR11, 0x62
.set OFFSET_REG_NR12, 0x63
.set OFFSET_REG_SOUND1CNT_X, 0x64
.set OFFSET_REG_NR13, 0x64
.set OFFSET_REG_NR14, 0x65
.set OFFSET_REG_SOUND2CNT, 0x68
.set OFFSET_REG_SOUND2CNT_L, 0x68
.set OFFSET_REG_NR21, 0x68
.set OFFSET_REG_NR22, 0x69
.set OFFSET_REG_SOUND2CNT_H, 0x6c
.set OFFSET_REG_NR23, 0x6c
.set OFFSET_REG_NR24, 0x6d
.set OFFSET_REG_SOUND3CNT, 0x70
.set OFFSET_REG_SOUND3CNT_L, 0x70
.set OFFSET_REG_NR30, 0x70
.set OFFSET_REG_SOUND3CNT_H, 0x72
.set OFFSET_REG_NR31, 0x72
.set OFFSET_REG_NR32, 0x73
.set OFFSET_REG_SOUND3CNT_X, 0x74
.set OFFSET_REG_NR33, 0x74
.set OFFSET_REG_NR34, 0x75
.set OFFSET_REG_SOUND4CNT, 0x78
.set OFFSET_REG_SOUND4CNT_L, 0x78
.set OFFSET_REG_NR41, 0x78
.set OFFSET_REG_NR42, 0x79
.set OFFSET_REG_SOUND4CNT_H, 0x7c
.set OFFSET_REG_NR43, 0x7c
.set OFFSET_REG_NR44, 0x7d
.set OFFSET_REG_SOUNDCNT, 0x80
.set OFFSET_REG_SOUNDCNT_L, 0x80
.set OFFSET_REG_NR50, 0x80
.set OFFSET_REG_NR51, 0x81
.set OFFSET_REG_SOUNDCNT_H, 0x82
.set OFFSET_REG_SOUNDCNT_X, 0x84
.set OFFSET_REG_NR52, 0x84
.set OFFSET_REG_SOUNDBIAS, 0x88
.set OFFSET_REG_WAVE_RAM, 0x90
.set OFFSET_REG_WAVE_RAM0, 0x90
.set OFFSET_REG_WAVE_RAM0_L, 0x90
.set OFFSET_REG_WAVE_RAM0_H, 0x92
.set OFFSET_REG_WAVE_RAM1, 0x94
.set OFFSET_REG_WAVE_RAM1_L, 0x94
.set OFFSET_REG_WAVE_RAM1_H, 0x96
.set OFFSET_REG_WAVE_RAM2, 0x98
.set OFFSET_REG_WAVE_RAM2_L, 0x98
.set OFFSET_REG_WAVE_RAM2_H, 0x9a
.set OFFSET_REG_WAVE_RAM3, 0x9c
.set OFFSET_REG_WAVE_RAM3_L, 0x9c
.set OFFSET_REG_WAVE_RAM3_H, 0x9e
.set OFFSET_REG_FIFO, 0xa0
.set OFFSET_REG_FIFO_A, 0xa0
.set OFFSET_REG_FIFO_A_L, 0xa0
.set OFFSET_REG_FIFO_A_H, 0xa2
.set OFFSET_REG_FIFO_B, 0xa4
.set OFFSET_REG_FIFO_B_L, 0xa4
.set OFFSET_REG_FIFO_B_H, 0xa6
.set OFFSET_REG_DMA0, 0xb0
.set OFFSET_REG_DMA0SAD, 0xb0
.set OFFSET_REG_DMA0SAD_L, 0xb0
.set OFFSET_REG_DMA0SAD_H, 0xb2
.set OFFSET_REG_DMA0DAD, 0xb4
.set OFFSET_REG_DMA0DAD_L, 0xb4
.set OFFSET_REG_DMA0DAD_H, 0xb6
.set OFFSET_REG_DMA0CNT, 0xb8
.set OFFSET_REG_DMA0CNT_L, 0xb8
.set OFFSET_REG_DMA0CNT_H, 0xba
.set OFFSET_REG_DMA1, 0xbc
.set OFFSET_REG_DMA1SAD, 0xbc
.set OFFSET_REG_DMA1SAD_L, 0xbc
.set OFFSET_REG_DMA1SAD_H, 0xbe
.set OFFSET_REG_DMA1DAD, 0xc0
.set OFFSET_REG_DMA1DAD_L, 0xc0
.set OFFSET_REG_DMA1DAD_H, 0xc2
.set OFFSET_REG_DMA1CNT, 0xc4
.set OFFSET_REG_DMA1CNT_L, 0xc4
.set OFFSET_REG_DMA1CNT_H, 0xc6
.set OFFSET_REG_DMA2, 0xc8
.set OFFSET_REG_DMA2SAD, 0xc8
.set OFFSET_REG_DMA2SAD_L, 0xc8
.set OFFSET_REG_DMA2SAD_H, 0xca
.set OFFSET_REG_DMA2DAD, 0xcc
.set OFFSET_REG_DMA2DAD_L, 0xcc
.set OFFSET_REG_DMA2DAD_H, 0xce
.set OFFSET_REG_DMA2CNT, 0xd0
.set OFFSET_REG_DMA2CNT_L, 0xd0
.set OFFSET_REG_DMA2CNT_H, 0xd2
.set OFFSET_REG_DMA3, 0xd4
.set OFFSET_REG_DMA3SAD, 0xd4
.set OFFSET_REG_DMA3SAD_L, 0xd4
.set OFFSET_REG_DMA3SAD_H, 0xd6
.set OFFSET_REG_DMA3DAD, 0xd8
.set OFFSET_REG_DMA3DAD_L, 0xd8
.set OFFSET_REG_DMA3DAD_H, 0xda
.set OFFSET_REG_DMA3CNT, 0xdc
.set OFFSET_REG_DMA3CNT_L, 0xdc
.set OFFSET_REG_DMA3CNT_H, 0xde
.set OFFSET_REG_TM0CNT, 0x100
.set OFFSET_REG_TM0CNT_L, 0x100
.set OFFSET_REG_TM0CNT_H, 0x102
.set OFFSET_REG_TM1CNT, 0x104
.set OFFSET_REG_TM1CNT_L, 0x104
.set OFFSET_REG_TM1CNT_H, 0x106
.set OFFSET_REG_TM2CNT, 0x108
.set OFFSET_REG_TM2CNT_L, 0x108
.set OFFSET_REG_TM2CNT_H, 0x10a
.set OFFSET_REG_TM3CNT, 0x10c
.set OFFSET_REG_TM3CNT_L, 0x10c
.set OFFSET_REG_TM3CNT_H, 0x10e
.set OFFSET_REG_SIOCNT, 0x128
.set OFFSET_REG_SIODATA8, 0x12a
.set OFFSET_REG_SIODATA32, 0x120
.set OFFSET_REG_SIOMLT_SEND, 0x12a
.set OFFSET_REG_SIOMLT_RECV, 0x120
.set OFFSET_REG_SIOMULTI0, 0x120
.set OFFSET_REG_SIOMULTI1, 0x122
.set OFFSET_REG_SIOMULTI2, 0x124
.set OFFSET_REG_SIOMULTI3, 0x126
.set OFFSET_REG_KEYINPUT, 0x130
.set OFFSET_REG_KEYCNT, 0x132
.set OFFSET_REG_RCNT, 0x134
.set OFFSET_REG_JOYCNT, 0x140
.set OFFSET_REG_JOYSTAT, 0x158
.set OFFSET_REG_JOY_RECV, 0x150
.set OFFSET_REG_JOY_RECV_L, 0x150
.set OFFSET_REG_JOY_RECV_H, 0x152
.set OFFSET_REG_JOY_TRANS, 0x154
.set OFFSET_REG_JOY_TRANS_L, 0x154
.set OFFSET_REG_JOY_TRANS_H, 0x156
.set OFFSET_REG_IME, 0x208
.set OFFSET_REG_IE, 0x200
.set OFFSET_REG_IF, 0x202
.set OFFSET_REG_WAITCNT, 0x204
@ I/O register addresses
.set REG_DISPCNT, REG_BASE + OFFSET_REG_DISPCNT
.set REG_DISPSTAT, REG_BASE + OFFSET_REG_DISPSTAT
.set REG_VCOUNT, REG_BASE + OFFSET_REG_VCOUNT
.set REG_BG0CNT, REG_BASE + OFFSET_REG_BG0CNT
.set REG_BG1CNT, REG_BASE + OFFSET_REG_BG1CNT
.set REG_BG2CNT, REG_BASE + OFFSET_REG_BG2CNT
.set REG_BG3CNT, REG_BASE + OFFSET_REG_BG3CNT
.set REG_BG0HOFS, REG_BASE + OFFSET_REG_BG0HOFS
.set REG_BG0VOFS, REG_BASE + OFFSET_REG_BG0VOFS
.set REG_BG1HOFS, REG_BASE + OFFSET_REG_BG1HOFS
.set REG_BG1VOFS, REG_BASE + OFFSET_REG_BG1VOFS
.set REG_BG2HOFS, REG_BASE + OFFSET_REG_BG2HOFS
.set REG_BG2VOFS, REG_BASE + OFFSET_REG_BG2VOFS
.set REG_BG3HOFS, REG_BASE + OFFSET_REG_BG3HOFS
.set REG_BG3VOFS, REG_BASE + OFFSET_REG_BG3VOFS
.set REG_BG2PA, REG_BASE + OFFSET_REG_BG2PA
.set REG_BG2PB, REG_BASE + OFFSET_REG_BG2PB
.set REG_BG2PC, REG_BASE + OFFSET_REG_BG2PC
.set REG_BG2PD, REG_BASE + OFFSET_REG_BG2PD
.set REG_BG2X_L, REG_BASE + OFFSET_REG_BG2X_L
.set REG_BG2X_H, REG_BASE + OFFSET_REG_BG2X_H
.set REG_BG2Y_L, REG_BASE + OFFSET_REG_BG2Y_L
.set REG_BG2Y_H, REG_BASE + OFFSET_REG_BG2Y_H
.set REG_BG3PA, REG_BASE + OFFSET_REG_BG3PA
.set REG_BG3PB, REG_BASE + OFFSET_REG_BG3PB
.set REG_BG3PC, REG_BASE + OFFSET_REG_BG3PC
.set REG_BG3PD, REG_BASE + OFFSET_REG_BG3PD
.set REG_BG3X_L, REG_BASE + OFFSET_REG_BG3X_L
.set REG_BG3X_H, REG_BASE + OFFSET_REG_BG3X_H
.set REG_BG3Y_L, REG_BASE + OFFSET_REG_BG3Y_L
.set REG_BG3Y_H, REG_BASE + OFFSET_REG_BG3Y_H
.set REG_WIN0H, REG_BASE + OFFSET_REG_WIN0H
.set REG_WIN1H, REG_BASE + OFFSET_REG_WIN1H
.set REG_WIN0V, REG_BASE + OFFSET_REG_WIN0V
.set REG_WIN1V, REG_BASE + OFFSET_REG_WIN1V
.set REG_WININ, REG_BASE + OFFSET_REG_WININ
.set REG_WINOUT, REG_BASE + OFFSET_REG_WINOUT
.set REG_MOSAIC, REG_BASE + OFFSET_REG_MOSAIC
.set REG_BLDCNT, REG_BASE + OFFSET_REG_BLDCNT
.set REG_BLDALPHA, REG_BASE + OFFSET_REG_BLDALPHA
.set REG_BLDY, REG_BASE + OFFSET_REG_BLDY
.set REG_SOUND1CNT, REG_BASE + OFFSET_REG_SOUND1CNT
.set REG_SOUND1CNT_L, REG_BASE + OFFSET_REG_SOUND1CNT_L
.set REG_NR10, REG_BASE + OFFSET_REG_NR10
.set REG_SOUND1CNT_H, REG_BASE + OFFSET_REG_SOUND1CNT_H
.set REG_NR11, REG_BASE + OFFSET_REG_NR11
.set REG_NR12, REG_BASE + OFFSET_REG_NR12
.set REG_SOUND1CNT_X, REG_BASE + OFFSET_REG_SOUND1CNT_X
.set REG_NR13, REG_BASE + OFFSET_REG_NR13
.set REG_NR14, REG_BASE + OFFSET_REG_NR14
.set REG_SOUND2CNT, REG_BASE + OFFSET_REG_SOUND2CNT
.set REG_SOUND2CNT_L, REG_BASE + OFFSET_REG_SOUND2CNT_L
.set REG_NR21, REG_BASE + OFFSET_REG_NR21
.set REG_NR22, REG_BASE + OFFSET_REG_NR22
.set REG_SOUND2CNT_H, REG_BASE + OFFSET_REG_SOUND2CNT_H
.set REG_NR23, REG_BASE + OFFSET_REG_NR23
.set REG_NR24, REG_BASE + OFFSET_REG_NR24
.set REG_SOUND3CNT, REG_BASE + OFFSET_REG_SOUND3CNT
.set REG_SOUND3CNT_L, REG_BASE + OFFSET_REG_SOUND3CNT_L
.set REG_NR30, REG_BASE + OFFSET_REG_NR30
.set REG_SOUND3CNT_H, REG_BASE + OFFSET_REG_SOUND3CNT_H
.set REG_NR31, REG_BASE + OFFSET_REG_NR31
.set REG_NR32, REG_BASE + OFFSET_REG_NR32
.set REG_SOUND3CNT_X, REG_BASE + OFFSET_REG_SOUND3CNT_X
.set REG_NR33, REG_BASE + OFFSET_REG_NR33
.set REG_NR34, REG_BASE + OFFSET_REG_NR34
.set REG_SOUND4CNT, REG_BASE + OFFSET_REG_SOUND4CNT
.set REG_SOUND4CNT_L, REG_BASE + OFFSET_REG_SOUND4CNT_L
.set REG_NR41, REG_BASE + OFFSET_REG_NR41
.set REG_NR42, REG_BASE + OFFSET_REG_NR42
.set REG_SOUND4CNT_H, REG_BASE + OFFSET_REG_SOUND4CNT_H
.set REG_NR43, REG_BASE + OFFSET_REG_NR43
.set REG_NR44, REG_BASE + OFFSET_REG_NR44
.set REG_SOUNDCNT, REG_BASE + OFFSET_REG_SOUNDCNT
.set REG_SOUNDCNT_L, REG_BASE + OFFSET_REG_SOUNDCNT_L
.set REG_NR50, REG_BASE + OFFSET_REG_NR50
.set REG_NR51, REG_BASE + OFFSET_REG_NR51
.set REG_SOUNDCNT_H, REG_BASE + OFFSET_REG_SOUNDCNT_H
.set REG_SOUNDCNT_X, REG_BASE + OFFSET_REG_SOUNDCNT_X
.set REG_NR52, REG_BASE + OFFSET_REG_NR52
.set REG_SOUNDBIAS, REG_BASE + OFFSET_REG_SOUNDBIAS
.set REG_WAVE_RAM, REG_BASE + OFFSET_REG_WAVE_RAM
.set REG_WAVE_RAM0, REG_BASE + OFFSET_REG_WAVE_RAM0
.set REG_WAVE_RAM0_L, REG_BASE + OFFSET_REG_WAVE_RAM0_L
.set REG_WAVE_RAM0_H, REG_BASE + OFFSET_REG_WAVE_RAM0_H
.set REG_WAVE_RAM1, REG_BASE + OFFSET_REG_WAVE_RAM1
.set REG_WAVE_RAM1_L, REG_BASE + OFFSET_REG_WAVE_RAM1_L
.set REG_WAVE_RAM1_H, REG_BASE + OFFSET_REG_WAVE_RAM1_H
.set REG_WAVE_RAM2, REG_BASE + OFFSET_REG_WAVE_RAM2
.set REG_WAVE_RAM2_L, REG_BASE + OFFSET_REG_WAVE_RAM2_L
.set REG_WAVE_RAM2_H, REG_BASE + OFFSET_REG_WAVE_RAM2_H
.set REG_WAVE_RAM3, REG_BASE + OFFSET_REG_WAVE_RAM3
.set REG_WAVE_RAM3_L, REG_BASE + OFFSET_REG_WAVE_RAM3_L
.set REG_WAVE_RAM3_H, REG_BASE + OFFSET_REG_WAVE_RAM3_H
.set REG_FIFO, REG_BASE + OFFSET_REG_FIFO
.set REG_FIFO_A, REG_BASE + OFFSET_REG_FIFO_A
.set REG_FIFO_A_L, REG_BASE + OFFSET_REG_FIFO_A_L
.set REG_FIFO_A_H, REG_BASE + OFFSET_REG_FIFO_A_H
.set REG_FIFO_B, REG_BASE + OFFSET_REG_FIFO_B
.set REG_FIFO_B_L, REG_BASE + OFFSET_REG_FIFO_B_L
.set REG_FIFO_B_H, REG_BASE + OFFSET_REG_FIFO_B_H
.set REG_DMA0, REG_BASE + OFFSET_REG_DMA0
.set REG_DMA0SAD, REG_BASE + OFFSET_REG_DMA0SAD
.set REG_DMA0SAD_L, REG_BASE + OFFSET_REG_DMA0SAD_L
.set REG_DMA0SAD_H, REG_BASE + OFFSET_REG_DMA0SAD_H
.set REG_DMA0DAD, REG_BASE + OFFSET_REG_DMA0DAD
.set REG_DMA0DAD_L, REG_BASE + OFFSET_REG_DMA0DAD_L
.set REG_DMA0DAD_H, REG_BASE + OFFSET_REG_DMA0DAD_H
.set REG_DMA0CNT, REG_BASE + OFFSET_REG_DMA0CNT
.set REG_DMA0CNT_L, REG_BASE + OFFSET_REG_DMA0CNT_L
.set REG_DMA0CNT_H, REG_BASE + OFFSET_REG_DMA0CNT_H
.set REG_DMA1, REG_BASE + OFFSET_REG_DMA1
.set REG_DMA1SAD, REG_BASE + OFFSET_REG_DMA1SAD
.set REG_DMA1SAD_L, REG_BASE + OFFSET_REG_DMA1SAD_L
.set REG_DMA1SAD_H, REG_BASE + OFFSET_REG_DMA1SAD_H
.set REG_DMA1DAD, REG_BASE + OFFSET_REG_DMA1DAD
.set REG_DMA1DAD_L, REG_BASE + OFFSET_REG_DMA1DAD_L
.set REG_DMA1DAD_H, REG_BASE + OFFSET_REG_DMA1DAD_H
.set REG_DMA1CNT, REG_BASE + OFFSET_REG_DMA1CNT
.set REG_DMA1CNT_L, REG_BASE + OFFSET_REG_DMA1CNT_L
.set REG_DMA1CNT_H, REG_BASE + OFFSET_REG_DMA1CNT_H
.set REG_DMA2, REG_BASE + OFFSET_REG_DMA2
.set REG_DMA2SAD, REG_BASE + OFFSET_REG_DMA2SAD
.set REG_DMA2SAD_L, REG_BASE + OFFSET_REG_DMA2SAD_L
.set REG_DMA2SAD_H, REG_BASE + OFFSET_REG_DMA2SAD_H
.set REG_DMA2DAD, REG_BASE + OFFSET_REG_DMA2DAD
.set REG_DMA2DAD_L, REG_BASE + OFFSET_REG_DMA2DAD_L
.set REG_DMA2DAD_H, REG_BASE + OFFSET_REG_DMA2DAD_H
.set REG_DMA2CNT, REG_BASE + OFFSET_REG_DMA2CNT
.set REG_DMA2CNT_L, REG_BASE + OFFSET_REG_DMA2CNT_L
.set REG_DMA2CNT_H, REG_BASE + OFFSET_REG_DMA2CNT_H
.set REG_DMA3, REG_BASE + OFFSET_REG_DMA3
.set REG_DMA3SAD, REG_BASE + OFFSET_REG_DMA3SAD
.set REG_DMA3SAD_L, REG_BASE + OFFSET_REG_DMA3SAD_L
.set REG_DMA3SAD_H, REG_BASE + OFFSET_REG_DMA3SAD_H
.set REG_DMA3DAD, REG_BASE + OFFSET_REG_DMA3DAD
.set REG_DMA3DAD_L, REG_BASE + OFFSET_REG_DMA3DAD_L
.set REG_DMA3DAD_H, REG_BASE + OFFSET_REG_DMA3DAD_H
.set REG_DMA3CNT, REG_BASE + OFFSET_REG_DMA3CNT
.set REG_DMA3CNT_L, REG_BASE + OFFSET_REG_DMA3CNT_L
.set REG_DMA3CNT_H, REG_BASE + OFFSET_REG_DMA3CNT_H
.set REG_TM0CNT, REG_BASE + OFFSET_REG_TM0CNT
.set REG_TM0CNT_L, REG_BASE + OFFSET_REG_TM0CNT_L
.set REG_TM0CNT_H, REG_BASE + OFFSET_REG_TM0CNT_H
.set REG_TM1CNT, REG_BASE + OFFSET_REG_TM1CNT
.set REG_TM1CNT_L, REG_BASE + OFFSET_REG_TM1CNT_L
.set REG_TM1CNT_H, REG_BASE + OFFSET_REG_TM1CNT_H
.set REG_TM2CNT, REG_BASE + OFFSET_REG_TM2CNT
.set REG_TM2CNT_L, REG_BASE + OFFSET_REG_TM2CNT_L
.set REG_TM2CNT_H, REG_BASE + OFFSET_REG_TM2CNT_H
.set REG_TM3CNT, REG_BASE + OFFSET_REG_TM3CNT
.set REG_TM3CNT_L, REG_BASE + OFFSET_REG_TM3CNT_L
.set REG_TM3CNT_H, REG_BASE + OFFSET_REG_TM3CNT_H
.set REG_SIOCNT, REG_BASE + OFFSET_REG_SIOCNT
.set REG_SIODATA8, REG_BASE + OFFSET_REG_SIODATA8
.set REG_SIODATA32, REG_BASE + OFFSET_REG_SIODATA32
.set REG_SIOMLT_SEND, REG_BASE + OFFSET_REG_SIOMLT_SEND
.set REG_SIOMLT_RECV, REG_BASE + OFFSET_REG_SIOMLT_RECV
.set REG_SIOMULTI0, REG_BASE + OFFSET_REG_SIOMULTI0
.set REG_SIOMULTI1, REG_BASE + OFFSET_REG_SIOMULTI1
.set REG_SIOMULTI2, REG_BASE + OFFSET_REG_SIOMULTI2
.set REG_SIOMULTI3, REG_BASE + OFFSET_REG_SIOMULTI3
.set REG_KEYINPUT, REG_BASE + OFFSET_REG_KEYINPUT
.set REG_KEYCNT, REG_BASE + OFFSET_REG_KEYCNT
.set REG_RCNT, REG_BASE + OFFSET_REG_RCNT
.set REG_JOYCNT, REG_BASE + OFFSET_REG_JOYCNT
.set REG_JOYSTAT, REG_BASE + OFFSET_REG_JOYSTAT
.set REG_JOY_RECV, REG_BASE + OFFSET_REG_JOY_RECV
.set REG_JOY_RECV_L, REG_BASE + OFFSET_REG_JOY_RECV_L
.set REG_JOY_RECV_H, REG_BASE + OFFSET_REG_JOY_RECV_H
.set REG_JOY_TRANS, REG_BASE + OFFSET_REG_JOY_TRANS
.set REG_JOY_TRANS_L, REG_BASE + OFFSET_REG_JOY_TRANS_L
.set REG_JOY_TRANS_H, REG_BASE + OFFSET_REG_JOY_TRANS_H
.set REG_IME, REG_BASE + OFFSET_REG_IME
.set REG_IE, REG_BASE + OFFSET_REG_IE
.set REG_IF, REG_BASE + OFFSET_REG_IF
.set REG_WAITCNT, REG_BASE + OFFSET_REG_WAITCNT
@ DMA register constants
.set DMA_DEST_INC, 0x0000
.set DMA_DEST_DEC, 0x0020
.set DMA_DEST_FIXED, 0x0040
.set DMA_DEST_RELOAD, 0x0060
.set DMA_SRC_INC, 0x0000
.set DMA_SRC_DEC, 0x0080
.set DMA_SRC_FIXED, 0x0100
.set DMA_REPEAT, 0x0200
.set DMA_16BIT, 0x0000
.set DMA_32BIT, 0x0400
.set DMA_DREQ_ON, 0x0800
.set DMA_START_NOW, 0x0000
.set DMA_START_VBLANK, 0x1000
.set DMA_START_HBLANK, 0x2000
.set DMA_START_SPECIAL, 0x3000
.set DMA_INTR_ENABLE, 0x4000
.set DMA_ENABLE, 0x8000
@ OAM attribute constants
.set OAM_OBJ_NORMAL, 0x00000000
.set OAM_OBJ_BLEND, 0x00000400
.set OAM_OBJ_WINDOW, 0x00000800
.set OAM_AFFINE_NONE, 0x00000000
.set OAM_AFFINE_NORMAL_SIZE, 0x00000100
.set OAM_OBJ_DISABLED, 0x00000200
.set OAM_AFFINE_DOUBLE_SIZE, 0x00000300
.set OAM_MOSAIC_OFF, 0x00000000
.set OAM_MOSAIC_ON, 0x00001000
.set OAM_4BPP, 0x00000000
.set OAM_8BPP, 0x00002000
.set OAM_H_FLIP, 0x10000000
.set OAM_V_FLIP, 0x20000000
.set OAM_SQUARE, 0x00000000
.set OAM_H_RECTANGLE, 0x00004000
.set OAM_V_RECTANGLE, 0x00008000
.set OAM_SIZE_0, 0x00000000
.set OAM_SIZE_1, 0x40000000
.set OAM_SIZE_2, 0x80000000
.set OAM_SIZE_3, 0xc0000000
.set OAM_SIZE_8x8, OAM_SIZE_0 | OAM_SQUARE
.set OAM_SIZE_16x16, OAM_SIZE_1 | OAM_SQUARE
.set OAM_SIZE_32x32, OAM_SIZE_2 | OAM_SQUARE
.set OAM_SIZE_64x64, OAM_SIZE_3 | OAM_SQUARE
.set OAM_SIZE_16x8, OAM_SIZE_0 | OAM_H_RECTANGLE
.set OAM_SIZE_32x8, OAM_SIZE_1 | OAM_H_RECTANGLE
.set OAM_SIZE_32x16, OAM_SIZE_2 | OAM_H_RECTANGLE
.set OAM_SIZE_64x32, OAM_SIZE_3 | OAM_H_RECTANGLE
.set OAM_SIZE_8x16, OAM_SIZE_0 | OAM_V_RECTANGLE
.set OAM_SIZE_8x32, OAM_SIZE_1 | OAM_V_RECTANGLE
.set OAM_SIZE_16x32, OAM_SIZE_2 | OAM_V_RECTANGLE
.set OAM_SIZE_32x64, OAM_SIZE_3 | OAM_V_RECTANGLE

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5
data/data_8270000.s Normal file
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.section .rodata
.global gUnknown_8270000
gUnknown_8270000: @ 8270000
.incbin "baserom.gba", 0x270000, 0x2724

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.section .rodata
.global gUnknown_826FDE4
gUnknown_826FDE4: @ 826FDE4
.incbin "baserom.gba", 0x26FDE4, 0x10
.global gUnknown_826FDF4
gUnknown_826FDF4: @ 826FDF4
.incbin "baserom.gba", 0x26FDF4, 0x10
.global gUnknown_826FE04
gUnknown_826FE04: @ 826FE04
.incbin "baserom.gba", 0x26FE04, 0x4
.global gUnknown_826FE08
gUnknown_826FE08: @ 826FE08
.incbin "baserom.gba", 0x26FE08, 0x4
.global gUnknown_826FE0C
gUnknown_826FE0C: @ 826FE0C
.incbin "baserom.gba", 0x26FE0C, 0x14
.global gUnknown_826FE20
gUnknown_826FE20: @ 826FE20
.incbin "baserom.gba", 0x26FE20, 0x8
.global gUnknown_826FE28
gUnknown_826FE28: @ 826FE28
.incbin "baserom.gba", 0x26FE28, 0x14
.global gUnknown_826FE3C
gUnknown_826FE3C: @ 826FE3C
.incbin "baserom.gba", 0x26FE3C, 0x1C
.global gUnknown_826FE58
gUnknown_826FE58: @ 826FE58
.incbin "baserom.gba", 0x26FE58, 0x4
.global gUnknown_826FE5C
gUnknown_826FE5C: @ 826FE5C
.incbin "baserom.gba", 0x26FE5C, 0x4
.global gUnknown_826FE60
gUnknown_826FE60: @ 826FE60
.incbin "baserom.gba", 0x26FE60, 0xC
.global gUnknown_826FE6C
gUnknown_826FE6C: @ 826FE6C
.incbin "baserom.gba", 0x26FE6C, 0x4
.global gUnknown_826FE70
gUnknown_826FE70: @ 826FE70
.incbin "baserom.gba", 0x26FE70, 0x8
.global gUnknown_826FE78
gUnknown_826FE78: @ 826FE78
.incbin "baserom.gba", 0x26FE78, 0x30
.global gUnknown_826FEA8
gUnknown_826FEA8: @ 826FEA8
.incbin "baserom.gba", 0x26FEA8, 0x8
.global gUnknown_826FEB0
gUnknown_826FEB0: @ 826FEB0
.incbin "baserom.gba", 0x26FEB0, 0x4
.global gUnknown_826FEB4
gUnknown_826FEB4: @ 826FEB4
.incbin "baserom.gba", 0x26FEB4, 0xC
.global gUnknown_826FEC0
gUnknown_826FEC0: @ 826FEC0
.incbin "baserom.gba", 0x26FEC0, 0xC8
.global gUnknown_826FF88
gUnknown_826FF88: @ 826FF88
.incbin "baserom.gba", 0x26FF88, 0x50
.global gUnknown_826FFD8
gUnknown_826FFD8: @ 826FFD8
.incbin "baserom.gba", 0x26FFD8, 0x4
.global gUnknown_826FFDC
gUnknown_826FFDC: @ 826FFDC
.incbin "baserom.gba", 0x26FFDC, 0x24

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.section .rodata
.incbin "baserom.gba", 0x300000, 0x500
.global gUnknown_8300500
gUnknown_8300500: @ 8300500
.incbin "baserom.gba", 0x300500, 0x7FB00
.global gUnknown_8380000
gUnknown_8380000: @ 8380000
.incbin "baserom.gba", 0x380000, 0x30000
.global gUnknown_83B0000
gUnknown_83B0000: @ 83B0000
.incbin "baserom.gba", 0x3B0000, 0x160000
.global gUnknown_8510000
gUnknown_8510000: @ 8510000
.incbin "baserom.gba", 0x510000

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#ifndef GUARD_GBA_DEFINES
#define GUARD_GBA_DEFINES
#include <stddef.h>
#define TRUE 1
#define FALSE 0
#define IWRAM_DATA __attribute__((section("iwram_data")))
#define EWRAM_DATA __attribute__((section("ewram_data")))
#define ALIGNED(n) __attribute__((aligned(n)))
#define SOUND_INFO_PTR (*(struct SoundInfo **)0x3007FF0)
#define INTR_CHECK (*(u16 *)0x3007FF8)
#define INTR_VECTOR (*(void **)0x3007FFC)
#define PLTT 0x5000000
#define PLTT_SIZE 0x400
#define BG_PLTT PLTT
#define BG_PLTT_SIZE 0x200
#define OBJ_PLTT (PLTT + 0x200)
#define OBJ_PLTT_SIZE 0x200
#define VRAM 0x6000000
#define VRAM_SIZE 0x18000
#define BG_VRAM VRAM
#define BG_VRAM_SIZE 0x10000
#define BG_CHAR_ADDR(n) (void *)(BG_VRAM + (0x4000 * (n)))
#define BG_SCREEN_ADDR(n) (void *)(BG_VRAM + (0x800 * (n)))
#define BG_TILE_ADDR(n) (void *)(BG_VRAM + (0x80 * (n)))
// text-mode BG
#define OBJ_VRAM0 (void *)(VRAM + 0x10000)
#define OBJ_VRAM0_SIZE 0x8000
// bitmap-mode BG
#define OBJ_VRAM1 (void *)(VRAM + 0x14000)
#define OBJ_VRAM1_SIZE 0x4000
#define OAM 0x7000000
#define OAM_SIZE 0x400
#define DISPLAY_WIDTH 240
#define DISPLAY_HEIGHT 160
#define TILE_SIZE_4BPP 32
#define TILE_SIZE_8BPP 64
#define TOTAL_OBJ_TILE_COUNT 1024
#define RGB(r, g, b) ((r) | ((g) << 5) | ((b) << 10))
#define RGB_BLACK RGB(0, 0, 0)
#define RGB_WHITE RGB(31, 31, 31)
#define WIN_RANGE(a, b) (((a) << 8) | (b))
#endif // GUARD_GBA_DEFINES

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#ifndef GUARD_GBA_FLASH_INTERNAL_H
#define GUARD_GBA_FLASH_INTERNAL_H
#define FLASH_BASE ((u8 *)0xE000000)
#define FLASH_WRITE(addr, data) ((*(vu8 *)(FLASH_BASE + (addr))) = (data))
#define FLASH_ROM_SIZE_1M 131072 // 1 megabit ROM
#define SECTORS_PER_BANK 16
struct FlashSector
{
u32 size;
u8 shift;
u16 count;
u16 top;
};
struct FlashType {
u32 romSize;
struct FlashSector sector;
u16 wait[2]; // game pak bus read/write wait
// TODO: add support for anonymous unions/structs if possible
union {
struct {
u8 makerId;
u8 deviceId;
} separate;
u16 joined;
} ids;
};
struct FlashSetupInfo
{
u16 (*programFlashSector)(u16, u8 *);
u16 (*eraseFlashChip)(void);
u16 (*eraseFlashSector)(u16);
u16 (*waitForFlashWrite)(u8, u8 *, u8);
const u16 *maxTime;
struct FlashType type;
};
extern u16 gFlashNumRemainingBytes;
extern u16 (*ProgramFlashSector)(u16, u8 *);
extern u16 (*EraseFlashChip)(void);
extern u16 (*EraseFlashSector)(u16);
extern u16 (*WaitForFlashWrite)(u8, u8 *, u8);
extern const u16 *gFlashMaxTime;
extern const struct FlashType *gFlash;
extern u8 (*PollFlashStatus)(u8 *);
extern u8 gFlashTimeoutFlag;
extern const struct FlashSetupInfo MX29L010;
extern const struct FlashSetupInfo LE26FV10N1TS;
extern const struct FlashSetupInfo DefaultFlash;
void SwitchFlashBank(u8 bankNum);
u16 ReadFlashId(void);
void StartFlashTimer(u8 phase);
void SetReadFlash1(u16 *dest);
void StopFlashTimer(void);
u16 WaitForFlashWrite_Common(u8 phase, u8 *addr, u8 lastData);
u16 EraseFlashChip_MX(void);
u16 EraseFlashSector_MX(u16 sectorNum);
u16 ProgramFlashSector_MX(u16 sectorNum, u8 *src);
#endif // GUARD_GBA_FLASH_INTERNAL_H

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#ifndef GUARD_GBA_GBA_H
#define GUARD_GBA_GBA_H
#include "gba/defines.h"
#include "gba/io_reg.h"
#include "gba/types.h"
#include "gba/multiboot.h"
#include "gba/syscall.h"
#include "gba/macro.h"
#endif // GUARD_GBA_GBA_H

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#ifndef GUARD_GBA_IO_REG_H
#define GUARD_GBA_IO_REG_H
#define REG_BASE 0x4000000 // I/O register base address
// I/O register offsets
#define REG_OFFSET_DISPCNT 0x0
#define REG_OFFSET_DISPSTAT 0x4
#define REG_OFFSET_VCOUNT 0x6
#define REG_OFFSET_BG0CNT 0x8
#define REG_OFFSET_BG1CNT 0xa
#define REG_OFFSET_BG2CNT 0xc
#define REG_OFFSET_BG3CNT 0xe
#define REG_OFFSET_BG0HOFS 0x10
#define REG_OFFSET_BG0VOFS 0x12
#define REG_OFFSET_BG1HOFS 0x14
#define REG_OFFSET_BG1VOFS 0x16
#define REG_OFFSET_BG2HOFS 0x18
#define REG_OFFSET_BG2VOFS 0x1a
#define REG_OFFSET_BG3HOFS 0x1c
#define REG_OFFSET_BG3VOFS 0x1e
#define REG_OFFSET_BG2PA 0x20
#define REG_OFFSET_BG2PB 0x22
#define REG_OFFSET_BG2PC 0x24
#define REG_OFFSET_BG2PD 0x26
#define REG_OFFSET_BG2X 0x28
#define REG_OFFSET_BG2X_L 0x28
#define REG_OFFSET_BG2X_H 0x2a
#define REG_OFFSET_BG2Y 0x2c
#define REG_OFFSET_BG2Y_L 0x2c
#define REG_OFFSET_BG2Y_H 0x2e
#define REG_OFFSET_BG3PA 0x30
#define REG_OFFSET_BG3PB 0x32
#define REG_OFFSET_BG3PC 0x34
#define REG_OFFSET_BG3PD 0x36
#define REG_OFFSET_BG3X 0x38
#define REG_OFFSET_BG3X_L 0x38
#define REG_OFFSET_BG3X_H 0x3a
#define REG_OFFSET_BG3Y 0x3c
#define REG_OFFSET_BG3Y_L 0x3c
#define REG_OFFSET_BG3Y_H 0x3e
#define REG_OFFSET_WIN0H 0x40
#define REG_OFFSET_WIN1H 0x42
#define REG_OFFSET_WIN0V 0x44
#define REG_OFFSET_WIN1V 0x46
#define REG_OFFSET_WININ 0x48
#define REG_OFFSET_WINOUT 0x4a
#define REG_OFFSET_MOSAIC 0x4c
#define REG_OFFSET_BLDCNT 0x50
#define REG_OFFSET_BLDALPHA 0x52
#define REG_OFFSET_BLDY 0x54
#define REG_OFFSET_SOUND1CNT_L 0x60
#define REG_OFFSET_NR10 0x60
#define REG_OFFSET_SOUND1CNT_H 0x62
#define REG_OFFSET_NR11 0x62
#define REG_OFFSET_NR12 0x63
#define REG_OFFSET_SOUND1CNT_X 0x64
#define REG_OFFSET_NR13 0x64
#define REG_OFFSET_NR14 0x65
#define REG_OFFSET_SOUND2CNT_L 0x68
#define REG_OFFSET_NR21 0x68
#define REG_OFFSET_NR22 0x69
#define REG_OFFSET_SOUND2CNT_H 0x6c
#define REG_OFFSET_NR23 0x6c
#define REG_OFFSET_NR24 0x6d
#define REG_OFFSET_SOUND3CNT_L 0x70
#define REG_OFFSET_NR30 0x70
#define REG_OFFSET_SOUND3CNT_H 0x72
#define REG_OFFSET_NR31 0x72
#define REG_OFFSET_NR32 0x73
#define REG_OFFSET_SOUND3CNT_X 0x74
#define REG_OFFSET_NR33 0x74
#define REG_OFFSET_NR34 0x75
#define REG_OFFSET_SOUND4CNT_L 0x78
#define REG_OFFSET_NR41 0x78
#define REG_OFFSET_NR42 0x79
#define REG_OFFSET_SOUND4CNT_H 0x7c
#define REG_OFFSET_NR43 0x7c
#define REG_OFFSET_NR44 0x7d
#define REG_OFFSET_SOUNDCNT_L 0x80
#define REG_OFFSET_NR50 0x80
#define REG_OFFSET_NR51 0x81
#define REG_OFFSET_SOUNDCNT_H 0x82
#define REG_OFFSET_SOUNDCNT_X 0x84
#define REG_OFFSET_NR52 0x84
#define REG_OFFSET_SOUNDBIAS 0x88
#define REG_OFFSET_SOUNDBIAS_L 0x88
#define REG_OFFSET_SOUNDBIAS_H 0x89
#define REG_OFFSET_WAVE_RAM0 0x90
#define REG_OFFSET_WAVE_RAM1 0x94
#define REG_OFFSET_WAVE_RAM2 0x98
#define REG_OFFSET_WAVE_RAM3 0x9c
#define REG_OFFSET_FIFO_A 0xa0
#define REG_OFFSET_FIFO_B 0xa4
#define REG_OFFSET_DMA0 0xb0
#define REG_OFFSET_DMA0SAD 0xb0
#define REG_OFFSET_DMA0SAD_L 0xb0
#define REG_OFFSET_DMA0SAD_H 0xb2
#define REG_OFFSET_DMA0DAD 0xb4
#define REG_OFFSET_DMA0DAD_L 0xb4
#define REG_OFFSET_DMA0DAD_H 0xb6
#define REG_OFFSET_DMA0CNT 0xb8
#define REG_OFFSET_DMA0CNT_L 0xb8
#define REG_OFFSET_DMA0CNT_H 0xba
#define REG_OFFSET_DMA1 0xbc
#define REG_OFFSET_DMA1SAD 0xbc
#define REG_OFFSET_DMA1SAD_L 0xbc
#define REG_OFFSET_DMA1SAD_H 0xbe
#define REG_OFFSET_DMA1DAD 0xc0
#define REG_OFFSET_DMA1DAD_L 0xc0
#define REG_OFFSET_DMA1DAD_H 0xc2
#define REG_OFFSET_DMA1CNT 0xc4
#define REG_OFFSET_DMA1CNT_L 0xc4
#define REG_OFFSET_DMA1CNT_H 0xc6
#define REG_OFFSET_DMA2 0xc8
#define REG_OFFSET_DMA2SAD 0xc8
#define REG_OFFSET_DMA2SAD_L 0xc8
#define REG_OFFSET_DMA2SAD_H 0xca
#define REG_OFFSET_DMA2DAD 0xcc
#define REG_OFFSET_DMA2DAD_L 0xcc
#define REG_OFFSET_DMA2DAD_H 0xce
#define REG_OFFSET_DMA2CNT 0xd0
#define REG_OFFSET_DMA2CNT_L 0xd0
#define REG_OFFSET_DMA2CNT_H 0xd2
#define REG_OFFSET_DMA3 0xd4
#define REG_OFFSET_DMA3SAD 0xd4
#define REG_OFFSET_DMA3SAD_L 0xd4
#define REG_OFFSET_DMA3SAD_H 0xd6
#define REG_OFFSET_DMA3DAD 0xd8
#define REG_OFFSET_DMA3DAD_L 0xd8
#define REG_OFFSET_DMA3DAD_H 0xda
#define REG_OFFSET_DMA3CNT 0xdc
#define REG_OFFSET_DMA3CNT_L 0xdc
#define REG_OFFSET_DMA3CNT_H 0xde
#define REG_OFFSET_TMCNT 0x100
#define REG_OFFSET_TM0CNT 0x100
#define REG_OFFSET_TM0CNT_L 0x100
#define REG_OFFSET_TM0CNT_H 0x102
#define REG_OFFSET_TM1CNT 0x104
#define REG_OFFSET_TM1CNT_L 0x104
#define REG_OFFSET_TM1CNT_H 0x106
#define REG_OFFSET_TM2CNT 0x108
#define REG_OFFSET_TM2CNT_L 0x108
#define REG_OFFSET_TM2CNT_H 0x10a
#define REG_OFFSET_TM3CNT 0x10c
#define REG_OFFSET_TM3CNT_L 0x10c
#define REG_OFFSET_TM3CNT_H 0x10e
#define REG_OFFSET_SIOCNT 0x128
#define REG_OFFSET_SIODATA8 0x12a
#define REG_OFFSET_SIODATA32 0x120
#define REG_OFFSET_SIOMLT_SEND 0x12a
#define REG_OFFSET_SIOMLT_RECV 0x120
#define REG_OFFSET_SIOMULTI0 0x120
#define REG_OFFSET_SIOMULTI1 0x122
#define REG_OFFSET_SIOMULTI2 0x124
#define REG_OFFSET_SIOMULTI3 0x126
#define REG_OFFSET_KEYINPUT 0x130
#define REG_OFFSET_KEYCNT 0x132
#define REG_OFFSET_RCNT 0x134
#define REG_OFFSET_JOYCNT 0x140
#define REG_OFFSET_JOYSTAT 0x158
#define REG_OFFSET_JOY_RECV 0x150
#define REG_OFFSET_JOY_RECV_L 0x150
#define REG_OFFSET_JOY_RECV_H 0x152
#define REG_OFFSET_JOY_TRANS 0x154
#define REG_OFFSET_JOY_TRANS_L 0x154
#define REG_OFFSET_JOY_TRANS_H 0x156
#define REG_OFFSET_IME 0x208
#define REG_OFFSET_IE 0x200
#define REG_OFFSET_IF 0x202
#define REG_OFFSET_WAITCNT 0x204
// I/O register addresses
#define REG_ADDR_DISPCNT (REG_BASE + REG_OFFSET_DISPCNT)
#define REG_ADDR_DISPSTAT (REG_BASE + REG_OFFSET_DISPSTAT)
#define REG_ADDR_VCOUNT (REG_BASE + REG_OFFSET_VCOUNT)
#define REG_ADDR_BG0CNT (REG_BASE + REG_OFFSET_BG0CNT)
#define REG_ADDR_BG1CNT (REG_BASE + REG_OFFSET_BG1CNT)
#define REG_ADDR_BG2CNT (REG_BASE + REG_OFFSET_BG2CNT)
#define REG_ADDR_BG3CNT (REG_BASE + REG_OFFSET_BG3CNT)
#define REG_ADDR_BG0HOFS (REG_BASE + REG_OFFSET_BG0HOFS)
#define REG_ADDR_BG0VOFS (REG_BASE + REG_OFFSET_BG0VOFS)
#define REG_ADDR_BG1HOFS (REG_BASE + REG_OFFSET_BG1HOFS)
#define REG_ADDR_BG1VOFS (REG_BASE + REG_OFFSET_BG1VOFS)
#define REG_ADDR_BG2HOFS (REG_BASE + REG_OFFSET_BG2HOFS)
#define REG_ADDR_BG2VOFS (REG_BASE + REG_OFFSET_BG2VOFS)
#define REG_ADDR_BG3HOFS (REG_BASE + REG_OFFSET_BG3HOFS)
#define REG_ADDR_BG3VOFS (REG_BASE + REG_OFFSET_BG3VOFS)
#define REG_ADDR_BG2PA (REG_BASE + REG_OFFSET_BG2PA)
#define REG_ADDR_BG2PB (REG_BASE + REG_OFFSET_BG2PB)
#define REG_ADDR_BG2PC (REG_BASE + REG_OFFSET_BG2PC)
#define REG_ADDR_BG2PD (REG_BASE + REG_OFFSET_BG2PD)
#define REG_ADDR_BG2X (REG_BASE + REG_OFFSET_BG2X)
#define REG_ADDR_BG2X_L (REG_BASE + REG_OFFSET_BG2X_L)
#define REG_ADDR_BG2X_H (REG_BASE + REG_OFFSET_BG2X_H)
#define REG_ADDR_BG2Y (REG_BASE + REG_OFFSET_BG2Y)
#define REG_ADDR_BG2Y_L (REG_BASE + REG_OFFSET_BG2Y_L)
#define REG_ADDR_BG2Y_H (REG_BASE + REG_OFFSET_BG2Y_H)
#define REG_ADDR_BG3PA (REG_BASE + REG_OFFSET_BG3PA)
#define REG_ADDR_BG3PB (REG_BASE + REG_OFFSET_BG3PB)
#define REG_ADDR_BG3PC (REG_BASE + REG_OFFSET_BG3PC)
#define REG_ADDR_BG3PD (REG_BASE + REG_OFFSET_BG3PD)
#define REG_ADDR_BG3X (REG_BASE + REG_OFFSET_BG3X)
#define REG_ADDR_BG3X_L (REG_BASE + REG_OFFSET_BG3X_L)
#define REG_ADDR_BG3X_H (REG_BASE + REG_OFFSET_BG3X_H)
#define REG_ADDR_BG3Y (REG_BASE + REG_OFFSET_BG3Y)
#define REG_ADDR_BG3Y_L (REG_BASE + REG_OFFSET_BG3Y_L)
#define REG_ADDR_BG3Y_H (REG_BASE + REG_OFFSET_BG3Y_H)
#define REG_ADDR_WIN0H (REG_BASE + REG_OFFSET_WIN0H)
#define REG_ADDR_WIN1H (REG_BASE + REG_OFFSET_WIN1H)
#define REG_ADDR_WIN0V (REG_BASE + REG_OFFSET_WIN0V)
#define REG_ADDR_WIN1V (REG_BASE + REG_OFFSET_WIN1V)
#define REG_ADDR_WININ (REG_BASE + REG_OFFSET_WININ)
#define REG_ADDR_WINOUT (REG_BASE + REG_OFFSET_WINOUT)
#define REG_ADDR_MOSAIC (REG_BASE + REG_OFFSET_MOSAIC)
#define REG_ADDR_BLDCNT (REG_BASE + REG_OFFSET_BLDCNT)
#define REG_ADDR_BLDALPHA (REG_BASE + REG_OFFSET_BLDALPHA)
#define REG_ADDR_BLDY (REG_BASE + REG_OFFSET_BLDY)
#define REG_ADDR_SOUND1CNT_L (REG_BASE + REG_OFFSET_SOUND1CNT_L)
#define REG_ADDR_NR10 (REG_BASE + REG_OFFSET_NR10)
#define REG_ADDR_SOUND1CNT_H (REG_BASE + REG_OFFSET_SOUND1CNT_H)
#define REG_ADDR_NR11 (REG_BASE + REG_OFFSET_NR11)
#define REG_ADDR_NR12 (REG_BASE + REG_OFFSET_NR12)
#define REG_ADDR_SOUND1CNT_X (REG_BASE + REG_OFFSET_SOUND1CNT_X)
#define REG_ADDR_NR13 (REG_BASE + REG_OFFSET_NR13)
#define REG_ADDR_NR14 (REG_BASE + REG_OFFSET_NR14)
#define REG_ADDR_SOUND2CNT_L (REG_BASE + REG_OFFSET_SOUND2CNT_L)
#define REG_ADDR_NR21 (REG_BASE + REG_OFFSET_NR21)
#define REG_ADDR_NR22 (REG_BASE + REG_OFFSET_NR22)
#define REG_ADDR_SOUND2CNT_H (REG_BASE + REG_OFFSET_SOUND2CNT_H)
#define REG_ADDR_NR23 (REG_BASE + REG_OFFSET_NR23)
#define REG_ADDR_NR24 (REG_BASE + REG_OFFSET_NR24)
#define REG_ADDR_SOUND3CNT_L (REG_BASE + REG_OFFSET_SOUND3CNT_L)
#define REG_ADDR_NR30 (REG_BASE + REG_OFFSET_NR30)
#define REG_ADDR_SOUND3CNT_H (REG_BASE + REG_OFFSET_SOUND3CNT_H)
#define REG_ADDR_NR31 (REG_BASE + REG_OFFSET_NR31)
#define REG_ADDR_NR32 (REG_BASE + REG_OFFSET_NR32)
#define REG_ADDR_SOUND3CNT_X (REG_BASE + REG_OFFSET_SOUND3CNT_X)
#define REG_ADDR_NR33 (REG_BASE + REG_OFFSET_NR33)
#define REG_ADDR_NR34 (REG_BASE + REG_OFFSET_NR34)
#define REG_ADDR_SOUND4CNT_L (REG_BASE + REG_OFFSET_SOUND4CNT_L)
#define REG_ADDR_NR41 (REG_BASE + REG_OFFSET_NR41)
#define REG_ADDR_NR42 (REG_BASE + REG_OFFSET_NR42)
#define REG_ADDR_SOUND4CNT_H (REG_BASE + REG_OFFSET_SOUND4CNT_H)
#define REG_ADDR_NR43 (REG_BASE + REG_OFFSET_NR43)
#define REG_ADDR_NR44 (REG_BASE + REG_OFFSET_NR44)
#define REG_ADDR_SOUNDCNT_L (REG_BASE + REG_OFFSET_SOUNDCNT_L)
#define REG_ADDR_NR50 (REG_BASE + REG_OFFSET_NR50)
#define REG_ADDR_NR51 (REG_BASE + REG_OFFSET_NR51)
#define REG_ADDR_SOUNDCNT_H (REG_BASE + REG_OFFSET_SOUNDCNT_H)
#define REG_ADDR_SOUNDCNT_X (REG_BASE + REG_OFFSET_SOUNDCNT_X)
#define REG_ADDR_NR52 (REG_BASE + REG_OFFSET_NR52)
#define REG_ADDR_SOUNDBIAS (REG_BASE + REG_OFFSET_SOUNDBIAS)
#define REG_ADDR_SOUNDBIAS_L (REG_BASE + REG_OFFSET_SOUNDBIAS_L)
#define REG_ADDR_SOUNDBIAS_H (REG_BASE + REG_OFFSET_SOUNDBIAS_H)
#define REG_ADDR_WAVE_RAM0 (REG_BASE + REG_OFFSET_WAVE_RAM0)
#define REG_ADDR_WAVE_RAM1 (REG_BASE + REG_OFFSET_WAVE_RAM1)
#define REG_ADDR_WAVE_RAM2 (REG_BASE + REG_OFFSET_WAVE_RAM2)
#define REG_ADDR_WAVE_RAM3 (REG_BASE + REG_OFFSET_WAVE_RAM3)
#define REG_ADDR_FIFO_A (REG_BASE + REG_OFFSET_FIFO_A)
#define REG_ADDR_FIFO_B (REG_BASE + REG_OFFSET_FIFO_B)
#define REG_ADDR_DMA0 (REG_BASE + REG_OFFSET_DMA0)
#define REG_ADDR_DMA0SAD (REG_BASE + REG_OFFSET_DMA0SAD)
#define REG_ADDR_DMA0DAD (REG_BASE + REG_OFFSET_DMA0DAD)
#define REG_ADDR_DMA0CNT (REG_BASE + REG_OFFSET_DMA0CNT)
#define REG_ADDR_DMA0CNT_L (REG_BASE + REG_OFFSET_DMA0CNT_L)
#define REG_ADDR_DMA0CNT_H (REG_BASE + REG_OFFSET_DMA0CNT_H)
#define REG_ADDR_DMA1 (REG_BASE + REG_OFFSET_DMA1)
#define REG_ADDR_DMA1SAD (REG_BASE + REG_OFFSET_DMA1SAD)
#define REG_ADDR_DMA1DAD (REG_BASE + REG_OFFSET_DMA1DAD)
#define REG_ADDR_DMA1CNT (REG_BASE + REG_OFFSET_DMA1CNT)
#define REG_ADDR_DMA1CNT_L (REG_BASE + REG_OFFSET_DMA1CNT_L)
#define REG_ADDR_DMA1CNT_H (REG_BASE + REG_OFFSET_DMA1CNT_H)
#define REG_ADDR_DMA2 (REG_BASE + REG_OFFSET_DMA2)
#define REG_ADDR_DMA2SAD (REG_BASE + REG_OFFSET_DMA2SAD)
#define REG_ADDR_DMA2DAD (REG_BASE + REG_OFFSET_DMA2DAD)
#define REG_ADDR_DMA2CNT (REG_BASE + REG_OFFSET_DMA2CNT)
#define REG_ADDR_DMA2CNT_L (REG_BASE + REG_OFFSET_DMA2CNT_L)
#define REG_ADDR_DMA2CNT_H (REG_BASE + REG_OFFSET_DMA2CNT_H)
#define REG_ADDR_DMA3 (REG_BASE + REG_OFFSET_DMA3)
#define REG_ADDR_DMA3SAD (REG_BASE + REG_OFFSET_DMA3SAD)
#define REG_ADDR_DMA3DAD (REG_BASE + REG_OFFSET_DMA3DAD)
#define REG_ADDR_DMA3CNT (REG_BASE + REG_OFFSET_DMA3CNT)
#define REG_ADDR_DMA3CNT_L (REG_BASE + REG_OFFSET_DMA3CNT_L)
#define REG_ADDR_DMA3CNT_H (REG_BASE + REG_OFFSET_DMA3CNT_H)
#define REG_ADDR_TMCNT (REG_BASE + REG_OFFSET_TMCNT)
#define REG_ADDR_TM0CNT (REG_BASE + REG_OFFSET_TM0CNT)
#define REG_ADDR_TM0CNT_L (REG_BASE + REG_OFFSET_TM0CNT_L)
#define REG_ADDR_TM0CNT_H (REG_BASE + REG_OFFSET_TM0CNT_H)
#define REG_ADDR_TM1CNT (REG_BASE + REG_OFFSET_TM1CNT)
#define REG_ADDR_TM1CNT_L (REG_BASE + REG_OFFSET_TM1CNT_L)
#define REG_ADDR_TM1CNT_H (REG_BASE + REG_OFFSET_TM1CNT_H)
#define REG_ADDR_TM2CNT (REG_BASE + REG_OFFSET_TM2CNT)
#define REG_ADDR_TM2CNT_L (REG_BASE + REG_OFFSET_TM2CNT_L)
#define REG_ADDR_TM2CNT_H (REG_BASE + REG_OFFSET_TM2CNT_H)
#define REG_ADDR_TM3CNT (REG_BASE + REG_OFFSET_TM3CNT)
#define REG_ADDR_TM3CNT_L (REG_BASE + REG_OFFSET_TM3CNT_L)
#define REG_ADDR_TM3CNT_H (REG_BASE + REG_OFFSET_TM3CNT_H)
#define REG_ADDR_SIOCNT (REG_BASE + REG_OFFSET_SIOCNT)
#define REG_ADDR_SIODATA8 (REG_BASE + REG_OFFSET_SIODATA8)
#define REG_ADDR_SIODATA32 (REG_BASE + REG_OFFSET_SIODATA32)
#define REG_ADDR_SIOMLT_SEND (REG_BASE + REG_OFFSET_SIOMLT_SEND)
#define REG_ADDR_SIOMLT_RECV (REG_BASE + REG_OFFSET_SIOMLT_RECV)
#define REG_ADDR_SIOMULTI0 (REG_BASE + REG_OFFSET_SIOMULTI0)
#define REG_ADDR_SIOMULTI1 (REG_BASE + REG_OFFSET_SIOMULTI1)
#define REG_ADDR_SIOMULTI2 (REG_BASE + REG_OFFSET_SIOMULTI2)
#define REG_ADDR_SIOMULTI3 (REG_BASE + REG_OFFSET_SIOMULTI3)
#define REG_ADDR_KEYINPUT (REG_BASE + REG_OFFSET_KEYINPUT)
#define REG_ADDR_KEYCNT (REG_BASE + REG_OFFSET_KEYCNT)
#define REG_ADDR_RCNT (REG_BASE + REG_OFFSET_RCNT)
#define REG_ADDR_JOYCNT (REG_BASE + REG_OFFSET_JOYCNT)
#define REG_ADDR_JOYSTAT (REG_BASE + REG_OFFSET_JOYSTAT)
#define REG_ADDR_JOY_RECV (REG_BASE + REG_OFFSET_JOY_RECV)
#define REG_ADDR_JOY_RECV_L (REG_BASE + REG_OFFSET_JOY_RECV_L)
#define REG_ADDR_JOY_RECV_H (REG_BASE + REG_OFFSET_JOY_RECV_H)
#define REG_ADDR_JOY_TRANS (REG_BASE + REG_OFFSET_JOY_TRANS)
#define REG_ADDR_JOY_TRANS_L (REG_BASE + REG_OFFSET_JOY_TRANS_L)
#define REG_ADDR_JOY_TRANS_H (REG_BASE + REG_OFFSET_JOY_TRANS_H)
#define REG_ADDR_IME (REG_BASE + REG_OFFSET_IME)
#define REG_ADDR_IE (REG_BASE + REG_OFFSET_IE)
#define REG_ADDR_IF (REG_BASE + REG_OFFSET_IF)
#define REG_ADDR_WAITCNT (REG_BASE + REG_OFFSET_WAITCNT)
// I/O registers
#define REG_DISPCNT (*(vu16 *)REG_ADDR_DISPCNT)
#define REG_DISPSTAT (*(vu16 *)REG_ADDR_DISPSTAT)
#define REG_VCOUNT (*(vu16 *)REG_ADDR_VCOUNT)
#define REG_BG0CNT (*(vu16 *)REG_ADDR_BG0CNT)
#define REG_BG1CNT (*(vu16 *)REG_ADDR_BG1CNT)
#define REG_BG2CNT (*(vu16 *)REG_ADDR_BG2CNT)
#define REG_BG3CNT (*(vu16 *)REG_ADDR_BG3CNT)
#define REG_BG0HOFS (*(vu16 *)REG_ADDR_BG0HOFS)
#define REG_BG0VOFS (*(vu16 *)REG_ADDR_BG0VOFS)
#define REG_BG1HOFS (*(vu16 *)REG_ADDR_BG1HOFS)
#define REG_BG1VOFS (*(vu16 *)REG_ADDR_BG1VOFS)
#define REG_BG2HOFS (*(vu16 *)REG_ADDR_BG2HOFS)
#define REG_BG2VOFS (*(vu16 *)REG_ADDR_BG2VOFS)
#define REG_BG3HOFS (*(vu16 *)REG_ADDR_BG3HOFS)
#define REG_BG3VOFS (*(vu16 *)REG_ADDR_BG3VOFS)
#define REG_BG2PA (*(vu16 *)REG_ADDR_BG2PA)
#define REG_BG2PB (*(vu16 *)REG_ADDR_BG2PB)
#define REG_BG2PC (*(vu16 *)REG_ADDR_BG2PC)
#define REG_BG2PD (*(vu16 *)REG_ADDR_BG2PD)
#define REG_BG2X (*(vu32 *)REG_ADDR_BG2X)
#define REG_BG2X_L (*(vu16 *)REG_ADDR_BG2X_L)
#define REG_BG2X_H (*(vu16 *)REG_ADDR_BG2X_H)
#define REG_BG2Y (*(vu32 *)REG_ADDR_BG2Y)
#define REG_BG2Y_L (*(vu16 *)REG_ADDR_BG2Y_L)
#define REG_BG2Y_H (*(vu16 *)REG_ADDR_BG2Y_H)
#define REG_BG3PA (*(vu16 *)REG_ADDR_BG3PA)
#define REG_BG3PB (*(vu16 *)REG_ADDR_BG3PB)
#define REG_BG3PC (*(vu16 *)REG_ADDR_BG3PC)
#define REG_BG3PD (*(vu16 *)REG_ADDR_BG3PD)
#define REG_BG3X (*(vu32 *)REG_ADDR_BG3X)
#define REG_BG3X_L (*(vu16 *)REG_ADDR_BG3X_L)
#define REG_BG3X_H (*(vu16 *)REG_ADDR_BG3X_H)
#define REG_BG3Y (*(vu32 *)REG_ADDR_BG3Y)
#define REG_BG3Y_L (*(vu16 *)REG_ADDR_BG3Y_L)
#define REG_BG3Y_H (*(vu16 *)REG_ADDR_BG3Y_H)
#define REG_WIN0H (*(vu16 *)REG_ADDR_WIN0H)
#define REG_WIN1H (*(vu16 *)REG_ADDR_WIN1H)
#define REG_WIN0V (*(vu16 *)REG_ADDR_WIN0V)
#define REG_WIN1V (*(vu16 *)REG_ADDR_WIN1V)
#define REG_WININ (*(vu16 *)REG_ADDR_WININ)
#define REG_WINOUT (*(vu16 *)REG_ADDR_WINOUT)
#define REG_MOSAIC (*(vu16 *)REG_ADDR_MOSAIC)
#define REG_BLDCNT (*(vu16 *)REG_ADDR_BLDCNT)
#define REG_BLDALPHA (*(vu16 *)REG_ADDR_BLDALPHA)
#define REG_BLDY (*(vu16 *)REG_ADDR_BLDY)
#define REG_SOUND1CNT_L (*(vu16 *)REG_ADDR_SOUND1CNT_L)
#define REG_NR10 (*(vu8 *)REG_ADDR_NR10)
#define REG_SOUND1CNT_H (*(vu16 *)REG_ADDR_SOUND1CNT_H)
#define REG_NR11 (*(vu8 *)REG_ADDR_NR11)
#define REG_NR12 (*(vu8 *)REG_ADDR_NR12)
#define REG_SOUND1CNT_X (*(vu16 *)REG_ADDR_SOUND1CNT_X)
#define REG_NR13 (*(vu8 *)REG_ADDR_NR13)
#define REG_NR14 (*(vu8 *)REG_ADDR_NR14)
#define REG_SOUND2CNT_L (*(vu16 *)REG_ADDR_SOUND2CNT_L)
#define REG_NR21 (*(vu8 *)REG_ADDR_NR21)
#define REG_NR22 (*(vu8 *)REG_ADDR_NR22)
#define REG_SOUND2CNT_H (*(vu16 *)REG_ADDR_SOUND2CNT_H)
#define REG_NR23 (*(vu8 *)REG_ADDR_NR23)
#define REG_NR24 (*(vu8 *)REG_ADDR_NR24)
#define REG_SOUND3CNT_L (*(vu16 *)REG_ADDR_SOUND3CNT_L)
#define REG_NR30 (*(vu8 *)REG_ADDR_NR30)
#define REG_SOUND3CNT_H (*(vu16 *)REG_ADDR_SOUND3CNT_H)
#define REG_NR31 (*(vu8 *)REG_ADDR_NR31)
#define REG_NR32 (*(vu8 *)REG_ADDR_NR32)
#define REG_SOUND3CNT_X (*(vu16 *)REG_ADDR_SOUND3CNT_X)
#define REG_NR33 (*(vu8 *)REG_ADDR_NR33)
#define REG_NR34 (*(vu8 *)REG_ADDR_NR34)
#define REG_SOUND4CNT_L (*(vu16 *)REG_ADDR_SOUND4CNT_L)
#define REG_NR41 (*(vu8 *)REG_ADDR_NR41)
#define REG_NR42 (*(vu8 *)REG_ADDR_NR42)
#define REG_SOUND4CNT_H (*(vu16 *)REG_ADDR_SOUND4CNT_H)
#define REG_NR43 (*(vu8 *)REG_ADDR_NR43)
#define REG_NR44 (*(vu8 *)REG_ADDR_NR44)
#define REG_SOUNDCNT_L (*(vu16 *)REG_ADDR_SOUNDCNT_L)
#define REG_NR50 (*(vu8 *)REG_ADDR_NR50)
#define REG_NR51 (*(vu8 *)REG_ADDR_NR51)
#define REG_SOUNDCNT_H (*(vu16 *)REG_ADDR_SOUNDCNT_H)
#define REG_SOUNDCNT_X (*(vu16 *)REG_ADDR_SOUNDCNT_X)
#define REG_NR52 (*(vu8 *)REG_ADDR_NR52)
#define REG_SOUNDBIAS (*(vu16 *)REG_ADDR_SOUNDBIAS)
#define REG_SOUNDBIAS_L (*(vu8 *)REG_ADDR_SOUNDBIAS_L)
#define REG_SOUNDBIAS_H (*(vu8 *)REG_ADDR_SOUNDBIAS_H)
#define REG_WAVE_RAM0 (*(vu32 *)REG_ADDR_WAVE_RAM0)
#define REG_WAVE_RAM1 (*(vu32 *)REG_ADDR_WAVE_RAM1)
#define REG_WAVE_RAM2 (*(vu32 *)REG_ADDR_WAVE_RAM2)
#define REG_WAVE_RAM3 (*(vu32 *)REG_ADDR_WAVE_RAM3)
#define REG_FIFO_A (*(vu32 *)REG_ADDR_FIFO_A)
#define REG_FIFO_B (*(vu32 *)REG_ADDR_FIFO_B)
#define REG_DMA0SAD (*(vu32 *)REG_ADDR_DMA0SAD)
#define REG_DMA0DAD (*(vu32 *)REG_ADDR_DMA0DAD)
#define REG_DMA0CNT (*(vu32 *)REG_ADDR_DMA0CNT)
#define REG_DMA0CNT_L (*(vu16 *)REG_ADDR_DMA0CNT_L)
#define REG_DMA0CNT_H (*(vu16 *)REG_ADDR_DMA0CNT_H)
#define REG_DMA1SAD (*(vu32 *)REG_ADDR_DMA1SAD)
#define REG_DMA1DAD (*(vu32 *)REG_ADDR_DMA1DAD)
#define REG_DMA1CNT (*(vu32 *)REG_ADDR_DMA1CNT)
#define REG_DMA1CNT_L (*(vu16 *)REG_ADDR_DMA1CNT_L)
#define REG_DMA1CNT_H (*(vu16 *)REG_ADDR_DMA1CNT_H)
#define REG_DMA2SAD (*(vu32 *)REG_ADDR_DMA2SAD)
#define REG_DMA2DAD (*(vu32 *)REG_ADDR_DMA2DAD)
#define REG_DMA2CNT (*(vu32 *)REG_ADDR_DMA2CNT)
#define REG_DMA2CNT_L (*(vu16 *)REG_ADDR_DMA2CNT_L)
#define REG_DMA2CNT_H (*(vu16 *)REG_ADDR_DMA2CNT_H)
#define REG_DMA3SAD (*(vu32 *)REG_ADDR_DMA3SAD)
#define REG_DMA3DAD (*(vu32 *)REG_ADDR_DMA3DAD)
#define REG_DMA3CNT (*(vu32 *)REG_ADDR_DMA3CNT)
#define REG_DMA3CNT_L (*(vu16 *)REG_ADDR_DMA3CNT_L)
#define REG_DMA3CNT_H (*(vu16 *)REG_ADDR_DMA3CNT_H)
#define REG_TMCNT(n) (*(vu16 *)(REG_ADDR_TMCNT + ((n) * 4)))
#define REG_TM0CNT (*(vu32 *)REG_ADDR_TM0CNT)
#define REG_TM0CNT_L (*(vu16 *)REG_ADDR_TM0CNT_L)
#define REG_TM0CNT_H (*(vu16 *)REG_ADDR_TM0CNT_H)
#define REG_TM1CNT (*(vu32 *)REG_ADDR_TM1CNT)
#define REG_TM1CNT_L (*(vu16 *)REG_ADDR_TM1CNT_L)
#define REG_TM1CNT_H (*(vu16 *)REG_ADDR_TM1CNT_H)
#define REG_TM2CNT (*(vu32 *)REG_ADDR_TM2CNT)
#define REG_TM2CNT_L (*(vu16 *)REG_ADDR_TM2CNT_L)
#define REG_TM2CNT_H (*(vu16 *)REG_ADDR_TM2CNT_H)
#define REG_TM3CNT (*(vu32 *)REG_ADDR_TM3CNT)
#define REG_TM3CNT_L (*(vu16 *)REG_ADDR_TM3CNT_L)
#define REG_TM3CNT_H (*(vu16 *)REG_ADDR_TM3CNT_H)
#define REG_SIOCNT (*(vu16 *)REG_ADDR_SIOCNT)
#define REG_SIODATA8 (*(vu16 *)REG_ADDR_SIODATA8)
#define REG_SIODATA32 (*(vu32 *)REG_ADDR_SIODATA32)
#define REG_SIOMLT_SEND (*(vu16 *)REG_ADDR_SIOMLT_SEND)
#define REG_SIOMLT_RECV (*(vu64 *)REG_ADDR_SIOMLT_RECV)
#define REG_SIOMULTI0 (*(vu16 *)REG_ADDR_SIOMULTI0)
#define REG_SIOMULTI1 (*(vu16 *)REG_ADDR_SIOMULTI1)
#define REG_SIOMULTI2 (*(vu16 *)REG_ADDR_SIOMULTI2)
#define REG_SIOMULTI3 (*(vu16 *)REG_ADDR_SIOMULTI3)
#define REG_KEYINPUT (*(vu16 *)REG_ADDR_KEYINPUT)
#define REG_KEYCNT (*(vu16 *)REG_ADDR_KEYCNT)
#define REG_RCNT (*(vu16 *)REG_ADDR_RCNT)
#define REG_IME (*(vu16 *)REG_ADDR_IME)
#define REG_IE (*(vu16 *)REG_ADDR_IE)
#define REG_IF (*(vu16 *)REG_ADDR_IF)
#define REG_WAITCNT (*(vu16 *)REG_ADDR_WAITCNT)
// I/O register fields
// DISPCNT
#define DISPCNT_MODE_0 0x0000 // BG0: text, BG1: text, BG2: text, BG3: text
#define DISPCNT_MODE_1 0x0001 // BG0: text, BG1: text, BG2: affine, BG3: off
#define DISPCNT_MODE_2 0x0002 // BG0: off, BG1: off, BG2: affine, BG3: affine
#define DISPCNT_MODE_3 0x0003 // Bitmap mode, 240x160, BGR555 color
#define DISPCNT_MODE_4 0x0004 // Bitmap mode, 240x160, 256 color palette
#define DISPCNT_MODE_5 0x0005 // Bitmap mode, 160x128, BGR555 color
#define DISPCNT_OBJ_1D_MAP 0x0040
#define DISPCNT_FORCED_BLANK 0x0080
#define DISPCNT_BG0_ON 0x0100
#define DISPCNT_BG1_ON 0x0200
#define DISPCNT_BG2_ON 0x0400
#define DISPCNT_BG3_ON 0x0800
#define DISPCNT_BG_ALL_ON 0x0F00
#define DISPCNT_OBJ_ON 0x1000
#define DISPCNT_WIN0_ON 0x2000
#define DISPCNT_WIN1_ON 0x4000
#define DISPCNT_OBJWIN_ON 0x8000
// DISPSTAT
#define DISPSTAT_VBLANK 0x0001 // in V-Blank
#define DISPSTAT_HBLANK 0x0002 // in H-Blank
#define DISPSTAT_VCOUNT 0x0004 // V-Count match
#define DISPSTAT_VBLANK_INTR 0x0008 // V-Blank interrupt enabled
#define DISPSTAT_HBLANK_INTR 0x0010 // H-Blank interrupt enabled
#define DISPSTAT_VCOUNT_INTR 0x0020 // V-Count interrupt enabled
// BGCNT
#define BGCNT_PRIORITY(n) (n) // Values 0 - 3. Lower priority BGs will be drawn on top of higher priority BGs.
#define BGCNT_CHARBASE(n) ((n) << 2) // Values 0 - 3. Base block for tile pixel data.
#define BGCNT_MOSAIC 0x0040
#define BGCNT_16COLOR 0x0000 // 4 bits per pixel
#define BGCNT_256COLOR 0x0080 // 8 bits per pixel
#define BGCNT_SCREENBASE(n) ((n) << 8) // Values 0 - 31. Base block for tile map.
#define BGCNT_WRAP 0x2000 // Only affects affine BGs. Text BGs wrap by default.
#define BGCNT_TXT256x256 0x0000 // Internal screen size size of text mode BG in pixels.
#define BGCNT_TXT512x256 0x4000
#define BGCNT_TXT256x512 0x8000
#define BGCNT_TXT512x512 0xC000
#define BGCNT_AFF128x128 0x0000 // Internal screen size size of affine mode BG in pixels.
#define BGCNT_AFF256x256 0x4000
#define BGCNT_AFF512x512 0x8000
#define BGCNT_AFF1024x1024 0xC000
// BLDCNT
// Bits 0-5 select layers for the 1st target
#define BLDCNT_TGT1_BG0 (1 << 0)
#define BLDCNT_TGT1_BG1 (1 << 1)
#define BLDCNT_TGT1_BG2 (1 << 2)
#define BLDCNT_TGT1_BG3 (1 << 3)
#define BLDCNT_TGT1_OBJ (1 << 4)
#define BLDCNT_TGT1_BD (1 << 5)
// Bits 6-7 select the special effect
#define BLDCNT_EFFECT_NONE (0 << 6) // no special effect
#define BLDCNT_EFFECT_BLEND (1 << 6) // 1st+2nd targets mixed (controlled by BLDALPHA)
#define BLDCNT_EFFECT_LIGHTEN (2 << 6) // 1st target becomes whiter (controlled by BLDY)
#define BLDCNT_EFFECT_DARKEN (3 << 6) // 1st target becomes blacker (controlled by BLDY)
// Bits 8-13 select layers for the 2nd target
#define BLDCNT_TGT2_BG0 (1 << 8)
#define BLDCNT_TGT2_BG1 (1 << 9)
#define BLDCNT_TGT2_BG2 (1 << 10)
#define BLDCNT_TGT2_BG3 (1 << 11)
#define BLDCNT_TGT2_OBJ (1 << 12)
#define BLDCNT_TGT2_BD (1 << 13)
// BLDALPHA
#define BLDALPHA_BLEND(target1, target2) (((target2) << 8) | (target1))
// SOUNDCNT_H
#define SOUND_CGB_MIX_QUARTER 0x0000
#define SOUND_CGB_MIX_HALF 0x0001
#define SOUND_CGB_MIX_FULL 0x0002
#define SOUND_A_MIX_HALF 0x0000
#define SOUND_A_MIX_FULL 0x0004
#define SOUND_B_MIX_HALF 0x0000
#define SOUND_B_MIX_FULL 0x0008
#define SOUND_ALL_MIX_FULL 0x000E
#define SOUND_A_RIGHT_OUTPUT 0x0100
#define SOUND_A_LEFT_OUTPUT 0x0200
#define SOUND_A_TIMER_0 0x0000
#define SOUND_A_TIMER_1 0x0400
#define SOUND_A_FIFO_RESET 0x0800
#define SOUND_B_RIGHT_OUTPUT 0x1000
#define SOUND_B_LEFT_OUTPUT 0x2000
#define SOUND_B_TIMER_0 0x0000
#define SOUND_B_TIMER_1 0x4000
#define SOUND_B_FIFO_RESET 0x8000
// SOUNDCNT_X
#define SOUND_1_ON 0x0001
#define SOUND_2_ON 0x0002
#define SOUND_3_ON 0x0004
#define SOUND_4_ON 0x0008
#define SOUND_MASTER_ENABLE 0x0080
// DMA
#define DMA_DEST_INC 0x0000
#define DMA_DEST_DEC 0x0020
#define DMA_DEST_FIXED 0x0040
#define DMA_DEST_RELOAD 0x0060
#define DMA_SRC_INC 0x0000
#define DMA_SRC_DEC 0x0080
#define DMA_SRC_FIXED 0x0100
#define DMA_REPEAT 0x0200
#define DMA_16BIT 0x0000
#define DMA_32BIT 0x0400
#define DMA_DREQ_ON 0x0800
#define DMA_START_NOW 0x0000
#define DMA_START_VBLANK 0x1000
#define DMA_START_HBLANK 0x2000
#define DMA_START_SPECIAL 0x3000
#define DMA_START_MASK 0x3000
#define DMA_INTR_ENABLE 0x4000
#define DMA_ENABLE 0x8000
// timer
#define TIMER_1CLK 0x00
#define TIMER_64CLK 0x01
#define TIMER_256CLK 0x02
#define TIMER_1024CLK 0x03
#define TIMER_INTR_ENABLE 0x40
#define TIMER_ENABLE 0x80
// serial
#define SIO_ID 0x0030 // Communication ID
#define SIO_8BIT_MODE 0x0000 // Normal 8-bit communication mode
#define SIO_32BIT_MODE 0x1000 // Normal 32-bit communication mode
#define SIO_MULTI_MODE 0x2000 // Multi-player communication mode
#define SIO_UART_MODE 0x3000 // UART communication mode
#define SIO_9600_BPS 0x0000 // baud rate 9600 bps
#define SIO_38400_BPS 0x0001 // 38400 bps
#define SIO_57600_BPS 0x0002 // 57600 bps
#define SIO_115200_BPS 0x0003 // 115200 bps
#define SIO_MULTI_SI 0x0004 // Multi-player communication SI terminal
#define SIO_MULTI_SD 0x0008 // SD terminal
#define SIO_MULTI_BUSY 0x0080
#define SIO_ERROR 0x0040 // Detect error
#define SIO_START 0x0080 // Start transfer
#define SIO_ENABLE 0x0080 // Enable SIO
#define SIO_INTR_ENABLE 0x4000
#define SIO_MULTI_SI_SHIFT 2
#define SIO_MULTI_SI_MASK 0x1
#define SIO_MULTI_DI_SHIFT 3
#define SIO_MULTI_DI_MASK 0x1
// keys
#define A_BUTTON 0x0001
#define B_BUTTON 0x0002
#define SELECT_BUTTON 0x0004
#define START_BUTTON 0x0008
#define DPAD_RIGHT 0x0010
#define DPAD_LEFT 0x0020
#define DPAD_UP 0x0040
#define DPAD_DOWN 0x0080
#define R_BUTTON 0x0100
#define L_BUTTON 0x0200
#define KEYS_MASK 0x03FF
#define KEY_INTR_ENABLE 0x0400
#define KEY_OR_INTR 0x0000
#define KEY_AND_INTR 0x8000
#define DPAD_ANY 0x00F0
#define JOY_EXCL_DPAD 0x030F
// interrupt flags
#define INTR_FLAG_VBLANK (1 << 0)
#define INTR_FLAG_HBLANK (1 << 1)
#define INTR_FLAG_VCOUNT (1 << 2)
#define INTR_FLAG_TIMER0 (1 << 3)
#define INTR_FLAG_TIMER1 (1 << 4)
#define INTR_FLAG_TIMER2 (1 << 5)
#define INTR_FLAG_TIMER3 (1 << 6)
#define INTR_FLAG_SERIAL (1 << 7)
#define INTR_FLAG_DMA0 (1 << 8)
#define INTR_FLAG_DMA1 (1 << 9)
#define INTR_FLAG_DMA2 (1 << 10)
#define INTR_FLAG_DMA3 (1 << 11)
#define INTR_FLAG_KEYPAD (1 << 12)
#define INTR_FLAG_GAMEPAK (1 << 13)
// WAITCNT
#define WAITCNT_SRAM_4 (0 << 0)
#define WAITCNT_SRAM_3 (1 << 0)
#define WAITCNT_SRAM_2 (2 << 0)
#define WAITCNT_SRAM_8 (3 << 0)
#define WAITCNT_SRAM_MASK (3 << 0)
#define WAITCNT_WS0_N_4 (0 << 2)
#define WAITCNT_WS0_N_3 (1 << 2)
#define WAITCNT_WS0_N_2 (2 << 2)
#define WAITCNT_WS0_N_8 (3 << 2)
#define WAITCNT_WS0_N_MASK (3 << 2)
#define WAITCNT_WS0_S_2 (0 << 4)
#define WAITCNT_WS0_S_1 (1 << 4)
#define WAITCNT_WS1_N_4 (0 << 5)
#define WAITCNT_WS1_N_3 (1 << 5)
#define WAITCNT_WS1_N_2 (2 << 5)
#define WAITCNT_WS1_N_8 (3 << 5)
#define WAITCNT_WS1_N_MASK (3 << 5)
#define WAITCNT_WS1_S_4 (0 << 7)
#define WAITCNT_WS1_S_1 (1 << 7)
#define WAITCNT_WS2_N_4 (0 << 8)
#define WAITCNT_WS2_N_3 (1 << 8)
#define WAITCNT_WS2_N_2 (2 << 8)
#define WAITCNT_WS2_N_8 (3 << 8)
#define WAITCNT_WS2_N_MASK (3 << 8)
#define WAITCNT_WS2_S_8 (0 << 10)
#define WAITCNT_WS2_S_1 (1 << 10)
#define WAITCNT_PHI_OUT_NONE (0 << 11)
#define WAITCNT_PHI_OUT_4MHZ (1 << 11)
#define WAITCNT_PHI_OUT_8MHZ (2 << 11)
#define WAITCNT_PHI_OUT_16MHZ (3 << 11)
#define WAITCNT_PHI_OUT_MASK (3 << 11)
#define WAITCNT_PREFETCH_ENABLE (1 << 14)
#define WAITCNT_AGB (0 << 15)
#define WAITCNT_CGB (1 << 15)
#endif // GUARD_GBA_IO_REG_H

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#ifndef GUARD_M4A_INTERNAL_H
#define GUARD_M4A_INTERNAL_H
#include "gba/gba.h"
// ASCII encoding of 'Smsh' in reverse
// This is presumably short for SMASH, the developer of MKS4AGB.
#define ID_NUMBER 0x68736D53
#define C_V 0x40 // center value for PAN, BEND, and TUNE
#define SOUND_MODE_REVERB_VAL 0x0000007F
#define SOUND_MODE_REVERB_SET 0x00000080
#define SOUND_MODE_MAXCHN 0x00000F00
#define SOUND_MODE_MAXCHN_SHIFT 8
#define SOUND_MODE_MASVOL 0x0000F000
#define SOUND_MODE_MASVOL_SHIFT 12
#define SOUND_MODE_FREQ_05734 0x00010000
#define SOUND_MODE_FREQ_07884 0x00020000
#define SOUND_MODE_FREQ_10512 0x00030000
#define SOUND_MODE_FREQ_13379 0x00040000
#define SOUND_MODE_FREQ_15768 0x00050000
#define SOUND_MODE_FREQ_18157 0x00060000
#define SOUND_MODE_FREQ_21024 0x00070000
#define SOUND_MODE_FREQ_26758 0x00080000
#define SOUND_MODE_FREQ_31536 0x00090000
#define SOUND_MODE_FREQ_36314 0x000A0000
#define SOUND_MODE_FREQ_40137 0x000B0000
#define SOUND_MODE_FREQ_42048 0x000C0000
#define SOUND_MODE_FREQ 0x000F0000
#define SOUND_MODE_FREQ_SHIFT 16
#define SOUND_MODE_DA_BIT_9 0x00800000
#define SOUND_MODE_DA_BIT_8 0x00900000
#define SOUND_MODE_DA_BIT_7 0x00A00000
#define SOUND_MODE_DA_BIT_6 0x00B00000
#define SOUND_MODE_DA_BIT 0x00B00000
#define SOUND_MODE_DA_BIT_SHIFT 20
struct WaveData
{
u16 type;
u16 status;
u32 freq;
u32 loopStart;
u32 size; // number of samples
s8 data[1]; // samples
};
#define TONEDATA_TYPE_CGB 0x07
#define TONEDATA_TYPE_FIX 0x08
#define TONEDATA_TYPE_SPL 0x40 // key split
#define TONEDATA_TYPE_RHY 0x80 // rhythm
#define TONEDATA_P_S_PAN 0xc0
#define TONEDATA_P_S_PAM TONEDATA_P_S_PAN
struct ToneData
{
u8 type;
u8 key;
u8 length; // sound length (compatible sound)
u8 pan_sweep; // pan or sweep (compatible sound ch. 1)
struct WaveData *wav;
u8 attack;
u8 decay;
u8 sustain;
u8 release;
};
struct CgbChannel
{
u8 sf;
u8 ty;
u8 rightVolume;
u8 leftVolume;
u8 at;
u8 de;
u8 su;
u8 re;
u8 ky;
u8 ev;
u8 eg;
u8 ec;
u8 echoVolume;
u8 echoLength;
u8 d1;
u8 d2;
u8 gt;
u8 mk;
u8 ve;
u8 pr;
u8 rp;
u8 d3[3];
u8 d5;
u8 sg;
u8 n4;
u8 pan;
u8 panMask;
u8 mo;
u8 le;
u8 sw;
u32 fr;
u32 wp;
u32 cp;
u32 tp;
u32 pp;
u32 np;
u8 d4[8];
};
struct MusicPlayerTrack;
struct SoundChannel
{
u8 status;
u8 type;
u8 rightVolume;
u8 leftVolume;
u8 attack;
u8 decay;
u8 sustain;
u8 release;
u8 ky;
u8 ev;
u8 er;
u8 el;
u8 echoVolume;
u8 echoLength;
u8 d1;
u8 d2;
u8 gt;
u8 mk;
u8 ve;
u8 pr;
u8 rp;
u8 d3[3];
u32 ct;
u32 fw;
u32 freq;
struct WaveData *wav;
u32 cp;
struct MusicPlayerTrack *track;
u32 pp;
u32 np;
u32 d4;
u16 xpi;
u16 xpc;
};
#define MAX_DIRECTSOUND_CHANNELS 12
#define PCM_DMA_BUF_SIZE 1584 // size of Direct Sound buffer
struct SoundInfo
{
// This field is normally equal to ID_NUMBER but it is set to other
// values during sensitive operations for locking purposes.
// This field should be volatile but isn't. This could potentially cause
// race conditions.
u32 ident;
vu8 pcmDmaCounter;
// Direct Sound
u8 reverb;
u8 maxChans;
u8 masterVolume;
u8 freq;
u8 mode;
u8 c15;
u8 pcmDmaPeriod; // number of V-blanks per PCM DMA
u8 maxLines;
u8 gap[3];
s32 pcmSamplesPerVBlank;
s32 pcmFreq;
s32 divFreq;
struct CgbChannel *cgbChans;
u32 func;
u32 intp;
void (*CgbSound)(void);
void (*CgbOscOff)(u8);
u32 (*MidiKeyToCgbFreq)(u8, u8, u8);
u32 MPlayJumpTable;
u32 plynote;
u32 ExtVolPit;
u8 gap2[16];
struct SoundChannel chans[MAX_DIRECTSOUND_CHANNELS];
s8 pcmBuffer[PCM_DMA_BUF_SIZE * 2];
};
struct SongHeader
{
u8 trackCount;
u8 blockCount;
u8 priority;
u8 reverb;
struct ToneData *tone;
u8 *part[1];
};
struct PokemonCrySong
{
u8 trackCount;
u8 blockCount;
u8 priority;
u8 reverb;
struct ToneData *tone;
u8 *part[2];
u8 gap;
u8 part0; // 0x11
u8 tuneValue; // 0x12
u8 gotoCmd; // 0x13
u32 gotoTarget; // 0x14
u8 part1; // 0x18
u8 tuneValue2; // 0x19
u8 cont[2]; // 0x1A
u8 volCmd; // 0x1C
u8 volumeValue; // 0x1D
u8 unkCmd0D[2]; // 0x1E
u32 unkCmd0DParam; // 0x20
u8 xreleCmd[2]; // 0x24
u8 releaseValue; // 0x26
u8 panCmd;
u8 panValue; // 0x28
u8 tieCmd; // 0x29
u8 tieKeyValue; // 0x2A
u8 tieVelocityValue; // 0x2B
u8 unkCmd0C[2]; // 0x2C
u16 unkCmd0CParam; // 0x2E
u8 end[2]; // 0x30
};
#define MPT_FLG_VOLSET 0x01
#define MPT_FLG_VOLCHG 0x03
#define MPT_FLG_PITSET 0x04
#define MPT_FLG_PITCHG 0x0C
#define MPT_FLG_START 0x40
#define MPT_FLG_EXIST 0x80
struct MusicPlayerTrack
{
u8 flags;
u8 wait;
u8 patternLevel;
u8 repN;
u8 gateTime;
u8 key;
u8 velocity;
u8 runningStatus;
u8 keyM;
u8 pitM;
s8 keyShift;
s8 keyShiftX;
s8 tune;
u8 pitX;
s8 bend;
u8 bendRange;
u8 volMR;
u8 volML;
u8 vol;
u8 volX;
s8 pan;
s8 panX;
s8 modM;
u8 mod;
u8 modT;
u8 lfoSpeed;
u8 lfoSpeedC;
u8 lfoDelay;
u8 lfoDelayC;
u8 priority;
u8 echoVolume;
u8 echoLength;
struct SoundChannel *chan;
struct ToneData tone;
u8 gap[10];
u16 unk_3A;
u32 unk_3C;
u8 *cmdPtr;
u8 *patternStack[3];
};
#define MUSICPLAYER_STATUS_TRACK 0x0000ffff
#define MUSICPLAYER_STATUS_PAUSE 0x80000000
#define MAX_MUSICPLAYER_TRACKS 16
#define TEMPORARY_FADE 0x0001
#define FADE_IN 0x0002
#define FADE_VOL_MAX 64
#define FADE_VOL_SHIFT 2
struct MusicPlayerInfo
{
struct SongHeader *songHeader;
u32 status;
u8 trackCount;
u8 priority;
u8 cmd;
u8 unk_B;
u32 clock;
u8 gap[8];
u8 *memAccArea;
u16 tempoD;
u16 tempoU;
u16 tempoI;
u16 tempoC;
u16 fadeOI;
u16 fadeOC;
u16 fadeOV;
struct MusicPlayerTrack *tracks;
struct ToneData *tone;
u32 ident;
u32 func;
u32 intp;
};
struct MusicPlayer
{
struct MusicPlayerInfo *info;
struct MusicPlayerTrack *track;
u8 unk_8;
u16 unk_A;
};
struct Song
{
struct SongHeader *header;
u16 ms;
u16 me;
};
extern const struct MusicPlayer gMPlayTable[];
extern const struct Song gSongTable[];
extern u8 gMPlayMemAccArea[];
//u8 gPokemonCrySong[52];
//u8 gPokemonCrySongs[52 * MAX_POKEMON_CRIES];
#define MAX_POKEMON_CRIES 2
extern struct PokemonCrySong gPokemonCrySong;
extern struct PokemonCrySong gPokemonCrySongs[];
extern struct MusicPlayerInfo gPokemonCryMusicPlayers[];
extern struct MusicPlayerTrack gPokemonCryTracks[];
extern char SoundMainRAM[];
extern void *gMPlayJumpTable[];
typedef void (*XcmdFunc)(struct MusicPlayerInfo *, struct MusicPlayerTrack *);
extern const XcmdFunc gXcmdTable[];
extern struct CgbChannel gCgbChans[];
extern const u8 gScaleTable[];
extern const u32 gFreqTable[];
extern const u16 gPcmSamplesPerVBlankTable[];
extern const u8 gCgbScaleTable[];
extern const s16 gCgbFreqTable[];
extern const u8 gNoiseTable[];
extern const struct PokemonCrySong gPokemonCrySongTemplate;
extern const struct ToneData voicegroup_pokemon_cry;
extern char gNumMusicPlayers[];
extern char gMaxLines[];
#define NUM_MUSIC_PLAYERS ((u16)gNumMusicPlayers)
#define MAX_LINES ((u32)gMaxLines)
u32 umul3232H32(u32 multiplier, u32 multiplicand);
void SoundMain(void);
void SoundMainBTM(void);
void TrackStop(struct MusicPlayerInfo *mplayInfo, struct MusicPlayerTrack *track);
void MPlayMain(void);
void RealClearChain(void *x);
void MPlayContinue(struct MusicPlayerInfo *mplayInfo);
void MPlayStart(struct MusicPlayerInfo *mplayInfo, struct SongHeader *songHeader);
void m4aMPlayStop(struct MusicPlayerInfo *mplayInfo);
void FadeOutBody(struct MusicPlayerInfo *mplayInfo);
void TrkVolPitSet(struct MusicPlayerInfo *mplayInfo, struct MusicPlayerTrack *track);
void MPlayFadeOut(struct MusicPlayerInfo *mplayInfo, u16 speed);
void ClearChain(void *x);
void Clear64byte(void *addr);
void SoundInit(struct SoundInfo *soundInfo);
void MPlayExtender(struct CgbChannel *cgbChans);
void m4aSoundMode(u32 mode);
void MPlayOpen(struct MusicPlayerInfo *mplayInfo, struct MusicPlayerTrack *track, u8 a3);
void CgbSound(void);
void CgbOscOff(u8);
u32 MidiKeyToCgbFreq(u8, u8, u8);
void DummyFunc(void);
void MPlayJumpTableCopy(void **mplayJumpTable);
void SampleFreqSet(u32 freq);
void m4aSoundVSyncOn(void);
void m4aSoundVSyncOff(void);
void ClearModM(struct MusicPlayerTrack *track);
void m4aMPlayModDepthSet(struct MusicPlayerInfo *mplayInfo, u16 trackBits, u8 modDepth);
void m4aMPlayLFOSpeedSet(struct MusicPlayerInfo *mplayInfo, u16 trackBits, u8 lfoSpeed);
struct MusicPlayerInfo *SetPokemonCryTone(struct ToneData *tone);
void SetPokemonCryVolume(u8 val);
void SetPokemonCryPanpot(s8 val);
void SetPokemonCryPitch(s16 val);
void SetPokemonCryLength(u16 val);
void SetPokemonCryRelease(u8 val);
void SetPokemonCryProgress(u32 val);
int IsPokemonCryPlaying(struct MusicPlayerInfo *mplayInfo);
void SetPokemonCryChorus(s8 val);
void SetPokemonCryStereo(u32 val);
void SetPokemonCryPriority(u8 val);
// sound command handler functions
void ply_fine(struct MusicPlayerInfo *, struct MusicPlayerTrack *);
void ply_goto(struct MusicPlayerInfo *, struct MusicPlayerTrack *);
void ply_patt(struct MusicPlayerInfo *, struct MusicPlayerTrack *);
void ply_pend(struct MusicPlayerInfo *, struct MusicPlayerTrack *);
void ply_rept(struct MusicPlayerInfo *, struct MusicPlayerTrack *);
void ply_memacc(struct MusicPlayerInfo *, struct MusicPlayerTrack *);
void ply_prio(struct MusicPlayerInfo *, struct MusicPlayerTrack *);
void ply_tempo(struct MusicPlayerInfo *, struct MusicPlayerTrack *);
void ply_keysh(struct MusicPlayerInfo *, struct MusicPlayerTrack *);
void ply_voice(struct MusicPlayerInfo *, struct MusicPlayerTrack *);
void ply_vol(struct MusicPlayerInfo *, struct MusicPlayerTrack *);
void ply_pan(struct MusicPlayerInfo *, struct MusicPlayerTrack *);
void ply_bend(struct MusicPlayerInfo *, struct MusicPlayerTrack *);
void ply_bendr(struct MusicPlayerInfo *, struct MusicPlayerTrack *);
void ply_lfos(struct MusicPlayerInfo *, struct MusicPlayerTrack *);
void ply_lfodl(struct MusicPlayerInfo *, struct MusicPlayerTrack *);
void ply_mod(struct MusicPlayerInfo *, struct MusicPlayerTrack *);
void ply_modt(struct MusicPlayerInfo *, struct MusicPlayerTrack *);
void ply_tune(struct MusicPlayerInfo *, struct MusicPlayerTrack *);
void ply_port(struct MusicPlayerInfo *, struct MusicPlayerTrack *);
void ply_xcmd(struct MusicPlayerInfo *, struct MusicPlayerTrack *);
void ply_endtie(struct MusicPlayerInfo *, struct MusicPlayerTrack *);
void ply_note(struct MusicPlayerInfo *, struct MusicPlayerTrack *);
// extended sound command handler functions
void ply_xxx(struct MusicPlayerInfo *, struct MusicPlayerTrack *);
void ply_xwave(struct MusicPlayerInfo *, struct MusicPlayerTrack *);
void ply_xtype(struct MusicPlayerInfo *, struct MusicPlayerTrack *);
void ply_xatta(struct MusicPlayerInfo *, struct MusicPlayerTrack *);
void ply_xdeca(struct MusicPlayerInfo *, struct MusicPlayerTrack *);
void ply_xsust(struct MusicPlayerInfo *, struct MusicPlayerTrack *);
void ply_xrele(struct MusicPlayerInfo *, struct MusicPlayerTrack *);
void ply_xiecv(struct MusicPlayerInfo *, struct MusicPlayerTrack *);
void ply_xiecl(struct MusicPlayerInfo *, struct MusicPlayerTrack *);
void ply_xleng(struct MusicPlayerInfo *, struct MusicPlayerTrack *);
void ply_xswee(struct MusicPlayerInfo *, struct MusicPlayerTrack *);
void ply_xcmd_0C(struct MusicPlayerInfo *, struct MusicPlayerTrack *);
void ply_xcmd_0D(struct MusicPlayerInfo *, struct MusicPlayerTrack *);
#endif // GUARD_M4A_INTERNAL_H

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#ifndef GUARD_GBA_MACRO_H
#define GUARD_GBA_MACRO_H
#define CPU_FILL(value, dest, size, bit) \
{ \
vu##bit tmp = (vu##bit)(value); \
CpuSet((void *)&tmp, \
dest, \
CPU_SET_##bit##BIT | CPU_SET_SRC_FIXED | ((size)/(bit/8) & 0x1FFFFF)); \
}
#define CpuFill16(value, dest, size) CPU_FILL(value, dest, size, 16)
#define CpuFill32(value, dest, size) CPU_FILL(value, dest, size, 32)
#define CPU_COPY(src, dest, size, bit) CpuSet(src, dest, CPU_SET_##bit##BIT | ((size)/(bit/8) & 0x1FFFFF))
#define CpuCopy16(src, dest, size) CPU_COPY(src, dest, size, 16)
#define CpuCopy32(src, dest, size) CPU_COPY(src, dest, size, 32)
#define CpuFastFill(value, dest, size) \
{ \
vu32 tmp = (vu32)(value); \
CpuFastSet((void *)&tmp, \
dest, \
CPU_FAST_SET_SRC_FIXED | ((size)/(32/8) & 0x1FFFFF)); \
}
#define CpuFastFill16(value, dest, size) CpuFastFill(((value) << 16) | (value), (dest), (size))
#define CpuFastCopy(src, dest, size) CpuFastSet(src, dest, ((size)/(32/8) & 0x1FFFFF))
#define DmaSet(dmaNum, src, dest, control) \
{ \
vu32 *dmaRegs = (vu32 *)REG_ADDR_DMA##dmaNum; \
dmaRegs[0] = (vu32)(src); \
dmaRegs[1] = (vu32)(dest); \
dmaRegs[2] = (vu32)(control); \
dmaRegs[2]; \
}
#define DMA_FILL(dmaNum, value, dest, size, bit) \
{ \
vu##bit tmp = (vu##bit)(value); \
DmaSet(dmaNum, \
&tmp, \
dest, \
(DMA_ENABLE | DMA_START_NOW | DMA_##bit##BIT | DMA_SRC_FIXED | DMA_DEST_INC) << 16 \
| ((size)/(bit/8))); \
}
#define DmaFill16(dmaNum, value, dest, size) DMA_FILL(dmaNum, value, dest, size, 16)
#define DmaFill32(dmaNum, value, dest, size) DMA_FILL(dmaNum, value, dest, size, 32)
// Note that the DMA clear macros cause the DMA control value to be calculated
// at runtime rather than compile time. The size is divided by the DMA transfer
// unit size (2 or 4 bytes) and then combined with the DMA control flags using a
// bitwise OR operation.
#define DMA_CLEAR(dmaNum, dest, size, bit) \
{ \
vu##bit *_dest = (vu##bit *)(dest); \
u32 _size = size; \
DmaFill##bit(dmaNum, 0, _dest, _size); \
}
#define DmaClear16(dmaNum, dest, size) DMA_CLEAR(dmaNum, dest, size, 16)
#define DmaClear32(dmaNum, dest, size) DMA_CLEAR(dmaNum, dest, size, 32)
#define DMA_COPY(dmaNum, src, dest, size, bit) \
DmaSet(dmaNum, \
src, \
dest, \
(DMA_ENABLE | DMA_START_NOW | DMA_##bit##BIT | DMA_SRC_INC | DMA_DEST_INC) << 16 \
| ((size)/(bit/8)))
#define DmaCopy16(dmaNum, src, dest, size) DMA_COPY(dmaNum, src, dest, size, 16)
#define DmaCopy32(dmaNum, src, dest, size) DMA_COPY(dmaNum, src, dest, size, 32)
#define DmaStop(dmaNum) \
{ \
vu16 *dmaRegs = (vu16 *)REG_ADDR_DMA##dmaNum; \
dmaRegs[5] &= ~(DMA_START_MASK | DMA_DREQ_ON | DMA_REPEAT); \
dmaRegs[5] &= ~DMA_ENABLE; \
dmaRegs[5]; \
}
#define DmaCopyLarge(dmaNum, src, dest, size, block, bit) \
{ \
const void *_src = src; \
void *_dest = dest; \
u32 _size = size; \
while (1) \
{ \
DmaCopy##bit(dmaNum, _src, _dest, (block)); \
_src += (block); \
_dest += (block); \
_size -= (block); \
if (_size <= (block)) \
{ \
DmaCopy##bit(dmaNum, _src, _dest, _size); \
break; \
} \
} \
}
#define DmaClearLarge(dmaNum, dest, size, block, bit) \
{ \
u32 _size = size; \
while (1) \
{ \
DmaFill##bit(dmaNum, 0, dest, (block)); \
dest += (block); \
_size -= (block); \
if (_size <= (block)) \
{ \
DmaFill##bit(dmaNum, 0, dest, _size); \
break; \
} \
} \
}
#define DmaCopyLarge16(dmaNum, src, dest, size, block) DmaCopyLarge(dmaNum, src, dest, size, block, 16)
#define DmaCopyLarge32(dmaNum, src, dest, size, block) DmaCopyLarge(dmaNum, src, dest, size, block, 32)
#define DmaCopyDefvars(dmaNum, src, dest, size, bit) \
{ \
const void *_src = src; \
void *_dest = dest; \
u32 _size = size; \
DmaCopy##bit(dmaNum, _src, _dest, _size); \
}
#define DmaCopy16Defvars(dmaNum, src, dest, size) DmaCopyDefvars(dmaNum, src, dest, size, 16)
#define DmaCopy32Defvars(dmaNum, src, dest, size) DmaCopyDefvars(dmaNum, src, dest, size, 32)
#endif // GUARD_GBA_MACRO_H

55
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#ifndef GUARD_GBA_MULTIBOOT_H
#define GUARD_GBA_MULTIBOOT_H
#define MULTIBOOT_NCHILD 3 // Maximum number of slaves
#define MULTIBOOT_HEADER_SIZE 0xc0 // Header size
#define MULTIBOOT_SEND_SIZE_MIN 0x100 // Minimum transmission size
#define MULTIBOOT_SEND_SIZE_MAX 0x40000 // Maximum transmission size
struct MultiBootParam
{
u32 system_work[5];
u8 handshake_data;
u8 padding;
u16 handshake_timeout;
u8 probe_count;
u8 client_data[MULTIBOOT_NCHILD];
u8 palette_data;
u8 response_bit;
u8 client_bit;
u8 reserved1;
u8 *boot_srcp;
u8 *boot_endp;
u8 *masterp;
u8 *reserved2[MULTIBOOT_NCHILD];
u32 system_work2[4];
u8 sendflag;
u8 probe_target_bit;
u8 check_wait;
u8 server_type;
};
#define MULTIBOOT_ERROR_04 0x04
#define MULTIBOOT_ERROR_08 0x08
#define MULTIBOOT_ERROR_0c 0x0c
#define MULTIBOOT_ERROR_40 0x40
#define MULTIBOOT_ERROR_44 0x44
#define MULTIBOOT_ERROR_48 0x48
#define MULTIBOOT_ERROR_4c 0x4c
#define MULTIBOOT_ERROR_80 0x80
#define MULTIBOOT_ERROR_84 0x84
#define MULTIBOOT_ERROR_88 0x88
#define MULTIBOOT_ERROR_8c 0x8c
#define MULTIBOOT_ERROR_NO_PROBE_TARGET 0x50
#define MULTIBOOT_ERROR_NO_DLREADY 0x60
#define MULTIBOOT_ERROR_BOOT_FAILURE 0x70
#define MULTIBOOT_ERROR_HANDSHAKE_FAILURE 0x71
#define MULTIBOOT_CONNECTION_CHECK_WAIT 15
#define MULTIBOOT_SERVER_TYPE_NORMAL 0
#define MULTIBOOT_SERVER_TYPE_QUICK 1
#define MULTIBOOT_HANDSHAKE_TIMEOUT 400
#endif // GUARD_GBA_MULTIBOOT_H

48
include/gba/syscall.h Normal file
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#ifndef GUARD_GBA_SYSCALL_H
#define GUARD_GBA_SYSCALL_H
#define RESET_EWRAM 0x01
#define RESET_IWRAM 0x02
#define RESET_PALETTE 0x04
#define RESET_VRAM 0x08
#define RESET_OAM 0x10
#define RESET_SIO_REGS 0x20
#define RESET_SOUND_REGS 0x40
#define RESET_REGS 0x80
#define RESET_ALL 0xFF
void SoftReset(u32 resetFlags);
void RegisterRamReset(u32 resetFlags);
void VBlankIntrWait(void);
u16 Sqrt(u32 num);
u16 ArcTan2(s16 x, s16 y);
#define CPU_SET_SRC_FIXED 0x01000000
#define CPU_SET_16BIT 0x00000000
#define CPU_SET_32BIT 0x04000000
void CpuSet(const void *src, void *dest, u32 control);
#define CPU_FAST_SET_SRC_FIXED 0x01000000
void CpuFastSet(const void *src, void *dest, u32 control);
void BgAffineSet(struct BgAffineSrcData *src, struct BgAffineDstData *dest, s32 count);
void ObjAffineSet(struct ObjAffineSrcData *src, void *dest, s32 count, s32 offset);
void LZ77UnCompWram(const void *src, void *dest);
void LZ77UnCompVram(const void *src, void *dest);
void RLUnCompWram(const void *src, void *dest);
void RLUnCompVram(const void *src, void *dest);
int MultiBoot(struct MultiBootParam *mp);
#endif // GUARD_GBA_SYSCALL_H

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#ifndef GUARD_GBA_TYPES_H
#define GUARD_GBA_TYPES_H
#include <stdint.h>
typedef uint8_t u8;
typedef uint16_t u16;
typedef uint32_t u32;
typedef uint64_t u64;
typedef int8_t s8;
typedef int16_t s16;
typedef int32_t s32;
typedef int64_t s64;
typedef volatile u8 vu8;
typedef volatile u16 vu16;
typedef volatile u32 vu32;
typedef volatile u64 vu64;
typedef volatile s8 vs8;
typedef volatile s16 vs16;
typedef volatile s32 vs32;
typedef volatile s64 vs64;
typedef float f32;
typedef double f64;
typedef u8 bool8;
typedef u16 bool16;
typedef u32 bool32;
struct PlttData
{
u16 r:5; // red
u16 g:5; // green
u16 b:5; // blue
u16 unused_15:1;
} /*__attribute__((packed))*/;
struct OamData
{
/*0x00*/ u32 y:8;
/*0x01*/ u32 affineMode:2; // 0x1, 0x2 = 0x3
u32 objMode:2; // 0x4, 0x8 = 0xC
u32 mosaic:1; // 0x10
u32 bpp:1; // 0x20
u32 shape:2; // 0x40, 0x80
/*0x02*/ u32 x:9;
u32 matrixNum:5; // bits 3/4 are h-flip/v-flip if not in affine mode
u32 size:2;
/*0x04*/ u16 tileNum:10;
u16 priority:2;
u16 paletteNum:4;
/*0x06*/ u16 affineParam;
};
#define ST_OAM_OBJ_NORMAL 0
#define ST_OAM_OBJ_BLEND 1
#define ST_OAM_OBJ_WINDOW 2
#define ST_OAM_AFFINE_OFF 0
#define ST_OAM_AFFINE_NORMAL 1
#define ST_OAM_AFFINE_ERASE 2
#define ST_OAM_AFFINE_DOUBLE 3
#define ST_OAM_AFFINE_ON_MASK 1
#define ST_OAM_AFFINE_DOUBLE_MASK 2
#define ST_OAM_4BPP 0
#define ST_OAM_8BPP 1
#define ST_OAM_SQUARE 0
#define ST_OAM_H_RECTANGLE 1
#define ST_OAM_V_RECTANGLE 2
struct BgAffineSrcData
{
s32 texX;
s32 texY;
s16 scrX;
s16 scrY;
s16 sx;
s16 sy;
u16 alpha;
};
struct BgAffineDstData
{
s16 pa;
s16 pb;
s16 pc;
s16 pd;
s32 dx;
s32 dy;
};
struct ObjAffineSrcData
{
s16 xScale;
s16 yScale;
u16 rotation;
};
// Multi-player SIO Control Structure
struct SioMultiCnt
{
u16 baudRate:2; // baud rate
u16 si:1; // SI terminal
u16 sd:1; // SD terminal
u16 id:2; // ID
u16 error:1; // error flag
u16 enable:1; // SIO enable
u16 unused_11_8:4;
u16 mode:2; // communication mode (should equal 2)
u16 intrEnable:1; // IRQ enable
u16 unused_15:1;
u16 data; // data
};
#define ST_SIO_MULTI_MODE 2 // Multi-player communication mode
// baud rate
#define ST_SIO_9600_BPS 0 // 9600 bps
#define ST_SIO_38400_BPS 1 // 38400 bps
#define ST_SIO_57600_BPS 2 // 57600 bps
#define ST_SIO_115200_BPS 3 // 115200 bps
#endif // GUARD_GBA_TYPES_H

39
include/global.h Normal file
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#ifndef GUARD_GLOBAL_H
#define GUARD_GLOBAL_H
#include "gba/gba.h"
// IDE support
#ifdef __APPLE__
#define _(x) x
#define __(x) x
#define INCBIN_U8 {0}
#define INCBIN_U16 {0}
#define INCBIN_U32 {0}
#define INCBIN_S8 {0}
#define INCBIN_S16 {0}
#define INCBIN_S32 {0}
void * memcpy (void *, const void *, size_t);
void * memset (void *, int, size_t);
int strcmp (const char *, const char *);
#endif
// Prevent cross-jump optimization.
#define BLOCK_CROSS_JUMP asm("");
// to help in decompiling
#define asm_comment(x) asm volatile("@ -- " x " -- ")
#define asm_unified(x) asm(".syntax unified\n" x "\n.syntax divided\n")
#define nonmatching(fndec, x) {\
__attribute__((naked))\
fndec\
{\
asm_unified(x);\
}\
}
#define ARRAY_COUNT(array) (sizeof(array) / sizeof((array)[0]))
#endif // GUARD_GLOBAL_H

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ld_script.sed Normal file
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/<EWRAM>/ {
r sym_ewram.ld
d
}
/<EWRAM2>/ {
r sym_ewram2.ld
d
}
/<IWRAM>/ {
r sym_iwram.ld
d
}

107
ld_script.txt Normal file
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ENTRY(Start)
SECTIONS {
. = 0x2000000;
ewram (NOLOAD) :
ALIGN(4)
{
ewram_start = .;
<EWRAM>
. = ALIGN(4);
src/agb_flash.o(.bss);
. = ALIGN(4);
tools/agbcc/lib/libgcc.a:fp-bit.o(.bss);
. = ALIGN(4);
tools/agbcc/lib/libgcc.a:dp-bit.o(.bss);
<EWRAM2>
. = 0x40000;
}
. = 0x3000000;
iwram (NOLOAD) :
ALIGN(4)
{
iwram_start = .;
<IWRAM>
. = 0x8000;
}
. = 0x8000000;
.text :
ALIGN(4)
{
asm/crt0.o(.text);
asm/code.o(.text);
src/main.o(.text);
asm/code_800B540.o(.text);
asm/m4a.o(.text);
asm/syscall.o(.text);
src/agb_flash.o(.text);
src/agb_flash_1m.o(.text);
src/agb_flash_mx.o(.text);
src/agb_flash_le.o(.text);
tools/agbcc/lib/libgcc.a:_call_via_rX.o(.text);
tools/agbcc/lib/libgcc.a:_divsi3.o(.text);
tools/agbcc/lib/libgcc.a:_dvmd_tls.o(.text);
tools/agbcc/lib/libgcc.a:_fixunssfsi.o(.text);
tools/agbcc/lib/libgcc.a:_modsi3.o(.text);
tools/agbcc/lib/libgcc.a:_umodsi3.o(.text);
tools/agbcc/lib/libgcc.a:fp-bit.o(.text);
tools/agbcc/lib/libgcc.a:_muldi3.o(.text);
tools/agbcc/lib/libgcc.a:dp-bit.o(.text);
tools/agbcc/lib/libgcc.a:_lshrdi3.o(.text);
tools/agbcc/lib/libgcc.a:_negdi2.o(.text);
asm/libc.o(.text);
} =0
.rodata :
ALIGN(4)
{
data/data.o(.rodata);
src/agb_flash.o(.rodata);
src/agb_flash_1m.o(.rodata);
src/agb_flash_mx.o(.rodata);
src/agb_flash_le.o(.rodata);
data/libc_data.o(.rodata);
data/data_8270000.o(.rodata);
} =0
unk_code_section :
ALIGN(4)
{
unk_code = .;
asm/code_8272724.o(.rodata);
asm/code_8272724.o(.text);
unk_code_end = .;
}
unk_code_ram_end = unk_code_ram + (unk_code_end - unk_code);
end = unk_code_ram_end;
. = 0x8300000;
unk_data :
ALIGN(4)
{
data/unk_data.o(.rodata);
}
/* DWARF 2 sections */
.debug_aranges 0 : { *(.debug_aranges) }
.debug_pubnames 0 : { *(.debug_pubnames) }
.debug_info 0 : { *(.debug_info) }
.debug_abbrev 0 : { *(.debug_abbrev) }
.debug_line 0 : { *(.debug_line) }
.debug_frame 0 : { *(.debug_frame) }
.debug_str 0 : { *(.debug_str) }
.debug_loc 0 : { *(.debug_loc) }
.debug_macinfo 0 : { *(.debug_macinfo) }
/* Discard everything not specifically mentioned above. */
/DISCARD/ :
{
*(*);
}
}

1
rom.md5 Normal file
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2100CF6F17E12CD34F1513647DFA506B pmd_red.gba

284
src/agb_flash.c Normal file
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#include "gba/gba.h"
#include "gba/flash_internal.h"
static u8 sTimerNum;
static u16 sTimerCount;
static vu16 *sTimerReg;
static u16 sSavedIme;
void SetReadFlash1(u16 *dest);
void SwitchFlashBank(u8 bankNum)
{
FLASH_WRITE(0x5555, 0xAA);
FLASH_WRITE(0x2AAA, 0x55);
FLASH_WRITE(0x5555, 0xB0);
FLASH_WRITE(0x0000, bankNum);
}
#define DELAY() \
do { \
vu16 i; \
for (i = 20000; i != 0; i--) \
; \
} while (0)
u16 ReadFlashId(void)
{
u16 flashId;
u16 readFlash1Buffer[0x20];
u8 (*readFlash1)(u8 *);
SetReadFlash1(readFlash1Buffer);
readFlash1 = (u8 (*)(u8 *))((s32)readFlash1Buffer + 1);
// Enter ID mode.
FLASH_WRITE(0x5555, 0xAA);
FLASH_WRITE(0x2AAA, 0x55);
FLASH_WRITE(0x5555, 0x90);
DELAY();
flashId = readFlash1(FLASH_BASE + 1) << 8;
flashId |= readFlash1(FLASH_BASE);
// Leave ID mode.
FLASH_WRITE(0x5555, 0xAA);
FLASH_WRITE(0x2AAA, 0x55);
FLASH_WRITE(0x5555, 0xF0);
FLASH_WRITE(0x5555, 0xF0);
DELAY();
return flashId;
}
void FlashTimerIntr(void)
{
if (sTimerCount != 0 && --sTimerCount == 0)
gFlashTimeoutFlag = 1;
}
u16 SetFlashTimerIntr(u8 timerNum, void (**intrFunc)(void))
{
if (timerNum >= 4)
return 1;
sTimerNum = timerNum;
sTimerReg = &REG_TMCNT(sTimerNum);
*intrFunc = FlashTimerIntr;
return 0;
}
void StartFlashTimer(u8 phase)
{
const u16 *maxTime = &gFlashMaxTime[phase * 3];
sSavedIme = REG_IME;
REG_IME = 0;
sTimerReg[1] = 0;
REG_IE |= (INTR_FLAG_TIMER0 << sTimerNum);
gFlashTimeoutFlag = 0;
sTimerCount = *maxTime++;
*sTimerReg++ = *maxTime++;
*sTimerReg-- = *maxTime++;
REG_IF = (INTR_FLAG_TIMER0 << sTimerNum);
REG_IME = 1;
}
void StopFlashTimer(void)
{
REG_IME = 0;
*sTimerReg++ = 0;
*sTimerReg-- = 0;
REG_IE &= ~(INTR_FLAG_TIMER0 << sTimerNum);
REG_IME = sSavedIme;
}
u8 ReadFlash1(u8 *addr)
{
return *addr;
}
void SetReadFlash1(u16 *dest)
{
u16 *src;
u16 i;
PollFlashStatus = (u8 (*)(u8 *))((s32)dest + 1);
src = (u16 *)ReadFlash1;
src = (u16 *)((s32)src & ~1);
i = ((s32)SetReadFlash1 - (s32)ReadFlash1) >> 1;
while (i != 0)
{
*dest++ = *src++;
i--;
}
}
void ReadFlash_Core(u8 *src, u8 *dest, u32 size)
{
while (size-- != 0)
{
*dest++ = *src++;
}
}
void ReadFlash(u16 sectorNum, u32 offset, u8 *dest, u32 size)
{
u8 *src;
u16 i;
u16 readFlash_Core_Buffer[0x40];
u16 *funcSrc;
u16 *funcDest;
void (*readFlash_Core)(u8 *, u8 *, u32);
REG_WAITCNT = (REG_WAITCNT & ~WAITCNT_SRAM_MASK) | WAITCNT_SRAM_8;
if (gFlash->romSize == FLASH_ROM_SIZE_1M)
{
SwitchFlashBank(sectorNum / SECTORS_PER_BANK);
sectorNum %= SECTORS_PER_BANK;
}
funcSrc = (u16 *)ReadFlash_Core;
funcSrc = (u16 *)((s32)funcSrc & ~1);
funcDest = readFlash_Core_Buffer;
i = ((s32)ReadFlash - (s32)ReadFlash_Core) >> 1;
while (i != 0)
{
*funcDest++ = *funcSrc++;
i--;
}
readFlash_Core = (void (*)(u8 *, u8 *, u32))((s32)readFlash_Core_Buffer + 1);
src = FLASH_BASE + (sectorNum << gFlash->sector.shift) + offset;
readFlash_Core(src, dest, size);
}
u32 VerifyFlashSector_Core(u8 *src, u8 *tgt, u32 size)
{
while (size-- != 0)
{
if (*tgt++ != *src++)
return (u32)(tgt - 1);
}
return 0;
}
u32 VerifyFlashSector(u16 sectorNum, u8 *src)
{
u16 i;
u16 verifyFlashSector_Core_Buffer[0x80];
u16 *funcSrc;
u16 *funcDest;
u8 *tgt;
u16 size;
u32 (*verifyFlashSector_Core)(u8 *, u8 *, u32);
REG_WAITCNT = (REG_WAITCNT & ~WAITCNT_SRAM_MASK) | WAITCNT_SRAM_8;
if (gFlash->romSize == FLASH_ROM_SIZE_1M)
{
SwitchFlashBank(sectorNum / SECTORS_PER_BANK);
sectorNum %= SECTORS_PER_BANK;
}
funcSrc = (u16 *)VerifyFlashSector_Core;
funcSrc = (u16 *)((s32)funcSrc & ~1);
funcDest = verifyFlashSector_Core_Buffer;
i = ((s32)VerifyFlashSector - (s32)VerifyFlashSector_Core) >> 1;
while (i != 0)
{
*funcDest++ = *funcSrc++;
i--;
}
verifyFlashSector_Core = (u32 (*)(u8 *, u8 *, u32))((s32)verifyFlashSector_Core_Buffer + 1);
tgt = FLASH_BASE + (sectorNum << gFlash->sector.shift);
size = gFlash->sector.size;
return verifyFlashSector_Core(src, tgt, size);
}
u32 VerifyFlashSectorNBytes(u16 sectorNum, u8 *src, u32 n)
{
u16 i;
u16 verifyFlashSector_Core_Buffer[0x80];
u16 *funcSrc;
u16 *funcDest;
u8 *tgt;
u32 (*verifyFlashSector_Core)(u8 *, u8 *, u32);
if (gFlash->romSize == FLASH_ROM_SIZE_1M)
{
SwitchFlashBank(sectorNum / SECTORS_PER_BANK);
sectorNum %= SECTORS_PER_BANK;
}
REG_WAITCNT = (REG_WAITCNT & ~WAITCNT_SRAM_MASK) | WAITCNT_SRAM_8;
funcSrc = (u16 *)VerifyFlashSector_Core;
funcSrc = (u16 *)((s32)funcSrc & ~1);
funcDest = verifyFlashSector_Core_Buffer;
i = ((s32)VerifyFlashSector - (s32)VerifyFlashSector_Core) >> 1;
while (i != 0)
{
*funcDest++ = *funcSrc++;
i--;
}
verifyFlashSector_Core = (u32 (*)(u8 *, u8 *, u32))((s32)verifyFlashSector_Core_Buffer + 1);
tgt = FLASH_BASE + (sectorNum << gFlash->sector.shift);
return verifyFlashSector_Core(src, tgt, n);
}
u32 ProgramFlashSectorAndVerify(u16 sectorNum, u8 *src)
{
u8 i;
u32 result;
for (i = 0; i < 3; i++)
{
result = ProgramFlashSector(sectorNum, src);
if (result != 0)
continue;
result = VerifyFlashSector(sectorNum, src);
if (result == 0)
break;
}
return result;
}
u32 ProgramFlashSectorAndVerifyNBytes(u16 sectorNum, u8 *src, u32 n)
{
u8 i;
u32 result;
for (i = 0; i < 3; i++)
{
result = ProgramFlashSector(sectorNum, src);
if (result != 0)
continue;
result = VerifyFlashSectorNBytes(sectorNum, src, n);
if (result == 0)
break;
}
return result;
}

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#include "gba/gba.h"
#include "gba/flash_internal.h"
static const char AgbLibFlashVersion[] = "FLASH1M_V102";
const struct FlashSetupInfo * const sSetupInfos[] =
{
&MX29L010,
&LE26FV10N1TS,
&DefaultFlash
};
u16 IdentifyFlash(void)
{
u16 result;
u16 flashId;
const struct FlashSetupInfo * const *setupInfo;
REG_WAITCNT = (REG_WAITCNT & ~WAITCNT_SRAM_MASK) | WAITCNT_SRAM_8;
flashId = ReadFlashId();
setupInfo = sSetupInfos;
result = 1;
for (;;)
{
if ((*setupInfo)->type.ids.separate.makerId == 0)
break;
if (flashId == (*setupInfo)->type.ids.joined)
{
result = 0;
break;
}
setupInfo++;
}
ProgramFlashSector = (*setupInfo)->programFlashSector;
EraseFlashChip = (*setupInfo)->eraseFlashChip;
EraseFlashSector = (*setupInfo)->eraseFlashSector;
WaitForFlashWrite = (*setupInfo)->waitForFlashWrite;
gFlashMaxTime = (*setupInfo)->maxTime;
gFlash = &(*setupInfo)->type;
return result;
}
u16 WaitForFlashWrite_Common(u8 phase, u8 *addr, u8 lastData)
{
u16 result = 0;
u8 status;
StartFlashTimer(phase);
while ((status = PollFlashStatus(addr)) != lastData)
{
if (status & 0x20)
{
// The write operation exceeded the flash chip's time limit.
if (PollFlashStatus(addr) == lastData)
break;
FLASH_WRITE(0x5555, 0xF0);
result = phase | 0xA000u;
break;
}
if (gFlashTimeoutFlag)
{
if (PollFlashStatus(addr) == lastData)
break;
FLASH_WRITE(0x5555, 0xF0);
result = phase | 0xC000u;
break;
}
}
StopFlashTimer();
return result;
}

30
src/agb_flash_le.c Normal file
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#include "gba/gba.h"
#include "gba/flash_internal.h"
const u16 leMaxTime[] =
{
10, 65469, TIMER_ENABLE | TIMER_INTR_ENABLE | TIMER_256CLK,
10, 65469, TIMER_ENABLE | TIMER_INTR_ENABLE | TIMER_256CLK,
2000, 65469, TIMER_ENABLE | TIMER_INTR_ENABLE | TIMER_256CLK,
2000, 65469, TIMER_ENABLE | TIMER_INTR_ENABLE | TIMER_256CLK,
};
const struct FlashSetupInfo LE26FV10N1TS =
{
ProgramFlashSector_MX,
EraseFlashChip_MX,
EraseFlashSector_MX,
WaitForFlashWrite_Common,
leMaxTime,
{
131072, // ROM size
{
4096, // sector size
12, // bit shift to multiply by sector size (4096 == 1 << 12)
32, // number of sectors
0 // appears to be unused
},
{ 3, 1 }, // wait state setup data
{ { 0x62, 0x13 } } // ID
}
};

166
src/agb_flash_mx.c Normal file
View File

@ -0,0 +1,166 @@
#include "gba/gba.h"
#include "gba/flash_internal.h"
const u16 mxMaxTime[] =
{
10, 65469, TIMER_ENABLE | TIMER_INTR_ENABLE | TIMER_256CLK,
10, 65469, TIMER_ENABLE | TIMER_INTR_ENABLE | TIMER_256CLK,
2000, 65469, TIMER_ENABLE | TIMER_INTR_ENABLE | TIMER_256CLK,
2000, 65469, TIMER_ENABLE | TIMER_INTR_ENABLE | TIMER_256CLK,
};
const struct FlashSetupInfo MX29L010 =
{
ProgramFlashSector_MX,
EraseFlashChip_MX,
EraseFlashSector_MX,
WaitForFlashWrite_Common,
mxMaxTime,
{
131072, // ROM size
{
4096, // sector size
12, // bit shift to multiply by sector size (4096 == 1 << 12)
32, // number of sectors
0 // appears to be unused
},
{ 3, 1 }, // wait state setup data
{ { 0xC2, 0x09 } } // ID
}
};
const struct FlashSetupInfo DefaultFlash =
{
ProgramFlashSector_MX,
EraseFlashChip_MX,
EraseFlashSector_MX,
WaitForFlashWrite_Common,
mxMaxTime,
{
131072, // ROM size
{
4096, // sector size
12, // bit shift to multiply by sector size (4096 == 1 << 12)
32, // number of sectors
0 // appears to be unused
},
{ 3, 1 }, // wait state setup data
{ { 0x00, 0x00 } } // ID of 0
}
};
u16 EraseFlashChip_MX(void)
{
u16 result;
u16 readFlash1Buffer[0x20];
REG_WAITCNT = (REG_WAITCNT & ~WAITCNT_SRAM_MASK) | gFlash->wait[0];
FLASH_WRITE(0x5555, 0xAA);
FLASH_WRITE(0x2AAA, 0x55);
FLASH_WRITE(0x5555, 0x80);
FLASH_WRITE(0x5555, 0xAA);
FLASH_WRITE(0x2AAA, 0x55);
FLASH_WRITE(0x5555, 0x10);
SetReadFlash1(readFlash1Buffer);
result = WaitForFlashWrite(3, FLASH_BASE, 0xFF);
REG_WAITCNT = (REG_WAITCNT & ~WAITCNT_SRAM_MASK) | WAITCNT_SRAM_8;
return result;
}
u16 EraseFlashSector_MX(u16 sectorNum)
{
u16 numTries;
u16 result;
u8 *addr;
u16 readFlash1Buffer[0x20];
if (sectorNum >= gFlash->sector.count)
return 0x80FF;
SwitchFlashBank(sectorNum / SECTORS_PER_BANK);
sectorNum %= SECTORS_PER_BANK;
numTries = 0;
try_erase:
REG_WAITCNT = (REG_WAITCNT & ~WAITCNT_SRAM_MASK) | gFlash->wait[0];
addr = FLASH_BASE + (sectorNum << gFlash->sector.shift);
FLASH_WRITE(0x5555, 0xAA);
FLASH_WRITE(0x2AAA, 0x55);
FLASH_WRITE(0x5555, 0x80);
FLASH_WRITE(0x5555, 0xAA);
FLASH_WRITE(0x2AAA, 0x55);
*addr = 0x30;
SetReadFlash1(readFlash1Buffer);
result = WaitForFlashWrite(2, addr, 0xFF);
if (!(result & 0xA000) || numTries != 0)
goto done;
numTries = 1;
goto try_erase;
done:
REG_WAITCNT = (REG_WAITCNT & ~WAITCNT_SRAM_MASK) | WAITCNT_SRAM_8;
return result;
}
static u16 ProgramByte(u8 *src, u8 *dest)
{
FLASH_WRITE(0x5555, 0xAA);
FLASH_WRITE(0x2AAA, 0x55);
FLASH_WRITE(0x5555, 0xA0);
*dest = *src;
return WaitForFlashWrite(1, dest, *src);
}
u16 ProgramFlashSector_MX(u16 sectorNum, u8 *src)
{
u16 result;
u8 *dest;
u16 readFlash1Buffer[0x20];
if (sectorNum >= gFlash->sector.count)
return 0x80FF;
result = EraseFlashSector_MX(sectorNum);
if (result != 0)
return result;
SwitchFlashBank(sectorNum / SECTORS_PER_BANK);
sectorNum %= SECTORS_PER_BANK;
SetReadFlash1(readFlash1Buffer);
REG_WAITCNT = (REG_WAITCNT & ~WAITCNT_SRAM_MASK) | gFlash->wait[0];
gFlashNumRemainingBytes = gFlash->sector.size;
dest = FLASH_BASE + (sectorNum << gFlash->sector.shift);
while (gFlashNumRemainingBytes > 0)
{
result = ProgramByte(src, dest);
if (result != 0)
break;
gFlashNumRemainingBytes--;
src++;
dest++;
}
return result;
}

108
src/main.c Normal file
View File

@ -0,0 +1,108 @@
#include "global.h"
extern char ewram_start[];
extern u16 gUnknown_202D7FC;
extern u8 gUnknown_202D7FE;
extern char alt_203B038[];
extern char gUnknown_203B038[];
extern char gUnknown_203BC04[];
extern char iwram_start[];
extern char alt_3001B58[];
extern char unk_code_ram[];
extern char unk_code_ram_end[];
extern u8 gUnknown_80B9BF1[];
extern char gUnknown_8270000[];
extern char unk_code[];
extern void sub_800CDA8(int);
extern void sub_800B540(void);
extern void sub_800CF0C(void);
extern void SeedRng(u8 *);
extern void sub_8004D78(void);
extern void nullsub_9(void);
extern void nullsub_6(void);
extern void sub_80047E8(void);
extern void InitBGPaletteBuffer(void);
extern void sub_80057E8(void);
extern void sub_800A8C4(void);
extern void sub_8006218(void);
extern void sub_80098A0(void);
extern void sub_80096E0(void);
extern void sub_800B6F4(int, void *);
extern void GameLoop(void);
extern void Hang(void);
extern void sub_800CE54(void);
void AgbMain(void)
{
u8 value[4];
u8 seed[6];
REG_WAITCNT = WAITCNT_PREFETCH_ENABLE | WAITCNT_WS0_S_1 | WAITCNT_WS0_N_3;
DmaStop(0);
DmaStop(1);
DmaStop(2);
DmaStop(3);
if (gUnknown_203BC04 - gUnknown_203B038 > 0)
CpuCopy32(gUnknown_8270000, gUnknown_203B038, gUnknown_203BC04 - gUnknown_203B038);
if (alt_203B038 - ewram_start > 0)
{
memset(value, 0, 4);
CpuSet(&value, ewram_start, CPU_SET_SRC_FIXED | CPU_SET_32BIT | (((alt_203B038 - ewram_start) / 4) & 0x1FFFFF));
}
if (unk_code_ram_end - unk_code_ram > 0)
CpuCopy32(unk_code, unk_code_ram, unk_code_ram_end - unk_code_ram);
if (alt_3001B58 - iwram_start > 0)
{
memset(value, 0, 4);
CpuSet(&value, iwram_start, CPU_SET_SRC_FIXED | CPU_SET_32BIT | (((alt_3001B58 - iwram_start) / 4) & 0x1FFFFF));
}
REG_WIN0H = 0;
REG_WIN1H = 0;
REG_WIN0V = 0;
REG_WIN1V = 0;
REG_WININ = 16191;
REG_WINOUT = 61;
gUnknown_202D7FC = REG_BLDCNT = 15426;
REG_BLDALPHA = 1546;
gUnknown_202D7FE = 0;
REG_BG0CNT = 11264;
REG_BG1CNT = 11521;
REG_BG2CNT = 11786;
REG_BG3CNT = 12043;
REG_DISPCNT = 32704;
sub_800CDA8(1);
sub_800B540();
sub_800CF0C();
memcpy(seed, gUnknown_80B9BF1, 6);
SeedRng(seed);
sub_8004D78();
nullsub_9();
nullsub_6();
sub_80047E8();
InitBGPaletteBuffer();
sub_80057E8();
sub_800A8C4();
sub_8006218();
sub_80098A0();
sub_80096E0();
sub_800B6F4(1, sub_800CE54);
REG_DISPCNT = 32576;
GameLoop();
Hang();
}

1054
sym_ewram.txt Normal file
View File

File diff suppressed because it is too large Load Diff

700
sym_ewram2.txt Normal file
View File

@ -0,0 +1,700 @@
.align 2
gUnknown_2039E18: @ 2039E18
.space 0x4
gUnknown_2039E1C: @ 2039E1C
.space 0x4
gUnknown_2039E20: @ 2039E20
.space 0x4
gUnknown_2039E24: @ 2039E24
.space 0x4
gUnknown_2039E28: @ 2039E28
.space 0xA8
gUnknown_2039ED0: @ 2039ED0
.space 0xFB0
gUnknown_203AE80: @ 203AE80
.space 0x4
gUnknown_203AE84: @ 203AE84
.space 0x84
gUnknown_203AF08: @ 203AF08
.space 0x4
gUnknown_203AF0C: @ 203AF0C
.space 0x4
gUnknown_203AF10: @ 203AF10
.space 0x100
gFlashTimeoutFlag: @ 203B010
.space 0x4
PollFlashStatus: @ 203B014
.space 0x4
WaitForFlashWrite: @ 203B018
.space 0x4
ProgramFlashSector: @ 203B01C
.space 0x4
gFlash: @ 203B020
.space 0x4
gFlashNumRemainingBytes: @ 203B024
.space 0x4
EraseFlashChip: @ 203B028
.space 0x4
EraseFlashSector: @ 203B02C
.space 0x4
gFlashMaxTime: @ 203B030
.space 0x4
gUnknown_203B034: @ 203B034
.space 0x4
alt_203B038:
gUnknown_203B038: @ 203B038
.space 0x4
gUnknown_203B03C: @ 203B03C
.space 0x4
gUnknown_203B040: @ 203B040
.space 0x30
gUnknown_203B070: @ 203B070
.space 0x4
gUnknown_203B074: @ 203B074
.space 0x4
gUnknown_203B078: @ 203B078
.space 0x4
gUnknown_203B07C: @ 203B07C
.space 0x4
gUnknown_203B080: @ 203B080
.space 0x4
gUnknown_203B084: @ 203B084
.space 0x4
gUnknown_203B088: @ 203B088
.space 0x4
gUnknown_203B08C: @ 203B08C
.space 0x4
gUnknown_203B090: @ 203B090
.space 0x4
gUnknown_203B094: @ 203B094
.space 0x4
gUnknown_203B098: @ 203B098
.space 0x1
gUnknown_203B099: @ 203B099
.space 0x1
gUnknown_203B09A: @ 203B09A
.space 0x1
gUnknown_203B09B: @ 203B09B
.space 0x1
gUnknown_203B09C: @ 203B09C
.space 0x4
gUnknown_203B0A0: @ 203B0A0
.space 0x4
gUnknown_203B0A4: @ 203B0A4
.space 0x4
gUnknown_203B0A8: @ 203B0A8
.space 0x2
gUnknown_203B0AA: @ 203B0AA
.space 0x2
gUnknown_203B0AC: @ 203B0AC
.space 0x2
gUnknown_203B0AE: @ 203B0AE
.space 0x2
gUnknown_203B0B0: @ 203B0B0
.space 0x2
gUnknown_203B0B2: @ 203B0B2
.space 0x2
gUnknown_203B0B4: @ 203B0B4
.space 0x4
gUnknown_203B0B8: @ 203B0B8
.space 0x4
gUnknown_203B0BC: @ 203B0BC
.space 0x2
gUnknown_203B0BE: @ 203B0BE
.space 0xE
gUnknown_203B0CC: @ 203B0CC
.space 0x4
gUnknown_203B0D0: @ 203B0D0
.space 0x4
gUnknown_203B0D4: @ 203B0D4
.space 0x4
gUnknown_203B0D8: @ 203B0D8
.space 0x4
gUnknown_203B0DC: @ 203B0DC
.space 0x8
gUnknown_203B0E4: @ 203B0E4
.space 0x4
gUnknown_203B0E8: @ 203B0E8
.space 0x4
gUnknown_203B0EC: @ 203B0EC
.space 0x60
gUnknown_203B14C: @ 203B14C
.space 0x4
gUnknown_203B150: @ 203B150
.space 0x2C
gUnknown_203B17C: @ 203B17C
.space 0x4
gUnknown_203B180: @ 203B180
.space 0x4
gUnknown_203B184: @ 203B184
.space 0x4
gUnknown_203B188: @ 203B188
.space 0x4
gUnknown_203B18C: @ 203B18C
.space 0x4
gUnknown_203B190: @ 203B190
.space 0x4
gUnknown_203B194: @ 203B194
.space 0x4
gUnknown_203B198: @ 203B198
.space 0x60
gUnknown_203B1F8: @ 203B1F8
.space 0x4
gUnknown_203B1FC: @ 203B1FC
.space 0x4
gUnknown_203B200: @ 203B200
.space 0x4
gUnknown_203B204: @ 203B204
.space 0x4
gUnknown_203B208: @ 203B208
.space 0x4
gUnknown_203B20C: @ 203B20C
.space 0x4
gUnknown_203B210: @ 203B210
.space 0x4
gUnknown_203B214: @ 203B214
.space 0x4
gUnknown_203B218: @ 203B218
.space 0x4
gUnknown_203B21C: @ 203B21C
.space 0x4
gUnknown_203B220: @ 203B220
.space 0x4
gUnknown_203B224: @ 203B224
.space 0x4
gUnknown_203B228: @ 203B228
.space 0x2
gUnknown_203B22A: @ 203B22A
.space 0x2
gUnknown_203B22C: @ 203B22C
.space 0x4
gUnknown_203B230: @ 203B230
.space 0x4
gUnknown_203B234: @ 203B234
.space 0x4
gUnknown_203B238: @ 203B238
.space 0x4
gUnknown_203B23C: @ 203B23C
.space 0x4
gUnknown_203B240: @ 203B240
.space 0x4
gUnknown_203B244: @ 203B244
.space 0x4
gUnknown_203B248: @ 203B248
.space 0x4
gUnknown_203B24C: @ 203B24C
.space 0x2
gUnknown_203B24E: @ 203B24E
.space 0x2
gUnknown_203B250: @ 203B250
.space 0x4
gUnknown_203B254: @ 203B254
.space 0x4
gUnknown_203B258: @ 203B258
.space 0x4
gUnknown_203B25C: @ 203B25C
.space 0x4
gUnknown_203B260: @ 203B260
.space 0x4
gUnknown_203B264: @ 203B264
.space 0x4
gUnknown_203B268: @ 203B268
.space 0x4
gUnknown_203B26C: @ 203B26C
.space 0x4
gUnknown_203B270: @ 203B270
.space 0x4
gUnknown_203B274: @ 203B274
.space 0x4
gUnknown_203B278: @ 203B278
.space 0x4
gUnknown_203B27C: @ 203B27C
.space 0x4
gUnknown_203B280: @ 203B280
.space 0x4
gUnknown_203B284: @ 203B284
.space 0x4
gUnknown_203B288: @ 203B288
.space 0x2
gUnknown_203B28A: @ 203B28A
.space 0x2
gUnknown_203B28C: @ 203B28C
.space 0x4
gUnknown_203B290: @ 203B290
.space 0x4
gUnknown_203B294: @ 203B294
.space 0x4
gUnknown_203B298: @ 203B298
.space 0x4
gUnknown_203B29C: @ 203B29C
.space 0x2
gUnknown_203B29E: @ 203B29E
.space 0x2
gUnknown_203B2A0: @ 203B2A0
.space 0x4
gUnknown_203B2A4: @ 203B2A4
.space 0x4
gUnknown_203B2A8: @ 203B2A8
.space 0x2
gUnknown_203B2AA: @ 203B2AA
.space 0x2
gUnknown_203B2AC: @ 203B2AC
.space 0x4
gUnknown_203B2B0: @ 203B2B0
.space 0x4
gUnknown_203B2B4: @ 203B2B4
.space 0x4
gUnknown_203B2B8: @ 203B2B8
.space 0x4
gUnknown_203B2BC: @ 203B2BC
.space 0x4
gUnknown_203B2C0: @ 203B2C0
.space 0x4
gUnknown_203B2C4: @ 203B2C4
.space 0x4
gUnknown_203B2C8: @ 203B2C8
.space 0x4
gUnknown_203B2CC: @ 203B2CC
.space 0x4
gUnknown_203B2D0: @ 203B2D0
.space 0x2
gUnknown_203B2D2: @ 203B2D2
.space 0x2
gUnknown_203B2D4: @ 203B2D4
.space 0x4
gUnknown_203B2D8: @ 203B2D8
.space 0x4
gUnknown_203B2DC: @ 203B2DC
.space 0x4
gUnknown_203B2E0: @ 203B2E0
.space 0x4
gUnknown_203B2E4: @ 203B2E4
.space 0x4
gUnknown_203B2E8: @ 203B2E8
.space 0x4
gUnknown_203B2EC: @ 203B2EC
.space 0x4
gUnknown_203B2F0: @ 203B2F0
.space 0x4
gUnknown_203B2F4: @ 203B2F4
.space 0x4
gUnknown_203B2F8: @ 203B2F8
.space 0x4
gUnknown_203B2FC: @ 203B2FC
.space 0x4
gUnknown_203B300: @ 203B300
.space 0x4
gUnknown_203B304: @ 203B304
.space 0x4
gUnknown_203B308: @ 203B308
.space 0x4
gUnknown_203B30C: @ 203B30C
.space 0x4
gUnknown_203B310: @ 203B310
.space 0x4
gUnknown_203B314: @ 203B314
.space 0x4
gUnknown_203B318: @ 203B318
.space 0x4
gUnknown_203B31C: @ 203B31C
.space 0x4
gUnknown_203B320: @ 203B320
.space 0x4
gUnknown_203B324: @ 203B324
.space 0x4
gUnknown_203B328: @ 203B328
.space 0x4
gUnknown_203B32C: @ 203B32C
.space 0x4
gUnknown_203B330: @ 203B330
.space 0x4
gUnknown_203B334: @ 203B334
.space 0x4
gUnknown_203B338: @ 203B338
.space 0x4
gUnknown_203B33C: @ 203B33C
.space 0x4
gUnknown_203B340: @ 203B340
.space 0x4
gUnknown_203B344: @ 203B344
.space 0x4
gUnknown_203B348: @ 203B348
.space 0x4
gUnknown_203B34C: @ 203B34C
.space 0x4
gUnknown_203B350: @ 203B350
.space 0x4
gUnknown_203B354: @ 203B354
.space 0x4
gUnknown_203B358: @ 203B358
.space 0x4
gUnknown_203B35C: @ 203B35C
.space 0x4
gUnknown_203B360: @ 203B360
.space 0x4
gUnknown_203B364: @ 203B364
.space 0x4
gUnknown_203B368: @ 203B368
.space 0x4
gUnknown_203B36C: @ 203B36C
.space 0x4
gUnknown_203B370: @ 203B370
.space 0x4
gUnknown_203B374: @ 203B374
.space 0x4
gUnknown_203B378: @ 203B378
.space 0x10
gUnknown_203B388: @ 203B388
.space 0x30
gUnknown_203B3B8: @ 203B3B8
.space 0x30
gUnknown_203B3E8: @ 203B3E8
.space 0x4
gUnknown_203B3EC: @ 203B3EC
.space 0x4
gUnknown_203B3F0: @ 203B3F0
.space 0x4
gUnknown_203B3F4: @ 203B3F4
.space 0x4
gUnknown_203B3F8: @ 203B3F8
.space 0x4
gUnknown_203B3FC: @ 203B3FC
.space 0x4
gUnknown_203B400: @ 203B400
.space 0x4
gUnknown_203B404: @ 203B404
.space 0x4
gUnknown_203B408: @ 203B408
.space 0x4
gUnknown_203B40C: @ 203B40C
.space 0x1
gUnknown_203B40D: @ 203B40D
.space 0x3
gUnknown_203B410: @ 203B410
.space 0x4
gUnknown_203B414: @ 203B414
.space 0x4
gUnknown_203B418: @ 203B418
.space 0x4
gUnknown_203B41C: @ 203B41C
.space 0x4
gUnknown_203B420: @ 203B420
.space 0x8
gUnknown_203B428: @ 203B428
.space 0x8
gUnknown_203B430: @ 203B430
.space 0x4
gUnknown_203B434: @ 203B434
.space 0x4
gUnknown_203B438: @ 203B438
.space 0x4
gUnknown_203B43C: @ 203B43C
.space 0x4
gUnknown_203B440: @ 203B440
.space 0x4
gUnknown_203B444: @ 203B444
.space 0xC
gUnknown_203B450: @ 203B450
.space 0x4
gUnknown_203B454: @ 203B454
.space 0x4
gUnknown_203B458: @ 203B458
.space 0x4
gUnknown_203B45C: @ 203B45C
.space 0x4
gUnknown_203B460: @ 203B460
.space 0x4
gUnknown_203B464: @ 203B464
.space 0x4
gUnknown_203B468: @ 203B468
.space 0x4
gUnknown_203B46C: @ 203B46C
.space 0x4
gUnknown_203B470: @ 203B470
.space 0x4
gUnknown_203B474: @ 203B474
.space 0x8
gUnknown_203B47C: @ 203B47C
.space 0x4
gUnknown_203B480: @ 203B480
.space 0x4
gUnknown_203B484: @ 203B484
.space 0x4
gUnknown_203B488: @ 203B488
.space 0x4
gUnknown_203B48C: @ 203B48C
.space 0x4
gUnknown_203B490: @ 203B490
.space 0x4
gUnknown_203B494: @ 203B494
.space 0x4
gUnknown_203B498: @ 203B498
.space 0x4
gUnknown_203B49C: @ 203B49C
.space 0x1
gUnknown_203B49D: @ 203B49D
.space 0x3
gUnknown_203B4A0: @ 203B4A0
.space 0xC
gUnknown_203B4AC: @ 203B4AC
.space 0x4
gUnknown_203B4B0: @ 203B4B0
.space 0x4
gUnknown_203B4B4: @ 203B4B4
.space 0x4
gUnknown_203B4B8: @ 203B4B8
.space 0x2F0
gUnknown_203B7A8: @ 203B7A8
.space 0x4
gUnknown_203B7AC: @ 203B7AC
.space 0x14
gUnknown_203B7C0: @ 203B7C0
.space 0x8
gUnknown_203B7C8: @ 203B7C8
.space 0x400
gUnknown_203BBC8: @ 203BBC8
.space 0x4
gUnknown_203BBCC: @ 203BBCC
.space 0x4
gUnknown_203BBD0: @ 203BBD0
.space 0x4
gUnknown_203BBD4: @ 203BBD4
.space 0x4
gUnknown_203BBD8: @ 203BBD8
.space 0x4
gUnknown_203BBDC: @ 203BBDC
.space 0x28
gUnknown_203BC04: @ 203BC04

77
sym_iwram.txt Normal file
View File

@ -0,0 +1,77 @@
SoundMainRAM_Buffer: @ 3000000
.space 0x400
gUnknown_3000400: @ 3000400
.space 0x800
gUnknown_3000C00: @ 3000C00
.space 0x294
gUnknown_3000E94: @ 3000E94
.space 0x144
gUnknown_3000FD8: @ 3000FD8
.space 0x10
gUnknown_3000FE8: @ 3000FE8
.space 0x30
gUnknown_3001018: @ 3001018
.space 0x180
gUnknown_3001198: @ 3001198
.space 0x9C0
alt_3001B58:
unk_code_ram: @ 3001B58
gUnknown_3001B58: @ 3001B58
.space 0x2
gUnknown_3001B5A: @ 3001B5A
.space 0x2
gUnknown_3001B5C: @ 3001B5C
.space 0x4
gUnknown_3001B60: @ 3001B60
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gUnknown_3001B64: @ 3001B64
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gUnknown_3001B68: @ 3001B68
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gUnknown_3001B6C: @ 3001B6C
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gUnknown_3001B70: @ 3001B70
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gUnknown_3001B74: @ 3001B74
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gUnknown_3001B78: @ 3001B78
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gUnknown_3001B7C: @ 3001B7C
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gUnknown_3001B80: @ 3001B80
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gUnknown_3001B84: @ 3001B84
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gUnknown_3001B88: @ 3001B88
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gUnknown_3001B8C: @ 3001B8C
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gUnknown_3001B90: @ 3001B90
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gUnknown_3004000: @ 3004000