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cleanup MI_dma_card

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red031000 2024-10-01 14:44:09 +01:00
parent d6e4cdc9fb
commit 57f95da687
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11 changed files with 1127 additions and 1208 deletions
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14
arm7/lib/include/MI_dma.h
View File

@ -1,10 +1,18 @@
#ifndef POKEDIAMOND_ARM7_MI_DMA_H
#define POKEDIAMOND_ARM7_MI_DMA_H
#ifndef POKEDIAMOND_MI_DMA_H
#define POKEDIAMOND_MI_DMA_H
#include "nitro/MI_dma_shared.h"
#include "nitro/types.h"
#include "registers.h"
void MI_StopDma(u32 channel);
void MI_WaitDma(u32 channel);
#endif
#define MIi_WAIT_BEFOREDMA(dmaCntp, dmaNo) \
do { \
dmaCntp = &((vu32 *)REG_DMA0SAD_ADDR)[dmaNo * 3 + 2]; \
while (*dmaCntp & REG_MI_DMA0CNT_E_MASK) {} \
} while (0)
#endif // POKEDIAMOND_MI_DMA_H

19
arm7/lib/src/MI_dma.c
View File

@ -1,13 +1,16 @@
#include "MI_dma.h"
#include "OS_system.h"
#include "code32.h"
void MI_WaitDma(u32 channel) {
OSIntrMode mode = OS_DisableInterrupts();
vu32 * addr = (vu32 *)(REG_ADDR_DMA0SAD + (channel * 3 + 2) * 4);
while(addr[0] & 0x80000000) ;
vu32 *addr;
MIi_WAIT_BEFOREDMA(addr, channel);
if (channel == 0) {
addr = (vu32 *)(REG_ADDR_DMA0SAD + channel * 12);
addr = (vu32 *)(REG_DMA0SAD_ADDR + channel * 12);
addr[0] = 0;
addr[1] = 0;
addr[2] = 0x81400001;
@ -17,7 +20,7 @@ void MI_WaitDma(u32 channel) {
void MI_StopDma(u32 channel) {
OSIntrMode mode = OS_DisableInterrupts();
vu16 * addr = (vu16 *)(REG_ADDR_DMA0SAD + (channel * 6 + 5) * 2);
vu16 *addr = (vu16 *)(REG_DMA0SAD_ADDR + (channel * 6 + 5) * 2);
addr[0] &= ~(DMA_START_MASK | DMA_REPEAT);
addr[0] &= ~DMA_ENABLE;
{
@ -27,10 +30,10 @@ void MI_StopDma(u32 channel) {
s32 dummy = addr[0];
}
if (channel == 0) {
vu32 * addr32 = (vu32 *)(REG_ADDR_DMA0SAD + channel * 12);
addr32[0] = 0;
addr32[1] = 0;
addr32[2] = 0x81400001;
vu32 *addr32 = (vu32 *)(REG_DMA0SAD_ADDR + channel * 12);
addr32[0] = 0;
addr32[1] = 0;
addr32[2] = 0x81400001;
}
mode = OS_RestoreInterrupts(mode);
}

68
arm9/lib/NitroSDK/include/MI_dma.h
View File

@ -1,34 +1,40 @@
#ifndef POKEDIAMOND_ARM9_MI_DMA_H
#define POKEDIAMOND_ARM9_MI_DMA_H
#ifndef POKEDIAMOND_MI_DMA_H
#define POKEDIAMOND_MI_DMA_H
#include "nitro/MI_dma_shared.h"
#include "consts.h"
#include "OS_system.h"
#include "consts.h"
typedef void (*MIDmaCallback)(void *);
#define MI_DMA_MAX_NUM 3
#define MI_DMA_MAX_NUM 3
#define REG_ADDR_DMA0CNT 0x40000b8
#define REG_ADDR_DMA0_CLR_DATA 0x40000e0
#define REG_ADDR_DMA0CNT 0x40000b8
#define REG_ADDR_DMA0_CLR_DATA 0x40000e0
#define MI_CNT_CLEAR32(size) (0x85000000 | ((size)/4))
#define MI_CNT_CLEAR32_IF(size) (0xc5000000 | ((size)/4))
#define MI_CNT_COPY32(size) (0x84000000 | ((size)/4))
#define MI_CNT_COPY32_IF(size) (0xc4000000 | ((size)/4))
#define MI_CNT_COPY16(size) (0x80000000 | ((size)/2))
#define MI_CNT_CLEAR32(size) (0x85000000 | ((size) / 4))
#define MI_CNT_CLEAR32_IF(size) (0xc5000000 | ((size) / 4))
#define MI_CNT_COPY32(size) (0x84000000 | ((size) / 4))
#define MI_CNT_COPY32_IF(size) (0xc4000000 | ((size) / 4))
#define MI_CNT_COPY16(size) (0x80000000 | ((size) / 2))
#define MI_DMA_SRC_FIX (2UL << 23)
#define MI_DMA_SRC_INC (0UL << 23)
#define MI_DMA_SRC_FIX (2UL << 23)
#define MI_DMA_SRC_INC (0UL << 23)
#define MI_DMA_16BIT_BUS (0UL << 26)
#define MI_DMA_32BIT_BUS (1UL << 26)
#define MI_DMA_16BIT_BUS (0UL << 26)
#define MI_DMA_32BIT_BUS (1UL << 26)
#define MIi_DMA_TIMING_ANY (u32)(~0)
#define MI_DMA_TIMING_H_BLANK (2UL << 27)
#define MIi_DMA_TIMING_ANY (u32)(~0)
#define MI_DMA_TIMING_H_BLANK (2UL << 27)
typedef union
{
#define MIi_WAIT_BEFOREDMA(dmaCntp, dmaNo) \
do { \
dmaCntp = &((vu32 *)REG_DMA0SAD_ADDR)[dmaNo * 3 + 2]; \
while (*dmaCntp & REG_MI_DMA0CNT_E_MASK) {} \
} while (0)
typedef union {
u32 b32;
u16 b16;
} MIiDmaClearSrc;
@ -47,34 +53,30 @@ void MIi_DmaSetParams_wait(u32 dmaNo, u32 src, u32 dest, u32 ctrl);
void MIi_DmaSetParams_noInt(u32 dmaNo, u32 src, u32 dest, u32 ctrl);
void MIi_DmaSetParams_wait_noInt(u32 dmaNo, u32 src, u32 dest, u32 ctrl);
static inline void MIi_DmaSetParams_wait_src32(u32 dmaNo, u32 data, u32 dest, u32 ctrl)
{
static inline void MIi_DmaSetParams_wait_src32(u32 dmaNo, u32 data, u32 dest, u32 ctrl) {
OSIntrMode lastIntrMode = OS_DisableInterrupts();
MIiDmaClearSrc *scrp = (MIiDmaClearSrc *) ((u32)REG_ADDR_DMA0_CLR_DATA + dmaNo * 4);
scrp->b32 = data;
MIiDmaClearSrc *scrp = (MIiDmaClearSrc *)((u32)REG_ADDR_DMA0_CLR_DATA + dmaNo * 4);
scrp->b32 = data;
MIi_DmaSetParams_wait_noInt(dmaNo, (u32)scrp, dest, ctrl);
(void)OS_RestoreInterrupts(lastIntrMode);
}
static inline void MIi_DmaSetParams_src32(u32 dmaNo, u32 data, u32 dest, u32 ctrl)
{
static inline void MIi_DmaSetParams_src32(u32 dmaNo, u32 data, u32 dest, u32 ctrl) {
OSIntrMode lastIntrMode = OS_DisableInterrupts();
MIiDmaClearSrc *srcp = (MIiDmaClearSrc *) ((u32)REG_ADDR_DMA0_CLR_DATA + dmaNo * 4);
srcp->b32 = data;
MIiDmaClearSrc *srcp = (MIiDmaClearSrc *)((u32)REG_ADDR_DMA0_CLR_DATA + dmaNo * 4);
srcp->b32 = data;
MIi_DmaSetParams_noInt(dmaNo, (u32)srcp, dest, ctrl);
(void)OS_RestoreInterrupts(lastIntrMode);
}
static inline void MIi_CallCallback(MIDmaCallback callback, void *arg)
{
if (callback)
{
(callback) (arg);
static inline void MIi_CallCallback(MIDmaCallback callback, void *arg) {
if (callback) {
(callback)(arg);
}
}
#endif //POKEDIAMOND_ARM9_MI_DMA_H
#endif // POKEDIAMOND_MI_DMA_H

2
arm9/lib/NitroSDK/include/MI_dma_card.h
View File

@ -5,4 +5,4 @@
void MIi_CardDmaCopy32(u32 dmaNo, const void *src, void *dest, u32 size);
#endif //POKEDIAMOND_MI_DMA_CARD_H
#endif // POKEDIAMOND_MI_DMA_CARD_H

1893
arm9/lib/NitroSDK/include/registers.h
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File diff suppressed because it is too large Load Diff

220
arm9/lib/NitroSDK/src/MI_dma.c
View File

@ -1,29 +1,28 @@
#include "MI_dma.h"
#include "OS_interrupt.h"
#include "OS_terminate_proc.h"
#include "sections.h"
#include "code32.h"
#include "sections.h"
#pragma section ITCM begin
void MIi_DmaSetParams(u32 dmaNo, u32 src, u32 dest, u32 ctrl)
{
void MIi_DmaSetParams(u32 dmaNo, u32 src, u32 dest, u32 ctrl) {
OSIntrMode lastIntrMode = OS_DisableInterrupts();
vu32 *p = (vu32 *)((u32)REG_ADDR_DMA0SAD + dmaNo * 12);
*p = (vu32)src;
*(p + 1) = (vu32)dest;
*(p + 2) = (vu32)ctrl;
vu32 *p = (vu32 *)((u32)REG_DMA0SAD_ADDR + dmaNo * 12);
*p = (vu32)src;
*(p + 1) = (vu32)dest;
*(p + 2) = (vu32)ctrl;
(void)OS_RestoreInterrupts(lastIntrMode);
}
void MIi_DmaSetParams_wait(u32 dmaNo, u32 src, u32 dest, u32 ctrl)
{
void MIi_DmaSetParams_wait(u32 dmaNo, u32 src, u32 dest, u32 ctrl) {
OSIntrMode enabled = OS_DisableInterrupts();
vu32 *p = (vu32 *)((u32)REG_ADDR_DMA0SAD + dmaNo * 12);
*p = (vu32)src;
*(p + 1) = (vu32)dest;
*(p + 2) = (vu32)ctrl;
vu32 *p = (vu32 *)((u32)REG_DMA0SAD_ADDR + dmaNo * 12);
*p = (vu32)src;
*(p + 1) = (vu32)dest;
*(p + 2) = (vu32)ctrl;
//delay cycles
// delay cycles
{
u32 delay = reg_MI_DMA0SAD;
}
@ -31,9 +30,8 @@ void MIi_DmaSetParams_wait(u32 dmaNo, u32 src, u32 dest, u32 ctrl)
u32 delay = reg_MI_DMA0SAD;
}
if (!dmaNo)
{
*p = (vu32)0;
if (!dmaNo) {
*p = (vu32)0;
*(p + 1) = (vu32)0;
*(p + 2) = (vu32)0x81400001;
}
@ -41,22 +39,20 @@ void MIi_DmaSetParams_wait(u32 dmaNo, u32 src, u32 dest, u32 ctrl)
(void)OS_RestoreInterrupts(enabled);
}
void MIi_DmaSetParams_noInt(u32 dmaNo, u32 src, u32 dest, u32 ctrl)
{
vu32 *p = (vu32 *)((u32)REG_ADDR_DMA0SAD + dmaNo * 12);
*p = (vu32)src;
void MIi_DmaSetParams_noInt(u32 dmaNo, u32 src, u32 dest, u32 ctrl) {
vu32 *p = (vu32 *)((u32)REG_DMA0SAD_ADDR + dmaNo * 12);
*p = (vu32)src;
*(p + 1) = (vu32)dest;
*(p + 2) = (vu32)ctrl;
}
void MIi_DmaSetParams_wait_noInt(u32 dmaNo, u32 src, u32 dest, u32 ctrl)
{
vu32 *p = (vu32 *)((u32)REG_ADDR_DMA0SAD + dmaNo * 12);
*p = (vu32)src;
void MIi_DmaSetParams_wait_noInt(u32 dmaNo, u32 src, u32 dest, u32 ctrl) {
vu32 *p = (vu32 *)((u32)REG_DMA0SAD_ADDR + dmaNo * 12);
*p = (vu32)src;
*(p + 1) = (vu32)dest;
*(p + 2) = (vu32)ctrl;
//delay cycles
// delay cycles
{
u32 delay = reg_MI_DMA0SAD;
}
@ -64,14 +60,13 @@ void MIi_DmaSetParams_wait_noInt(u32 dmaNo, u32 src, u32 dest, u32 ctrl)
u32 delay = reg_MI_DMA0SAD;
}
if (!dmaNo)
{
*p = (vu32)0;
if (!dmaNo) {
*p = (vu32)0;
*(p + 1) = (vu32)0;
*(p + 2) = (vu32)0x81400001;
}
//delay cycles
// delay cycles
{
u32 delay = reg_MI_DMA0SAD;
}
@ -81,134 +76,96 @@ void MIi_DmaSetParams_wait_noInt(u32 dmaNo, u32 src, u32 dest, u32 ctrl)
}
#pragma section ITCM end
void MI_DmaFill32(u32 dmaNo, void *dest, u32 data, u32 size)
{
void MI_DmaFill32(u32 dmaNo, void *dest, u32 data, u32 size) {
vu32 *dmaCntp;
if (!size)
{
if (!size) {
return;
}
do
{
dmaCntp = &((vu32 *)REG_ADDR_DMA0SAD)[dmaNo * 3 + 2];
while (*dmaCntp & 0x80000000) {}
} while(0);
MIi_WAIT_BEFOREDMA(dmaCntp, dmaNo);
MIi_DmaSetParams_wait_src32(dmaNo, data, (u32)dest, MI_CNT_CLEAR32(size));
do
{
do {
while (*dmaCntp & 0x80000000) {}
} while(0);
} while (0);
}
void MI_DmaCopy32(u32 dmaNo, const void *src, void *dest, u32 size)
{
void MI_DmaCopy32(u32 dmaNo, const void *src, void *dest, u32 size) {
vu32 *dmaCntp;
MIi_CheckDma0SourceAddress(dmaNo, (u32)src, size, DMA_SRC_INC);
if (!size)
{
if (!size) {
return;
}
do
{
dmaCntp = &((vu32 *)REG_ADDR_DMA0SAD)[dmaNo * 3 + 2];
while (*dmaCntp & 0x80000000) {}
} while(0);
MIi_WAIT_BEFOREDMA(dmaCntp, dmaNo);
MIi_DmaSetParams_wait(dmaNo, (u32)src, (u32)dest, MI_CNT_COPY32(size));
do
{
do {
while (*dmaCntp & 0x80000000) {}
} while(0);
} while (0);
}
void MI_DmaCopy16(u32 dmaNo, const void *src, void *dest, u32 size)
{
void MI_DmaCopy16(u32 dmaNo, const void *src, void *dest, u32 size) {
vu32 *dmaCntp;
if (!size)
{
if (!size) {
return;
}
MIi_CheckDma0SourceAddress(dmaNo, (u32)src, size, DMA_SRC_INC);
do
{
dmaCntp = &((vu32 *)REG_ADDR_DMA0SAD)[dmaNo * 3 + 2];
while (*dmaCntp & 0x80000000) {}
} while(0);
MIi_WAIT_BEFOREDMA(dmaCntp, dmaNo);
MIi_DmaSetParams_wait(dmaNo, (u32)src, (u32)dest, MI_CNT_COPY16(size));
do
{
do {
while (*dmaCntp & 0x80000000) {}
} while(0);
} while (0);
}
void MI_DmaFill32Async(u32 dmaNo, void *dest, u32 data, u32 size, MIDmaCallback callback, void *arg)
{
if (!size)
{
void MI_DmaFill32Async(u32 dmaNo, void *dest, u32 data, u32 size, MIDmaCallback callback, void *arg) {
if (!size) {
MIi_CallCallback(callback, arg);
}
else
{
} else {
MI_WaitDma(dmaNo);
if (callback)
{
if (callback) {
OSi_EnterDmaCallback(dmaNo, callback, arg);
MIi_DmaSetParams_src32(dmaNo, data, (u32)dest, MI_CNT_CLEAR32_IF(size));
}
else
{
} else {
MIi_DmaSetParams_src32(dmaNo, data, (u32)dest, MI_CNT_CLEAR32(size));
}
}
}
void MI_DmaCopy32Async(u32 dmaNo, const void *src, void *dest, u32 size, MIDmaCallback callback, void *arg)
{
void MI_DmaCopy32Async(u32 dmaNo, const void *src, void *dest, u32 size, MIDmaCallback callback, void *arg) {
MIi_CheckDma0SourceAddress(dmaNo, (u32)src, size, DMA_SRC_INC);
if (!size)
{
if (!size) {
MIi_CallCallback(callback, arg);
}
else
{
} else {
MI_WaitDma(dmaNo);
if (callback)
{
if (callback) {
OSi_EnterDmaCallback(dmaNo, callback, arg);
MIi_DmaSetParams(dmaNo, (u32)src, (u32)dest, MI_CNT_COPY32_IF(size));
}
else
{
} else {
MIi_DmaSetParams(dmaNo, (u32)src, (u32)dest, MI_CNT_COPY32(size));
}
}
}
void MI_WaitDma(u32 dmaNo)
{
void MI_WaitDma(u32 dmaNo) {
OSIntrMode lastIntrMode = OS_DisableInterrupts();
vu32 *dmaCntp = &((vu32 *)REG_ADDR_DMA0SAD)[dmaNo * 3 + 2];
vu32 *dmaCntp;
MIi_WAIT_BEFOREDMA(dmaCntp, dmaNo);
while (*dmaCntp & 0x80000000) {}
if (!dmaNo)
{
vu32 *p = (vu32 *)((u32)REG_ADDR_DMA0SAD + dmaNo * 12);
*p = (vu32)0;
if (!dmaNo) {
vu32 *p = (vu32 *)((u32)REG_DMA0SAD_ADDR + dmaNo * 12);
*p = (vu32)0;
*(p + 1) = (vu32)0;
*(p + 2) = (vu32)0x81400001;
}
@ -216,15 +173,14 @@ void MI_WaitDma(u32 dmaNo)
(void)OS_RestoreInterrupts(lastIntrMode);
}
void MI_StopDma(u32 dmaNo)
{
void MI_StopDma(u32 dmaNo) {
OSIntrMode lastIntrMode = OS_DisableInterrupts();
vu16 *dmaCntp = &((vu16 *)REG_ADDR_DMA0SAD)[dmaNo * 6 + 5];
vu16 *dmaCntp = &((vu16 *)REG_DMA0SAD_ADDR)[dmaNo * 6 + 5];
*dmaCntp &= ~0x3a00;
*dmaCntp &= ~0x8000;
//delay cycles
// delay cycles
{
s32 delay = dmaCntp[0];
}
@ -232,10 +188,9 @@ void MI_StopDma(u32 dmaNo)
s32 delay = dmaCntp[0];
}
if (!dmaNo)
{
vu32 *p = (vu32 *)((u32)REG_ADDR_DMA0SAD + dmaNo * 12);
*p = (vu32)0;
if (!dmaNo) {
vu32 *p = (vu32 *)((u32)REG_DMA0SAD_ADDR + dmaNo * 12);
*p = (vu32)0;
*(p + 1) = (vu32)0;
*(p + 2) = (vu32)0x81400001;
}
@ -243,24 +198,25 @@ void MI_StopDma(u32 dmaNo)
(void)OS_RestoreInterrupts(lastIntrMode);
}
void MIi_CheckAnotherAutoDMA(u32 dmaNo, u32 dmaType)
{
void MIi_CheckAnotherAutoDMA(u32 dmaNo, u32 dmaType) {
u32 dmaCnt;
u32 timing;
for (int i = 0; i < 3; i++)
{
if (i == dmaNo) continue;
for (int i = 0; i < 3; i++) {
if (i == dmaNo) {
continue;
}
dmaCnt = *(REGType32v *)(REG_ADDR_DMA0CNT + i * 12);
if (!(dmaCnt & 0x80000000)) continue;
if (!(dmaCnt & 0x80000000)) {
continue;
}
timing = dmaCnt & 0x38000000;
if (timing == dmaType
|| (timing == 0x8000000 && dmaType == MI_DMA_TIMING_H_BLANK)
|| (timing == MI_DMA_TIMING_H_BLANK && dmaType == 0x8000000))
{
|| (timing == MI_DMA_TIMING_H_BLANK && dmaType == 0x8000000)) {
continue;
}
@ -270,37 +226,31 @@ void MIi_CheckAnotherAutoDMA(u32 dmaNo, u32 dmaType)
|| timing == 0x30000000
|| timing == 0x38000000
|| timing == 0x8000000
|| timing == 0x10000000)
{
|| timing == 0x10000000) {
OS_Terminate();
}
}
}
void MIi_CheckDma0SourceAddress(u32 dmaNo, u32 src, u32 size, u32 dir)
{
if (!dmaNo)
{
void MIi_CheckDma0SourceAddress(u32 dmaNo, u32 src, u32 size, u32 dir) {
if (!dmaNo) {
u32 addStart = src & 0xff000000;
u32 addEnd;
switch (dir)
{
case 0: //dma_src_inc
addEnd = src + size;
break;
case 0x800000: //dma_src_dec
addEnd = src - size;
break;
default:
addEnd = src;
break;
switch (dir) {
case 0: // dma_src_inc
addEnd = src + size;
break;
case 0x800000: // dma_src_dec
addEnd = src - size;
break;
default:
addEnd = src;
break;
}
addEnd &= 0xff000000;
if (addStart == 0x04000000 || addStart >= 0x08000000 ||
addEnd == 0x04000000 || addEnd >= 0x08000000)
{
if (addStart == 0x04000000 || addStart >= 0x08000000 || addEnd == 0x04000000 || addEnd >= 0x08000000) {
OS_Terminate();
}
}

15
arm9/lib/NitroSDK/src/MI_dma_card.c
View File

@ -1,24 +1,19 @@
#include "MI_dma_card.h"
#include "MI_dma.h"
#include "code32.h"
void MIi_CardDmaCopy32(u32 dmaNo, const void *src, void *dest, u32 size)
{
void MIi_CardDmaCopy32(u32 dmaNo, const void *src, void *dest, u32 size) {
MIi_CheckAnotherAutoDMA(dmaNo, MIi_DMA_TIMING_ANY);
MIi_CheckDma0SourceAddress(dmaNo, (u32)src, size, MI_DMA_SRC_FIX);
if (size == 0)
{
if (size == 0) {
return;
}
vu32 *dmaCntp;
MIi_WAIT_BEFOREDMA(dmaCntp, dmaNo);
do
{
dmaCntp = &((vu32 *)REG_ADDR_DMA0SAD)[dmaNo * 3 + 2];
while (*dmaCntp & 0x80000000) {}
} while(0);
// TODO: control params, should be MI_CNT_CARDRECV32(4) | MI_DMA_CONTINUOUS_ON
MIi_DmaSetParams(dmaNo, (u32)src, (u32)dest, (u32)(0xaf000001));
}

72
arm9/lib/NitroSDK/src/MI_dma_gxcommand.c
View File

@ -1,8 +1,9 @@
#include "MI_dma_gxcommand.h"
#include "OS_interrupt.h"
#include "OS_reset.h"
#include "sections.h"
#include "code32.h"
#include "sections.h"
static MIiGXDmaParams MIi_GXDmaParams = { FALSE };
@ -11,43 +12,33 @@ static void MIi_DMACallback(void *arg);
static void MIi_DMAFastCallback(void *arg);
#pragma section ITCM begin
void MI_SendGXCommand(u32 dmaNo, const void *src, u32 commandLength)
{
void MI_SendGXCommand(u32 dmaNo, const void *src, u32 commandLength) {
vu32 *dmaCntp;
u32 leftLength = commandLength;
u32 currentSrc = (u32)src;
if (!leftLength)
{
if (!leftLength) {
return;
}
MIi_CheckDma0SourceAddress(dmaNo, (u32)src, commandLength, DMA_SRC_INC);
do
{
dmaCntp = &((vu32 *)REG_ADDR_DMA0SAD)[dmaNo * 3 + 2];
while (*dmaCntp & 0x80000000) {}
} while(0);
MIi_WAIT_BEFOREDMA(dmaCntp, dmaNo);
while (leftLength > 0)
{
while (leftLength > 0) {
u32 length = (leftLength > MIi_GX_LENGTH_ONCE) ? MIi_GX_LENGTH_ONCE : leftLength;
MIi_DmaSetParams(dmaNo, currentSrc, (u32)REG_GXFIFO_ADDR, MI_CNT_SEND32(length));
leftLength -= length;
currentSrc += length;
}
do
{
do {
while (*dmaCntp & 0x80000000) {}
} while(0);
} while (0);
}
#pragma section ITCM end
void MI_SendGXCommandAsync(u32 dmaNo, const void *src, u32 commandLength, MIDmaCallback callback, void *arg)
{
if (!commandLength)
{
void MI_SendGXCommandAsync(u32 dmaNo, const void *src, u32 commandLength, MIDmaCallback callback, void *arg) {
if (!commandLength) {
MIi_CallCallback(callback, arg);
return;
}
@ -56,12 +47,12 @@ void MI_SendGXCommandAsync(u32 dmaNo, const void *src, u32 commandLength, MIDmaC
while (!(G3X_GetCommandFifoStatus() & GX_FIFOSTAT_UNDERHALF)) {}
MIi_GXDmaParams.isBusy = TRUE;
MIi_GXDmaParams.dmaNo = dmaNo;
MIi_GXDmaParams.src = (u32)src;
MIi_GXDmaParams.length = commandLength;
MIi_GXDmaParams.isBusy = TRUE;
MIi_GXDmaParams.dmaNo = dmaNo;
MIi_GXDmaParams.src = (u32)src;
MIi_GXDmaParams.length = commandLength;
MIi_GXDmaParams.callback = callback;
MIi_GXDmaParams.arg = arg;
MIi_GXDmaParams.arg = arg;
MIi_CheckDma0SourceAddress(dmaNo, (u32)src, commandLength, DMA_SRC_INC);
@ -82,34 +73,28 @@ void MI_SendGXCommandAsync(u32 dmaNo, const void *src, u32 commandLength, MIDmaC
}
}
static void MIi_FIFOCallback(void)
{
if (!MIi_GXDmaParams.length)
{
static void MIi_FIFOCallback(void) {
if (!MIi_GXDmaParams.length) {
return;
}
u32 length = (MIi_GXDmaParams.length >= MIi_GX_LENGTH_ONCE) ? MIi_GX_LENGTH_ONCE : MIi_GXDmaParams.length;
u32 src = MIi_GXDmaParams.src;
u32 src = MIi_GXDmaParams.src;
MIi_GXDmaParams.length -= length;
MIi_GXDmaParams.src += length;
if (!MIi_GXDmaParams.length)
{
if (!MIi_GXDmaParams.length) {
OSi_EnterDmaCallback(MIi_GXDmaParams.dmaNo, MIi_DMACallback, NULL);
MIi_DmaSetParams(MIi_GXDmaParams.dmaNo, src, (u32)REG_GXFIFO_ADDR, MI_CNT_SEND32_IF(length));
(void)OS_ResetRequestIrqMask(OS_IE_GXFIFO);
}
else
{
} else {
MIi_DmaSetParams(MIi_GXDmaParams.dmaNo, src, (u32)REG_GXFIFO_ADDR, MI_CNT_SEND32(length));
(void)OS_ResetRequestIrqMask(OS_IE_GXFIFO);
}
}
static void MIi_DMACallback(void *arg)
{
static void MIi_DMACallback(void *arg) {
#pragma unused(arg)
(void)OS_DisableIrqMask(OS_IE_GXFIFO);
@ -121,20 +106,18 @@ static void MIi_DMACallback(void *arg)
MIi_CallCallback(MIi_GXDmaParams.callback, MIi_GXDmaParams.arg);
}
void MI_SendGXCommandAsyncFast(u32 dmaNo, const void *src, u32 commandLength, MIDmaCallback callback, void *arg)
{
if (!commandLength)
{
void MI_SendGXCommandAsyncFast(u32 dmaNo, const void *src, u32 commandLength, MIDmaCallback callback, void *arg) {
if (!commandLength) {
MIi_CallCallback(callback, arg);
return;
}
while (MIi_GXDmaParams.isBusy) {}
MIi_GXDmaParams.isBusy = TRUE;
MIi_GXDmaParams.dmaNo = dmaNo;
MIi_GXDmaParams.isBusy = TRUE;
MIi_GXDmaParams.dmaNo = dmaNo;
MIi_GXDmaParams.callback = callback;
MIi_GXDmaParams.arg = arg;
MIi_GXDmaParams.arg = arg;
MIi_CheckAnotherAutoDMA(dmaNo, 0x38000000);
@ -146,8 +129,7 @@ void MI_SendGXCommandAsyncFast(u32 dmaNo, const void *src, u32 commandLength, MI
MIi_DmaSetParams(dmaNo, (u32)src, (u32)REG_GXFIFO_ADDR, MI_CNT_GXCOPY_IF(commandLength));
}
static void MIi_DMAFastCallback(void *arg)
{
static void MIi_DMAFastCallback(void *arg) {
#pragma unused(arg)
MIi_GXDmaParams.isBusy = FALSE;

2
include/nitro/MI_dma_shared.h
View File

@ -13,7 +13,7 @@
#ifndef GUARD_DMA_SHARED_H
#define GUARD_DMA_SHARED_H
#define REG_ADDR_DMA0SAD 0x040000b0
#define REG_MI_DMA0CNT_E_MASK 0x80000000
#define DMA_DEST_INC 0x0000
#define DMA_DEST_DEC 0x0020

28
include/nitro/registers_shared.h
View File

@ -10,19 +10,21 @@
#include "nitro/types.h"
#define reg_OS_TM0CNT_L (*(REGType16v *)0x4000100)
#define reg_OS_TM0CNT_H (*(REGType16v *)0x4000102)
#define reg_OS_TM1CNT_L (*(REGType16v *)0x4000104)
#define reg_OS_TM1CNT_H (*(REGType16v *)0x4000106)
#define reg_OS_TM2CNT_L (*(REGType16v *)0x4000108)
#define reg_OS_TM2CNT_H (*(REGType16v *)0x400010a)
#define reg_OS_TM3CNT_L (*(REGType16v *)0x400010c)
#define reg_OS_TM3CNT_H (*(REGType16v *)0x400010e)
#define reg_OS_TM0CNT_L (*(REGType16v *)0x4000100)
#define reg_OS_TM0CNT_H (*(REGType16v *)0x4000102)
#define reg_OS_TM1CNT_L (*(REGType16v *)0x4000104)
#define reg_OS_TM1CNT_H (*(REGType16v *)0x4000106)
#define reg_OS_TM2CNT_L (*(REGType16v *)0x4000108)
#define reg_OS_TM2CNT_H (*(REGType16v *)0x400010a)
#define reg_OS_TM3CNT_L (*(REGType16v *)0x400010c)
#define reg_OS_TM3CNT_H (*(REGType16v *)0x400010e)
#define reg_OS_IME (*(REGType16v *)0x4000208)
#define reg_OS_IE (*(REGType32v *)0x4000210)
#define reg_OS_IF (*(REGType32v *)0x4000214)
#define reg_OS_IME (*(REGType16v *)0x4000208)
#define reg_OS_IE (*(REGType32v *)0x4000210)
#define reg_OS_IF (*(REGType32v *)0x4000214)
#define REG_OS_TM0CNT_H_PS_SHIFT 0
#define REG_DMA0SAD_ADDR 0x40000b0
#endif //POKEDIAMOND_REGISTERS_SHARED_H
#define REG_OS_TM0CNT_H_PS_SHIFT 0
#endif // POKEDIAMOND_REGISTERS_SHARED_H

2
m2ctx.sh
View File

@ -4,7 +4,7 @@ OUT_FILE=ctx.c
GCC=gcc
FLAGS="-E -P -dD -undef"
INCLUDES="-Iinclude -Iinclude/constants -Iinclude/nitro -Iinclude-mw -Ifiles -Iarm9/lib/NitroSDK/include -Iarm9/lib/MSL_C/include -Iarm9/lib/libnns/include -Iarm9/overlays/21/include -Iarm9/overlays/52/include -Iarm9/overlays/59/include -include global.h"
INCLUDES="-Iinclude -Iinclude/constants -Iinclude/nitro -Iinclude-mw -Ifiles -Iarm9/lib/NitroSDK/include -Iarm9/lib/MSL_C/include -Iarm9/lib/libnns/include -Iarm9/overlays/21/include -Iarm9/overlays/52/include -Iarm9/overlays/59/include"
DEFINES="-DDIAMOND"