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NitroSDK: Split ARM9 fx.a

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This commit is contained in:
PikalaxALT 2021-09-18 15:06:49 -04:00
parent b912557e5a
commit 62894baf5d
22 changed files with 3140 additions and 3001 deletions
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2
common.mk
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@ -50,7 +50,7 @@ NATIVE_TOOLS := \
TOOLDIRS := $(foreach tool,$(NATIVE_TOOLS),$(dir $(tool)))
# Directories
LIB_SUBDIRS := cw dwc nitro nnsys
LIB_SUBDIRS := cw NitroSDK NitroSystem NitroDWC NitroWiFi libCPS libVCT
SRC_SUBDIR := src
ASM_SUBDIR := asm
LIB_SRC_SUBDIR := lib/src $(LIB_SUBDIRS:%=lib/%/src)

2
global.inc
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@ -29492,3 +29492,5 @@
.public sub_0205CB14
.public sub_0205CB2C
.public sub_0205F47C
.public MI_Copy48B
.public MTX_ScaleApply33

0
lib/dwc/asm/overlay_00_arm.s → lib/NitroDWC/asm/overlay_00_arm.s
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0
lib/dwc/asm/overlay_13_arm_1.s → lib/NitroDWC/asm/overlay_13_arm_1.s
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0
lib/dwc/asm/overlay_13_arm_2.s → lib/NitroDWC/asm/overlay_13_arm_2.s
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0
lib/dwc/asm/overlay_38_arm.s → lib/NitroDWC/asm/overlay_38_arm.s
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0
lib/dwc/asm/overlay_39_arm.s → lib/NitroDWC/asm/overlay_39_arm.s
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0
lib/dwc/asm/overlay_45_arm.s → lib/NitroDWC/asm/overlay_45_arm.s
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0
lib/dwc/asm/overlay_74_arm.s → lib/NitroDWC/asm/overlay_74_arm.s
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0
lib/dwc/asm/overlay_93_arm.s → lib/NitroDWC/asm/overlay_93_arm.s
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29
lib/NitroSDK/asm/fx.s Normal file
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@ -0,0 +1,29 @@
.include "asm/macros.inc"
.include "global.inc"
.text
arm_func_start FX_Init
FX_Init: ; 0x020CD784
bx lr
arm_func_end FX_Init
arm_func_start FX_Modf
FX_Modf: ; 0x020CD788
cmp r0, #0
ldr r2, _020CD7C0 ; =0x7FFFF000
blt _020CD7A4
and r3, r0, r2
str r3, [r1]
and r0, r0, r2, lsr #19
bx lr
_020CD7A4:
rsb ip, r0, #0
and r0, ip, r2
rsb r3, r0, #0
and r0, ip, r2, lsr #19
str r3, [r1]
rsb r0, r0, #0
bx lr
.align 2, 0
_020CD7C0: .word 0x7FFFF000
arm_func_end FX_Modf

262
lib/NitroSDK/asm/fx_atan.s Normal file
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@ -0,0 +1,262 @@
.include "asm/macros.inc"
.include "global.inc"
.text
arm_func_start FX_Atan2Idx
FX_Atan2Idx: ; 0x020CD5DC
stmdb sp!, {r4, lr}
cmp r0, #0
ble _020CD670
cmp r1, #0
ble _020CD628
cmp r1, r0
ble _020CD608
mov r2, r0
mov r4, #0
mov r0, #1
b _020CD720
_020CD608:
bge _020CD620
mov r2, r1
mov r1, r0
mov r4, #0x4000
mov r0, #0
b _020CD720
_020CD620:
mov r0, #0x2000
ldmia sp!, {r4, pc}
_020CD628:
bge _020CD668
rsb r1, r1, #0
cmp r1, r0
bge _020CD64C
mov r2, r1
mov r1, r0
mov r4, #0x4000
mov r0, #1
b _020CD720
_020CD64C:
ble _020CD660
mov r2, r0
mov r4, #0x8000
mov r0, #0
b _020CD720
_020CD660:
mov r0, #0x6000
ldmia sp!, {r4, pc}
_020CD668:
mov r0, #0x4000
ldmia sp!, {r4, pc}
_020CD670:
bge _020CD710
cmp r1, #0
rsb r0, r0, #0
bge _020CD6C4
rsb r1, r1, #0
cmp r1, r0
ble _020CD6A0
mov r4, #0x8000
mov r2, r0
rsb r4, r4, #0
mov r0, #1
b _020CD720
_020CD6A0:
bge _020CD6BC
mov r4, #0x4000
mov r2, r1
mov r1, r0
rsb r4, r4, #0
mov r0, #0
b _020CD720
_020CD6BC:
mov r0, #0xa000
ldmia sp!, {r4, pc}
_020CD6C4:
cmp r1, #0
ble _020CD708
cmp r1, r0
bge _020CD6EC
mov r4, #0x4000
mov r2, r1
mov r1, r0
rsb r4, r4, #0
mov r0, #1
b _020CD720
_020CD6EC:
ble _020CD700
mov r4, #0
mov r2, r0
mov r0, r4
b _020CD720
_020CD700:
mov r0, #0xe000
ldmia sp!, {r4, pc}
_020CD708:
mov r0, #0xc000
ldmia sp!, {r4, pc}
_020CD710:
cmp r1, #0
movge r0, #0
movlt r0, #0x8000
ldmia sp!, {r4, pc}
_020CD720:
cmp r1, #0
moveq r0, #0
ldmeqia sp!, {r4, pc}
cmp r0, #0
mov r0, r2
beq _020CD75C
bl FX_Div
mov r1, r0, asr #5
ldr r0, _020CD780 ; =FX_AtanIdxTable_
mov r1, r1, lsl #1
ldrsh r0, [r0, r1]
add r0, r4, r0
mov r0, r0, lsl #0x10
mov r0, r0, lsr #0x10
ldmia sp!, {r4, pc}
_020CD75C:
bl FX_Div
mov r1, r0, asr #5
ldr r0, _020CD780 ; =FX_AtanIdxTable_
mov r1, r1, lsl #1
ldrsh r0, [r0, r1]
sub r0, r4, r0
mov r0, r0, lsl #0x10
mov r0, r0, lsr #0x10
ldmia sp!, {r4, pc}
.align 2, 0
_020CD780: .word FX_AtanIdxTable_
arm_func_end FX_Atan2Idx
.rodata
FX_AtanIdxTable_:
.short 0x0000
.short 0x0051
.short 0x00A3
.short 0x00F4
.short 0x0146
.short 0x0197
.short 0x01E9
.short 0x023A
.short 0x028B
.short 0x02DC
.short 0x032D
.short 0x037E
.short 0x03CF
.short 0x0420
.short 0x0470
.short 0x04C1
.short 0x0511
.short 0x0561
.short 0x05B1
.short 0x0601
.short 0x0651
.short 0x06A0
.short 0x06EF
.short 0x073E
.short 0x078D
.short 0x07DC
.short 0x082A
.short 0x0878
.short 0x08C6
.short 0x0914
.short 0x0961
.short 0x09AE
.short 0x09FB
.short 0x0A48
.short 0x0A94
.short 0x0AE0
.short 0x0B2C
.short 0x0B77
.short 0x0BC2
.short 0x0C0D
.short 0x0C57
.short 0x0CA1
.short 0x0CEB
.short 0x0D34
.short 0x0D7D
.short 0x0DC6
.short 0x0E0F
.short 0x0E56
.short 0x0E9E
.short 0x0EE5
.short 0x0F2C
.short 0x0F73
.short 0x0FB9
.short 0x0FFF
.short 0x1044
.short 0x1089
.short 0x10CE
.short 0x1112
.short 0x1156
.short 0x1199
.short 0x11DC
.short 0x121F
.short 0x1261
.short 0x12A3
.short 0x12E4
.short 0x1325
.short 0x1366
.short 0x13A6
.short 0x13E6
.short 0x1425
.short 0x1464
.short 0x14A2
.short 0x14E0
.short 0x151E
.short 0x155B
.short 0x1598
.short 0x15D5
.short 0x1611
.short 0x164C
.short 0x1688
.short 0x16C2
.short 0x16FD
.short 0x1737
.short 0x1770
.short 0x17AA
.short 0x17E2
.short 0x181B
.short 0x1853
.short 0x188A
.short 0x18C1
.short 0x18F8
.short 0x192E
.short 0x1964
.short 0x199A
.short 0x19CF
.short 0x1A04
.short 0x1A38
.short 0x1A6C
.short 0x1A9F
.short 0x1AD3
.short 0x1B05
.short 0x1B38
.short 0x1B6A
.short 0x1B9C
.short 0x1BCD
.short 0x1BFE
.short 0x1C2E
.short 0x1C5E
.short 0x1C8E
.short 0x1CBE
.short 0x1CED
.short 0x1D1B
.short 0x1D4A
.short 0x1D78
.short 0x1DA5
.short 0x1DD3
.short 0x1DFF
.short 0x1E2C
.short 0x1E58
.short 0x1E84
.short 0x1EB0
.short 0x1EDB
.short 0x1F06
.short 0x1F30
.short 0x1F5A
.short 0x1F84
.short 0x1FAE
.short 0x1FD7

180
lib/NitroSDK/asm/fx_cp.s Normal file
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@ -0,0 +1,180 @@
.include "asm/macros.inc"
.include "global.inc"
.text
arm_func_start FX_Div
FX_Div: ; 0x020CCBA0
stmdb sp!, {r3, lr}
bl FX_DivAsync
bl FX_GetDivResult
ldmia sp!, {r3, pc}
arm_func_end FX_Div
arm_func_start FX_Inv
FX_Inv: ; 0x020CCBB0
stmdb sp!, {r3, lr}
bl FX_InvAsync
bl FX_GetDivResult
ldmia sp!, {r3, pc}
arm_func_end FX_Inv
arm_func_start FX_InvFx64c
FX_InvFx64c: ; 0x020CCBC0
stmdb sp!, {r3, lr}
bl FX_InvAsync
ldr r1, _020CCBE4 ; =0x04000280
_020CCBCC:
ldrh r0, [r1]
tst r0, #0x8000
bne _020CCBCC
ldr r1, _020CCBE8 ; =0x040002A0
ldmia r1, {r0, r1}
ldmia sp!, {r3, pc}
.align 2, 0
_020CCBE4: .word 0x04000280
_020CCBE8: .word 0x040002A0
arm_func_end FX_InvFx64c
arm_func_start FX_Sqrt
FX_Sqrt: ; 0x020CCBEC
stmdb sp!, {r3, lr}
cmp r0, #0
movle r0, #0
ldmleia sp!, {r3, pc}
ldr r2, _020CCC1C ; =0x040002B0
mov r1, #1
strh r1, [r2]
mov r1, #0
str r1, [r2, #8]
str r0, [r2, #0xc]
bl FX_GetSqrtResult
ldmia sp!, {r3, pc}
.align 2, 0
_020CCC1C: .word 0x040002B0
arm_func_end FX_Sqrt
arm_func_start FX_GetDivResultFx64c
FX_GetDivResultFx64c: ; 0x020CCC20
ldr r1, _020CCC3C ; =0x04000280
_020CCC24:
ldrh r0, [r1]
tst r0, #0x8000
bne _020CCC24
ldr r1, _020CCC40 ; =0x040002A0
ldmia r1, {r0, r1}
bx lr
.align 2, 0
_020CCC3C: .word 0x04000280
_020CCC40: .word 0x040002A0
arm_func_end FX_GetDivResultFx64c
arm_func_start FX_GetDivResult
FX_GetDivResult: ; 0x020CCC44
ldr r1, _020CCC74 ; =0x04000280
_020CCC48:
ldrh r0, [r1]
tst r0, #0x8000
bne _020CCC48
ldr r0, _020CCC78 ; =0x040002A0
ldr r1, [r0]
ldr r0, [r0, #4]
adds r2, r1, #0x80000
adc r1, r0, #0
mov r0, r2, lsr #0x14
orr r0, r0, r1, lsl #12
bx lr
.align 2, 0
_020CCC74: .word 0x04000280
_020CCC78: .word 0x040002A0
arm_func_end FX_GetDivResult
arm_func_start FX_InvAsync
FX_InvAsync: ; 0x020CCC7C
ldr r2, _020CCCA8 ; =0x04000280
mov r1, #1
strh r1, [r2]
mov r1, #0
str r1, [r2, #0x10]
mov r1, #0x1000
str r1, [r2, #0x14]
str r0, [r2, #0x18]
mov r0, #0
str r0, [r2, #0x1c]
bx lr
.align 2, 0
_020CCCA8: .word 0x04000280
arm_func_end FX_InvAsync
arm_func_start FX_GetSqrtResult
FX_GetSqrtResult: ; 0x020CCCAC
ldr r1, _020CCCD0 ; =0x040002B0
_020CCCB0:
ldrh r0, [r1]
tst r0, #0x8000
bne _020CCCB0
ldr r0, _020CCCD4 ; =0x040002B4
ldr r0, [r0]
add r0, r0, #0x200
mov r0, r0, lsr #0xa
bx lr
.align 2, 0
_020CCCD0: .word 0x040002B0
_020CCCD4: .word 0x040002B4
arm_func_end FX_GetSqrtResult
arm_func_start FX_DivAsync
FX_DivAsync: ; 0x020CCCD8
ldr r3, _020CCCFC ; =0x04000280
mov r2, #1
strh r2, [r3]
mov r2, #0
str r2, [r3, #0x10]
str r0, [r3, #0x14]
str r1, [r3, #0x18]
str r2, [r3, #0x1c]
bx lr
.align 2, 0
_020CCCFC: .word 0x04000280
arm_func_end FX_DivAsync
arm_func_start FX_DivS32
FX_DivS32: ; 0x020CCD00
ldr r2, _020CCD34 ; =0x04000280
mov r3, #0
strh r3, [r2]
str r0, [r2, #0x10]
str r1, [r2, #0x18]
mov r0, r3
str r0, [r2, #0x1c]
_020CCD1C:
ldrh r0, [r2]
tst r0, #0x8000
bne _020CCD1C
ldr r0, _020CCD38 ; =0x040002A0
ldr r0, [r0]
bx lr
.align 2, 0
_020CCD34: .word 0x04000280
_020CCD38: .word 0x040002A0
arm_func_end FX_DivS32
arm_func_start FX_ModS32
FX_ModS32: ; 0x020CCD3C
ldr r2, _020CCD70 ; =0x04000280
mov r3, #0
strh r3, [r2]
str r0, [r2, #0x10]
str r1, [r2, #0x18]
mov r0, r3
str r0, [r2, #0x1c]
_020CCD58:
ldrh r0, [r2]
tst r0, #0x8000
bne _020CCD58
ldr r0, _020CCD74 ; =0x040002A8
ldr r0, [r0]
bx lr
.align 2, 0
_020CCD70: .word 0x04000280
_020CCD74: .word 0x040002A8
arm_func_end FX_ModS32

49
lib/NitroSDK/asm/fx_mtx22.s Normal file
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@ -0,0 +1,49 @@
.include "asm/macros.inc"
.include "global.inc"
.text
arm_func_start MTX_Identity22_
MTX_Identity22_: ; 0x020CAF70
mov r1, #0
mov r2, #0x1000
mov r3, #0
stmia r0!, {r2, r3}
stmia r0!, {r1, r2}
bx lr
arm_func_end MTX_Identity22_
thumb_func_start MTX_Rot22_
MTX_Rot22_: ; 0x020CAF88
str r2, [r0]
str r1, [r0, #4]
neg r1, r1
str r1, [r0, #8]
str r2, [r0, #0xc]
bx lr
thumb_func_end MTX_Rot22_
arm_func_start MTX_ScaleApply22
MTX_ScaleApply22: ; 0x020CAF94
stmdb sp!, {r3, lr}
ldr ip, [r0]
smull lr, ip, r2, ip
mov lr, lr, lsr #0xc
orr lr, lr, ip, lsl #20
str lr, [r1]
ldr ip, [r0, #4]
smull lr, ip, r2, ip
mov r2, lr, lsr #0xc
orr r2, r2, ip, lsl #20
str r2, [r1, #4]
ldr r2, [r0, #8]
smull ip, r2, r3, r2
mov ip, ip, lsr #0xc
orr ip, ip, r2, lsl #20
str ip, [r1, #8]
ldr r0, [r0, #0xc]
smull r2, r0, r3, r0
mov r2, r2, lsr #0xc
orr r2, r2, r0, lsl #20
str r2, [r1, #0xc]
ldmia sp!, {r3, pc}
arm_func_end MTX_ScaleApply22

488
lib/NitroSDK/asm/fx_mtx33.s Normal file
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@ -0,0 +1,488 @@
.include "asm/macros.inc"
.include "global.inc"
.text
arm_func_start MTX_Identity33_
MTX_Identity33_: ; 0x020CAFEC
mov r2, #0x1000
str r2, [r0, #0x20]
mov r3, #0
stmia r0!, {r2, r3}
mov r1, #0
stmia r0!, {r1, r3}
stmia r0!, {r2, r3}
stmia r0!, {r1, r3}
bx lr
arm_func_end MTX_Identity33_
arm_func_start MTX_ScaleApply33
MTX_ScaleApply33: ; 0x020CB010
stmdb sp!, {r4, lr}
ldr r4, [r0]
ldr ip, [sp, #8]
smull lr, r4, r2, r4
mov lr, lr, lsr #0xc
orr lr, lr, r4, lsl #20
str lr, [r1]
ldr r4, [r0, #4]
smull lr, r4, r2, r4
mov lr, lr, lsr #0xc
orr lr, lr, r4, lsl #20
str lr, [r1, #4]
ldr lr, [r0, #8]
smull r4, lr, r2, lr
mov r2, r4, lsr #0xc
orr r2, r2, lr, lsl #20
str r2, [r1, #8]
ldr r2, [r0, #0xc]
smull lr, r2, r3, r2
mov lr, lr, lsr #0xc
orr lr, lr, r2, lsl #20
str lr, [r1, #0xc]
ldr r2, [r0, #0x10]
smull lr, r2, r3, r2
mov lr, lr, lsr #0xc
orr lr, lr, r2, lsl #20
str lr, [r1, #0x10]
ldr r2, [r0, #0x14]
smull lr, r2, r3, r2
mov r3, lr, lsr #0xc
orr r3, r3, r2, lsl #20
str r3, [r1, #0x14]
ldr r2, [r0, #0x18]
smull r3, r2, ip, r2
mov r3, r3, lsr #0xc
orr r3, r3, r2, lsl #20
str r3, [r1, #0x18]
ldr r2, [r0, #0x1c]
smull r3, r2, ip, r2
mov r3, r3, lsr #0xc
orr r3, r3, r2, lsl #20
str r3, [r1, #0x1c]
ldr r0, [r0, #0x20]
smull r2, r0, ip, r0
mov r2, r2, lsr #0xc
orr r2, r2, r0, lsl #20
str r2, [r1, #0x20]
ldmia sp!, {r4, pc}
arm_func_end MTX_ScaleApply33
thumb_func_start MTX_RotX33_
MTX_RotX33_: ; 0x020CB0D0
mov r3, #1
lsl r3, r3, #0xc
str r3, [r0]
mov r3, #0
str r3, [r0, #4]
str r3, [r0, #8]
str r3, [r0, #0xc]
str r2, [r0, #0x10]
str r1, [r0, #0x14]
str r3, [r0, #0x18]
neg r1, r1
str r1, [r0, #0x1c]
str r2, [r0, #0x20]
bx lr
thumb_func_end MTX_RotX33_
thumb_func_start MTX_RotY33_
MTX_RotY33_: ; 0x020CB0EC
str r2, [r0]
str r2, [r0, #0x20]
mov r3, #0
str r3, [r0, #4]
str r3, [r0, #0xc]
str r3, [r0, #0x14]
str r3, [r0, #0x1c]
neg r2, r1
mov r3, #1
lsl r3, r3, #0xc
str r1, [r0, #0x18]
str r2, [r0, #8]
str r3, [r0, #0x10]
bx lr
thumb_func_end MTX_RotY33_
thumb_func_start MTX_RotZ33_
MTX_RotZ33_: ; 0x020CB108
stmia r0!, {r2}
mov r3, #0
stmia r0!, {r1, r3}
neg r1, r1
stmia r0!, {r1, r2}
mov r1, #1
lsl r1, r1, #0xc
str r3, [r0]
str r3, [r0, #4]
str r3, [r0, #8]
str r1, [r0, #0xc]
bx lr
thumb_func_end MTX_RotZ33_
arm_func_start MTX_Inverse33
MTX_Inverse33: ; 0x020CB120
stmdb sp!, {r3, r4, r5, r6, r7, r8, sb, sl, fp, lr}
sub sp, sp, #0x50
mov sl, r0
ldr r0, [sl, #0x14]
cmp sl, r1
addeq sb, sp, #0x2c
ldr r3, [sl, #0x18]
ldr r2, [sl, #0xc]
ldr r6, [sl, #0x20]
str r1, [sp]
movne sb, r1
smull fp, r8, r2, r6
smull r7, r1, r0, r3
subs r7, fp, r7
sbc ip, r8, r1
ldr r4, [sl, #0x10]
ldr r5, [sl, #0x1c]
adds r1, r7, #0x800
smull fp, r8, r4, r6
smull r7, r6, r0, r5
adc r0, ip, #0
subs r7, fp, r7
sbc r6, r8, r6
mov r8, r1, lsr #0xc
orr r8, r8, r0, lsl #20
smull r1, r0, r2, r5
adds r7, r7, #0x800
smull r5, r3, r4, r3
adc r2, r6, #0
mov r7, r7, lsr #0xc
orr r7, r7, r2, lsl #20
subs r1, r1, r5
sbc r5, r0, r3
ldr r2, [sl]
adds r6, r1, #0x800
ldr fp, [sl, #4]
smull r4, r3, r2, r7
smull r1, r0, fp, r8
adc r2, r5, #0
mov r6, r6, lsr #0xc
orr r6, r6, r2, lsl #20
subs r2, r4, r1
ldr r1, [sl, #8]
sbc r0, r3, r0
smlal r2, r0, r1, r6
adds r1, r2, #0x800
adc r2, r0, #0
mov r0, r1, lsr #0xc
mov r1, r8, asr #0x1f
str r1, [sp, #4]
mov r1, r7, asr #0x1f
str r1, [sp, #8]
mov r1, r6, asr #0x1f
str r1, [sp, #0xc]
orrs r0, r0, r2, lsl #20
mov r1, #0
addeq sp, sp, #0x50
subeq r0, r1, #1
ldmeqia sp!, {r3, r4, r5, r6, r7, r8, sb, sl, fp, pc}
bl FX_InvAsync
ldr r1, [sl, #8]
ldr r2, [sl, #0x1c]
ldr fp, [sl, #0x10]
smull r0, r4, r2, r1
smull r3, r2, fp, r1
ldr r5, [sl, #0x18]
str r2, [sp, #0x18]
str r3, [sp, #0x14]
smull r3, r2, r5, r1
str r2, [sp, #0x20]
ldr r2, [sl, #0x20]
str r3, [sp, #0x1c]
str r2, [sp, #0x10]
ldr r5, [sp, #0x10]
ldmia sl, {r3, lr}
smull ip, r5, lr, r5
subs r0, ip, r0
ldr r2, [sl, #0xc]
sbc r4, r5, r4
smull r1, r5, r2, r1
str r5, [sp, #0x28]
mov r5, r0, lsr #0xc
ldr fp, [sl, #0x14]
orr r5, r5, r4, lsl #20
smull r4, r2, lr, fp
ldr r0, [sp, #0x14]
subs r4, r4, r0
ldr r0, [sp, #0x18]
mov r4, r4, lsr #0xc
sbc r0, r2, r0
orr r4, r4, r0, lsl #20
ldr r0, [sp, #0x10]
ldr r2, [sp, #0x1c]
smull ip, r0, r3, r0
subs r2, ip, r2
ldr ip, [sp, #0x20]
sbc r0, r0, ip
smull ip, fp, r3, fp
ldr r3, [sp, #0x28]
subs r1, ip, r1
sbc r3, fp, r3
mov fp, r2, lsr #0xc
orr fp, fp, r0, lsl #20
mov r0, r1, lsr #0xc
orr r0, r0, r3, lsl #20
str r0, [sp, #0x24]
bl FX_GetDivResult
smull r2, r1, r0, r5
mov r2, r2, lsr #0xc
orr r2, r2, r1, lsl #20
rsb lr, r2, #0
smull r2, r1, r0, r4
mov r4, r2, lsr #0xc
orr r4, r4, r1, lsl #20
smull r2, r1, r0, fp
mov r3, r2, lsr #0xc
orr r3, r3, r1, lsl #20
ldr r1, [sp, #0x24]
umull fp, r5, r0, r7
smull r2, r1, r0, r1
mov r2, r2, lsr #0xc
orr r2, r2, r1, lsl #20
ldr r1, [sp, #8]
mov ip, r0, asr #0x1f
mla r5, r0, r1, r5
mla r5, ip, r7, r5
mov r1, fp, lsr #0xc
orr r1, r1, r5, lsl #20
stmia sb, {r1, lr}
str r4, [sb, #8]
ldr r1, [sp, #4]
umull r5, r4, r0, r8
mla r4, r0, r1, r4
mla r4, ip, r8, r4
mov r1, r5, lsr #0xc
orr r1, r1, r4, lsl #20
rsb r1, r1, #0
str r1, [sb, #0xc]
ldr r1, [sp, #0xc]
rsb r2, r2, #0
str r3, [sb, #0x10]
str r2, [sb, #0x14]
umull r3, r2, r0, r6
mla r2, r0, r1, r2
mla r2, ip, r6, r2
mov r1, r3, lsr #0xc
orr r1, r1, r2, lsl #20
str r1, [sb, #0x18]
ldr r3, [sl]
ldr r1, [sl, #0x1c]
ldr r2, [sl, #0x18]
smull r5, r4, r3, r1
ldr r1, [sl, #4]
smull r3, r1, r2, r1
subs r2, r5, r3
sbc r1, r4, r1
mov r2, r2, lsr #0xc
orr r2, r2, r1, lsl #20
smull r2, r1, r0, r2
mov r2, r2, lsr #0xc
orr r2, r2, r1, lsl #20
rsb r1, r2, #0
str r1, [sb, #0x1c]
ldr r4, [sl]
ldr r3, [sl, #0x10]
ldr r2, [sl, #0xc]
ldr r1, [sl, #4]
smull r6, r5, r4, r3
smull r3, r1, r2, r1
subs r2, r6, r3
sbc r1, r5, r1
mov r2, r2, lsr #0xc
orr r2, r2, r1, lsl #20
mov r1, r2, asr #0x1f
umull r4, r3, r0, r2
mla r3, r0, r1, r3
add r0, sp, #0x2c
mla r3, ip, r2, r3
mov r1, r4, lsr #0xc
orr r1, r1, r3, lsl #20
str r1, [sb, #0x20]
cmp sb, r0
bne _020CB404
ldr r1, [sp]
bl MI_Copy36B
_020CB404:
mov r0, #0
add sp, sp, #0x50
ldmia sp!, {r3, r4, r5, r6, r7, r8, sb, sl, fp, pc}
arm_func_end MTX_Inverse33
arm_func_start MTX_Concat33
MTX_Concat33: ; 0x020CB410
stmdb sp!, {r3, r4, r5, r6, r7, r8, sb, sl, fp, lr}
sub sp, sp, #0x40
mov ip, r2
ldr r3, [r0, #4]
ldr r2, [r1, #0xc]
cmp ip, r1
smull r7, r5, r3, r2
ldr r6, [r0]
ldr r4, [r1]
addeq sl, sp, #0x1c
smlal r7, r5, r6, r4
ldr r2, [r0, #8]
ldr r4, [r1, #0x18]
movne sl, ip
smlal r7, r5, r2, r4
mov r4, r7, lsr #0xc
orr r4, r4, r5, lsl #20
str r4, [sl]
ldr r4, [r1, #0x10]
ldr r5, [r1, #4]
smull r8, r7, r3, r4
smlal r8, r7, r6, r5
ldr r4, [r1, #0x1c]
smlal r8, r7, r2, r4
mov r4, r8, lsr #0xc
orr r4, r4, r7, lsl #20
str r4, [sl, #4]
ldr r4, [r1, #0x14]
ldr r5, [r1, #8]
smull r8, r7, r3, r4
smlal r8, r7, r6, r5
ldr r3, [r1, #0x20]
smlal r8, r7, r2, r3
mov r2, r8, lsr #0xc
orr r2, r2, r7, lsl #20
str r2, [sl, #8]
ldr sb, [r0, #0x10]
ldr r2, [r0, #0xc]
smull r7, r6, sb, r4
smlal r7, r6, r2, r5
ldr r4, [r0, #0x14]
smlal r7, r6, r4, r3
mov r3, r7, lsr #0xc
orr r3, r3, r6, lsl #20
str r3, [sl, #0x14]
ldr r3, [r1, #0x10]
ldr r5, [r1, #4]
smull r7, r6, sb, r3
smlal r7, r6, r2, r5
ldr r5, [r1, #0x1c]
mov r3, sb, asr #0x1f
smlal r7, r6, r4, r5
str r3, [sp]
mov r3, r7, lsr #0xc
orr r3, r3, r6, lsl #20
str r3, [sl, #0x10]
mov r3, r2, asr #0x1f
str r3, [sp, #4]
mov r3, r4, asr #0x1f
ldr r8, [r1, #0xc]
str r3, [sp, #8]
mov r3, r8, asr #0x1f
str r3, [sp, #0x18]
ldr r7, [r1]
ldr r6, [r1, #0x18]
mov r3, r7, asr #0x1f
str r3, [sp, #0xc]
umull r3, r5, r4, r6
mov fp, r6, asr #0x1f
str r3, [sp, #0x10]
mla r5, r4, fp, r5
ldr r3, [sp, #8]
add lr, sp, #0x1c
mla r5, r3, r6, r5
umull r3, r4, r2, r7
str r3, [sp, #0x14]
ldr r3, [sp, #0xc]
mla r4, r2, r3, r4
ldr r2, [sp, #4]
umull r3, fp, sb, r8
mla r4, r2, r7, r4
ldr r2, [sp, #0x14]
adds r3, r2, r3
ldr r2, [sp, #0x18]
mla fp, sb, r2, fp
ldr r2, [sp]
mla fp, r2, r8, fp
adc r4, r4, fp
ldr r2, [sp, #0x10]
ldr fp, [sp, #0x18]
adds r3, r2, r3
adc r2, r5, r4
mov r3, r3, lsr #0xc
orr r3, r3, r2, lsl #20
str r3, [sl, #0xc]
ldr r2, [r0, #0x1c]
ldr r5, [r0, #0x18]
ldr r4, [r0, #0x20]
umull r3, r0, r2, r8
mla r0, r2, fp, r0
mov sb, r2, asr #0x1f
mla r0, sb, r8, r0
smlal r3, r0, r5, r7
smlal r3, r0, r4, r6
mov r3, r3, lsr #0xc
orr r3, r3, r0, lsl #20
str r3, [sl, #0x18]
ldr r0, [r1, #0x10]
ldr r3, [r1, #4]
smull r7, r0, r2, r0
cmp sl, lr
smlal r7, r0, r5, r3
ldr r6, [r1, #0x1c]
addne sp, sp, #0x40
smlal r7, r0, r4, r6
mov r3, r7, lsr #0xc
orr r3, r3, r0, lsl #20
str r3, [sl, #0x1c]
ldr r0, [r1, #0x14]
ldr r6, [r1, #0x20]
ldr r3, [r1, #8]
smull r1, r0, r2, r0
smlal r1, r0, r5, r3
smlal r1, r0, r4, r6
mov r1, r1, lsr #0xc
orr r1, r1, r0, lsl #20
str r1, [sl, #0x20]
ldmneia sp!, {r3, r4, r5, r6, r7, r8, sb, sl, fp, pc}
ldmia lr!, {r0, r1, r2, r3}
stmia ip!, {r0, r1, r2, r3}
ldmia lr!, {r0, r1, r2, r3}
stmia ip!, {r0, r1, r2, r3}
ldr r0, [lr]
str r0, [ip]
add sp, sp, #0x40
ldmia sp!, {r3, r4, r5, r6, r7, r8, sb, sl, fp, pc}
arm_func_end MTX_Concat33
arm_func_start MTX_MultVec33
MTX_MultVec33: ; 0x020CB630
stmdb sp!, {r4, r5, r6, lr}
ldr r4, [r1, #0xc]
ldmia r0, {r3, ip}
smull r6, r5, ip, r4
ldr r4, [r1]
ldr r0, [r0, #8]
smlal r6, r5, r3, r4
ldr r4, [r1, #0x18]
smlal r6, r5, r0, r4
mov r4, r6, lsr #0xc
orr r4, r4, r5, lsl #20
str r4, [r2]
ldr r4, [r1, #0x10]
ldr r5, [r1, #4]
smull r6, lr, ip, r4
smlal r6, lr, r3, r5
ldr r4, [r1, #0x1c]
smlal r6, lr, r0, r4
mov r4, r6, lsr #0xc
orr r4, r4, lr, lsl #20
str r4, [r2, #4]
ldr lr, [r1, #0x14]
ldr r4, [r1, #8]
smull r5, lr, ip, lr
smlal r5, lr, r3, r4
ldr r1, [r1, #0x20]
smlal r5, lr, r0, r1
mov r0, r5, lsr #0xc
orr r0, r0, lr, lsl #20
str r0, [r2, #8]
ldmia sp!, {r4, r5, r6, pc}
arm_func_end MTX_MultVec33

684
lib/NitroSDK/asm/fx_mtx43.s Normal file
View File

@ -0,0 +1,684 @@
.include "asm/macros.inc"
.include "global.inc"
.text
arm_func_start MTX_Identity43_
MTX_Identity43_: ; 0x020CB6AC
mov r2, #0x1000
mov r3, #0
stmia r0!, {r2, r3}
mov r1, #0
stmia r0!, {r1, r3}
stmia r0!, {r2, r3}
stmia r0!, {r1, r3}
stmia r0!, {r2, r3}
stmia r0!, {r1, r3}
bx lr
arm_func_end MTX_Identity43_
arm_func_start MTX_Copy43To44_
MTX_Copy43To44_: ; 0x020CB6D4
stmdb sp!, {r4}
mov ip, #0
ldmia r0!, {r2, r3, r4}
stmia r1!, {r2, r3, r4, ip}
ldmia r0!, {r2, r3, r4}
stmia r1!, {r2, r3, r4, ip}
ldmia r0!, {r2, r3, r4}
stmia r1!, {r2, r3, r4, ip}
mov ip, #0x1000
ldmia r0!, {r2, r3, r4}
stmia r1!, {r2, r3, r4, ip}
ldmia sp!, {r4}
bx lr
arm_func_end MTX_Copy43To44_
arm_func_start MTX_TransApply43
MTX_TransApply43: ; 0x020CB708
stmdb sp!, {r3, r4, r5, r6, r7, lr}
mov r7, r0
mov r6, r1
mov r5, r2
mov r4, r3
cmp r7, r6
beq _020CB728
bl MI_Copy36B
_020CB728:
ldr r0, [r7, #0xc]
ldr r1, [r7]
smull r3, r2, r4, r0
smlal r3, r2, r5, r1
ldr r0, [sp, #0x18]
ldr r1, [r7, #0x18]
ldr ip, [r7, #0x24]
smlal r3, r2, r0, r1
mov r1, r3, lsr #0xc
orr r1, r1, r2, lsl #20
add r1, ip, r1
str r1, [r6, #0x24]
ldr r1, [r7, #0x10]
ldr r2, [r7, #4]
smull ip, r3, r4, r1
smlal ip, r3, r5, r2
ldr r1, [r7, #0x1c]
ldr r2, [r7, #0x28]
smlal ip, r3, r0, r1
mov r1, ip, lsr #0xc
orr r1, r1, r3, lsl #20
add r1, r2, r1
str r1, [r6, #0x28]
ldr r1, [r7, #0x14]
ldr r2, [r7, #8]
smull ip, r3, r4, r1
smlal ip, r3, r5, r2
ldr r1, [r7, #0x20]
ldr r2, [r7, #0x2c]
smlal ip, r3, r0, r1
mov r0, ip, lsr #0xc
orr r0, r0, r3, lsl #20
add r0, r2, r0
str r0, [r6, #0x2c]
ldmia sp!, {r3, r4, r5, r6, r7, pc}
arm_func_end MTX_TransApply43
thumb_func_start MTX_Scale43_
MTX_Scale43_: ; 0x020CB7B4
stmia r0!, {r1}
mov r1, #0
str r3, [r0, #0x1c]
mov r3, #0
stmia r0!, {r1, r3}
stmia r0!, {r1, r2, r3}
mov r2, #0
stmia r0!, {r1, r3}
add r0, #4
stmia r0!, {r1, r2, r3}
bx lr
.align 2, 0
thumb_func_end MTX_Scale43_
arm_func_start MTX_ScaleApply43
MTX_ScaleApply43: ; 0x020CB7CC
stmdb sp!, {r3, r4, r5, lr}
ldr ip, [sp, #0x10]
mov r5, r0
str ip, [sp]
mov r4, r1
bl MTX_ScaleApply33
ldr r0, [r5, #0x24]
str r0, [r4, #0x24]
ldr r0, [r5, #0x28]
str r0, [r4, #0x28]
ldr r0, [r5, #0x2c]
str r0, [r4, #0x2c]
ldmia sp!, {r3, r4, r5, pc}
arm_func_end MTX_ScaleApply43
thumb_func_start MTX_RotX43_
MTX_RotX43_: ; 0x020CB800
str r1, [r0, #0x14]
neg r1, r1
str r1, [r0, #0x1c]
mov r1, #1
lsl r1, r1, #0xc
stmia r0!, {r1}
mov r3, #0
mov r1, #0
stmia r0!, {r1, r3}
stmia r0!, {r1, r2}
str r1, [r0, #4]
add r0, #0xc
stmia r0!, {r2, r3}
stmia r0!, {r1, r3}
bx lr
.align 2, 0
thumb_func_end MTX_RotX43_
thumb_func_start MTX_RotY43_
MTX_RotY43_: ; 0x020CB820
str r1, [r0, #0x18]
mov r3, #0
stmia r0!, {r2, r3}
neg r1, r1
stmia r0!, {r1, r3}
mov r1, #1
lsl r1, r1, #0xc
stmia r0!, {r1, r3}
add r0, #4
mov r1, #0
stmia r0!, {r1, r2, r3}
stmia r0!, {r1, r3}
bx lr
.align 2, 0
thumb_func_end MTX_RotY43_
arm_func_start MTX_Inverse43
MTX_Inverse43: ; 0x020CB83C
stmdb sp!, {r4, r5, r6, r7, r8, sb, sl, fp, lr}
sub sp, sp, #0x5c
mov sl, r0
ldr r0, [sl, #0x14]
cmp sl, r1
addeq sb, sp, #0x2c
ldr r3, [sl, #0x18]
ldr r2, [sl, #0xc]
ldr r6, [sl, #0x20]
str r1, [sp]
movne sb, r1
smull fp, r8, r2, r6
smull r7, r1, r0, r3
subs r7, fp, r7
sbc ip, r8, r1
ldr r4, [sl, #0x10]
ldr r5, [sl, #0x1c]
adds r1, r7, #0x800
smull fp, r8, r4, r6
smull r7, r6, r0, r5
adc r0, ip, #0
subs r7, fp, r7
sbc r6, r8, r6
mov r8, r1, lsr #0xc
orr r8, r8, r0, lsl #20
smull r1, r0, r2, r5
adds r7, r7, #0x800
smull r5, r3, r4, r3
adc r2, r6, #0
mov r7, r7, lsr #0xc
orr r7, r7, r2, lsl #20
subs r1, r1, r5
sbc r5, r0, r3
ldr r2, [sl]
adds r6, r1, #0x800
ldr fp, [sl, #4]
smull r4, r3, r2, r7
smull r1, r0, fp, r8
adc r2, r5, #0
mov r6, r6, lsr #0xc
orr r6, r6, r2, lsl #20
subs r2, r4, r1
ldr r1, [sl, #8]
sbc r0, r3, r0
smlal r2, r0, r1, r6
adds r1, r2, #0x800
adc r2, r0, #0
mov r0, r1, lsr #0xc
mov r1, r8, asr #0x1f
str r1, [sp, #4]
mov r1, r7, asr #0x1f
str r1, [sp, #8]
mov r1, r6, asr #0x1f
str r1, [sp, #0xc]
orrs r0, r0, r2, lsl #20
mov r1, #0
addeq sp, sp, #0x5c
subeq r0, r1, #1
ldmeqia sp!, {r4, r5, r6, r7, r8, sb, sl, fp, pc}
bl FX_InvAsync
ldr r1, [sl, #8]
ldr r2, [sl, #0x1c]
ldr fp, [sl, #0x10]
smull r0, r4, r2, r1
smull r3, r2, fp, r1
ldr r5, [sl, #0x18]
str r2, [sp, #0x18]
str r3, [sp, #0x14]
smull r3, r2, r5, r1
str r2, [sp, #0x20]
ldr r2, [sl, #0x20]
str r3, [sp, #0x1c]
str r2, [sp, #0x10]
ldr r5, [sp, #0x10]
ldmia sl, {r3, lr}
smull ip, r5, lr, r5
subs r0, ip, r0
ldr r2, [sl, #0xc]
sbc r4, r5, r4
smull r1, r5, r2, r1
str r5, [sp, #0x28]
mov r5, r0, lsr #0xc
ldr fp, [sl, #0x14]
orr r5, r5, r4, lsl #20
smull r4, r2, lr, fp
ldr r0, [sp, #0x14]
subs r4, r4, r0
ldr r0, [sp, #0x18]
mov r4, r4, lsr #0xc
sbc r0, r2, r0
orr r4, r4, r0, lsl #20
ldr r0, [sp, #0x10]
ldr r2, [sp, #0x1c]
smull ip, r0, r3, r0
subs r2, ip, r2
ldr ip, [sp, #0x20]
sbc r0, r0, ip
smull ip, fp, r3, fp
ldr r3, [sp, #0x28]
subs r1, ip, r1
sbc r3, fp, r3
mov fp, r2, lsr #0xc
orr fp, fp, r0, lsl #20
mov r0, r1, lsr #0xc
orr r0, r0, r3, lsl #20
str r0, [sp, #0x24]
bl FX_GetDivResult
smull r2, r1, r0, r5
mov r2, r2, lsr #0xc
orr r2, r2, r1, lsl #20
rsb lr, r2, #0
smull r2, r1, r0, r4
mov r4, r2, lsr #0xc
orr r4, r4, r1, lsl #20
smull r2, r1, r0, fp
mov r3, r2, lsr #0xc
orr r3, r3, r1, lsl #20
ldr r1, [sp, #0x24]
umull fp, r5, r0, r7
smull r2, r1, r0, r1
mov r2, r2, lsr #0xc
orr r2, r2, r1, lsl #20
ldr r1, [sp, #8]
mov ip, r0, asr #0x1f
mla r5, r0, r1, r5
mla r5, ip, r7, r5
mov r1, fp, lsr #0xc
orr r1, r1, r5, lsl #20
stmia sb, {r1, lr}
str r4, [sb, #8]
ldr r1, [sp, #4]
umull r5, r4, r0, r8
mla r4, r0, r1, r4
mla r4, ip, r8, r4
mov r1, r5, lsr #0xc
orr r1, r1, r4, lsl #20
rsb r1, r1, #0
str r1, [sb, #0xc]
ldr r1, [sp, #0xc]
rsb r2, r2, #0
str r3, [sb, #0x10]
str r2, [sb, #0x14]
umull r3, r2, r0, r6
mla r2, r0, r1, r2
mla r2, ip, r6, r2
mov r1, r3, lsr #0xc
orr r1, r1, r2, lsl #20
str r1, [sb, #0x18]
ldr r3, [sl]
ldr r1, [sl, #0x1c]
ldr r2, [sl, #0x18]
smull r5, r4, r3, r1
ldr r1, [sl, #4]
smull r3, r1, r2, r1
subs r2, r5, r3
sbc r1, r4, r1
mov r2, r2, lsr #0xc
orr r2, r2, r1, lsl #20
smull r2, r1, r0, r2
mov r2, r2, lsr #0xc
orr r2, r2, r1, lsl #20
rsb r1, r2, #0
str r1, [sb, #0x1c]
ldr r4, [sl]
ldr r3, [sl, #0x10]
ldr r2, [sl, #0xc]
ldr r1, [sl, #4]
smull r6, r5, r4, r3
smull r3, r1, r2, r1
subs r2, r6, r3
sbc r1, r5, r1
mov r2, r2, lsr #0xc
orr r2, r2, r1, lsl #20
mov r1, r2, asr #0x1f
umull r4, r3, r0, r2
mla r3, r0, r1, r3
mla r3, ip, r2, r3
mov r0, r4, lsr #0xc
orr r0, r0, r3, lsl #20
str r0, [sb, #0x20]
ldr r1, [sb, #0xc]
ldr r0, [sl, #0x28]
ldr r2, [sb]
smull r5, r4, r1, r0
ldr r0, [sl, #0x24]
ldr r3, [sb, #0x18]
smlal r5, r4, r2, r0
ldr r1, [sl, #0x2c]
add r0, sp, #0x2c
smlal r5, r4, r3, r1
mov r1, r5, lsr #0xc
orr r1, r1, r4, lsl #20
rsb r1, r1, #0
str r1, [sb, #0x24]
ldr r2, [sb, #0x10]
ldr r1, [sl, #0x28]
ldr r3, [sb, #4]
smull r5, r4, r2, r1
ldr r1, [sl, #0x24]
ldr r2, [sb, #0x1c]
smlal r5, r4, r3, r1
ldr r1, [sl, #0x2c]
cmp sb, r0
smlal r5, r4, r2, r1
mov r1, r5, lsr #0xc
orr r1, r1, r4, lsl #20
rsb r1, r1, #0
str r1, [sb, #0x28]
ldr r2, [sb, #0x14]
ldr r1, [sl, #0x28]
ldr r3, [sb, #8]
smull r6, r5, r2, r1
ldr r1, [sl, #0x24]
ldr r4, [sb, #0x20]
smlal r6, r5, r3, r1
ldr r2, [sl, #0x2c]
smlal r6, r5, r4, r2
mov r1, r6, lsr #0xc
orr r1, r1, r5, lsl #20
rsb r1, r1, #0
str r1, [sb, #0x2c]
bne _020CBBBC
ldr r1, [sp]
bl MI_Copy48B
_020CBBBC:
mov r0, #0
add sp, sp, #0x5c
ldmia sp!, {r4, r5, r6, r7, r8, sb, sl, fp, pc}
arm_func_end MTX_Inverse43
arm_func_start MTX_Concat43
MTX_Concat43: ; 0x020CBBC8
stmdb sp!, {r4, r5, r6, r7, r8, sb, sl, fp, lr}
sub sp, sp, #0x4c
mov ip, r2
ldr r2, [r0, #4]
ldr r3, [r1, #0xc]
cmp ip, r1
smull r7, r4, r2, r3
ldr r6, [r0]
ldr r3, [r1]
addeq sl, sp, #0x1c
smlal r7, r4, r6, r3
ldr r5, [r0, #8]
ldr r3, [r1, #0x18]
movne sl, ip
smlal r7, r4, r5, r3
mov r3, r7, lsr #0xc
orr r3, r3, r4, lsl #20
str r3, [sl]
ldr r3, [r1, #0x10]
ldr r4, [r1, #4]
smull r8, r7, r2, r3
smlal r8, r7, r6, r4
ldr r3, [r1, #0x1c]
smlal r8, r7, r5, r3
mov r3, r8, lsr #0xc
orr r3, r3, r7, lsl #20
str r3, [sl, #4]
ldr r3, [r1, #0x14]
ldr r4, [r1, #8]
smull r8, r7, r2, r3
smlal r8, r7, r6, r4
ldr r2, [r1, #0x20]
smlal r8, r7, r5, r2
mov r5, r8, lsr #0xc
orr r5, r5, r7, lsl #20
str r5, [sl, #8]
ldr r8, [r0, #0x10]
ldr sb, [r0, #0xc]
smull r5, r3, r8, r3
smlal r5, r3, sb, r4
ldr r7, [r0, #0x14]
mov r6, sb, asr #0x1f
smlal r5, r3, r7, r2
mov r2, r5, lsr #0xc
orr r2, r2, r3, lsl #20
str r2, [sl, #0x14]
ldr r2, [r1, #0x10]
ldr r3, [r1, #4]
smull r5, r4, r8, r2
smlal r5, r4, sb, r3
ldr r3, [r1, #0x1c]
mov r2, r8, asr #0x1f
smlal r5, r4, r7, r3
str r2, [sp, #0x14]
mov r2, r5, lsr #0xc
orr r2, r2, r4, lsl #20
str r2, [sl, #0x10]
mov r2, r7, asr #0x1f
ldr r5, [r1]
str r2, [sp]
ldr r4, [r1, #0xc]
ldr lr, [r1, #0x18]
mov r2, r4, asr #0x1f
str r2, [sp, #4]
mov r2, r5, asr #0x1f
str r2, [sp, #8]
umull r2, r3, r7, lr
mov fp, lr, asr #0x1f
mla r3, r7, fp, r3
str r2, [sp, #0xc]
ldr r2, [sp]
ldr r7, [sp, #8]
mla r3, r2, lr, r3
umull fp, r2, sb, r5
mla r2, sb, r7, r2
mla r2, r6, r5, r2
ldr r6, [sp, #4]
umull sb, r7, r8, r4
mla r7, r8, r6, r7
ldr r8, [sp, #0x14]
adds r6, fp, sb
mla r7, r8, r4, r7
adc r7, r2, r7
ldr r2, [sp, #0xc]
adds r6, r2, r6
adc r2, r3, r7
mov r3, r6, lsr #0xc
orr r3, r3, r2, lsl #20
str r3, [sl, #0xc]
ldr r3, [r0, #0x1c]
ldr r6, [r0, #0x18]
smull r7, r4, r3, r4
smlal r7, r4, r6, r5
ldr r2, [r0, #0x20]
smlal r7, r4, r2, lr
mov r5, r7, lsr #0xc
orr r5, r5, r4, lsl #20
str r5, [sl, #0x18]
ldr r4, [r1, #0x10]
ldr r5, [r1, #4]
smull r8, r4, r3, r4
smlal r8, r4, r6, r5
ldr r7, [r1, #0x1c]
smlal r8, r4, r2, r7
mov r5, r8, lsr #0xc
orr r5, r5, r4, lsl #20
str r5, [sl, #0x1c]
ldr r5, [r1, #0x14]
ldr r4, [r1, #8]
smull r8, r7, r3, r5
smlal r8, r7, r6, r4
ldr r3, [r1, #0x20]
smlal r8, r7, r2, r3
mov r2, r8, lsr #0xc
orr r2, r2, r7, lsl #20
str r2, [sl, #0x20]
ldr r2, [r0, #0x28]
ldr sb, [r0, #0x24]
ldr r7, [r0, #0x2c]
smull r5, r0, r2, r5
smlal r5, r0, sb, r4
smlal r5, r0, r7, r3
mov r3, r5, lsr #0xc
orr r3, r3, r0, lsl #20
mov r0, r7, asr #0x1f
str r0, [sp, #0x18]
ldr r0, [r1, #0x2c]
mov fp, r2, asr #0x1f
adds r0, r0, r3
str r0, [sl, #0x2c]
ldr r3, [r1, #0x10]
ldr r4, [r1, #4]
smull r6, r3, r2, r3
smlal r6, r3, sb, r4
ldr r5, [r1, #0x1c]
ldr r0, [r1, #0x28]
smlal r6, r3, r7, r5
mov r4, r6, lsr #0xc
orr r4, r4, r3, lsl #20
adds r0, r0, r4
mov r8, sb, asr #0x1f
str r0, [sl, #0x28]
ldr r4, [r1]
ldr r3, [r1, #0xc]
umull r0, r5, sb, r4
mov lr, r4, asr #0x1f
mla r5, sb, lr, r5
mov sb, r3, asr #0x1f
str r0, [sp, #0x10]
mla r5, r8, r4, r5
umull r8, r0, r2, r3
mla r0, r2, sb, r0
ldr r4, [sp, #0x10]
mla r0, fp, r3, r0
adds r4, r4, r8
adc r2, r5, r0
ldr r6, [r1, #0x18]
ldr r8, [r1, #0x24]
mov r1, r6, asr #0x1f
umull r5, r3, r7, r6
mla r3, r7, r1, r3
adds r1, r5, r4
ldr r0, [sp, #0x18]
mov r1, r1, lsr #0xc
mla r3, r0, r6, r3
adc r0, r3, r2
orr r1, r1, r0, lsl #20
adds r0, r8, r1
add r4, sp, #0x1c
cmp sl, r4
addne sp, sp, #0x4c
str r0, [sl, #0x24]
ldmneia sp!, {r4, r5, r6, r7, r8, sb, sl, fp, pc}
ldmia r4!, {r0, r1, r2, r3}
stmia ip!, {r0, r1, r2, r3}
ldmia r4!, {r0, r1, r2, r3}
stmia ip!, {r0, r1, r2, r3}
ldmia r4, {r0, r1, r2, r3}
stmia ip, {r0, r1, r2, r3}
add sp, sp, #0x4c
ldmia sp!, {r4, r5, r6, r7, r8, sb, sl, fp, pc}
arm_func_end MTX_Concat43
arm_func_start MTX_MultVec43
MTX_MultVec43: ; 0x020CBE9C
stmdb sp!, {r4, r5, r6, lr}
ldr r4, [r1, #0xc]
ldmia r0, {r3, ip}
smull r6, r5, ip, r4
ldr r4, [r1]
ldr r0, [r0, #8]
smlal r6, r5, r3, r4
ldr r4, [r1, #0x18]
smlal r6, r5, r0, r4
mov r6, r6, lsr #0xc
orr r6, r6, r5, lsl #20
str r6, [r2]
ldr r4, [r1, #0x24]
add r4, r6, r4
str r4, [r2]
ldr r4, [r1, #0x10]
ldr r5, [r1, #4]
smull r6, lr, ip, r4
smlal r6, lr, r3, r5
ldr r4, [r1, #0x1c]
smlal r6, lr, r0, r4
mov r5, r6, lsr #0xc
orr r5, r5, lr, lsl #20
str r5, [r2, #4]
ldr r4, [r1, #0x28]
add r4, r5, r4
str r4, [r2, #4]
ldr lr, [r1, #0x14]
ldr r4, [r1, #8]
smull r5, lr, ip, lr
smlal r5, lr, r3, r4
ldr r3, [r1, #0x20]
smlal r5, lr, r0, r3
mov r3, r5, lsr #0xc
orr r3, r3, lr, lsl #20
str r3, [r2, #8]
ldr r0, [r1, #0x2c]
add r0, r3, r0
str r0, [r2, #8]
ldmia sp!, {r4, r5, r6, pc}
arm_func_end MTX_MultVec43
arm_func_start MTX_LookAt
MTX_LookAt: ; 0x020CBF3C
stmdb sp!, {r3, r4, r5, r6, lr}
sub sp, sp, #0x24
mov r6, r0
ldr r5, [r6]
ldr r4, [r2]
add r0, sp, #0x18
sub r4, r5, r4
str r4, [sp, #0x18]
ldr ip, [r6, #4]
ldr r4, [r2, #4]
mov r5, r1
sub r1, ip, r4
str r1, [sp, #0x1c]
ldr r4, [r6, #8]
ldr r2, [r2, #8]
mov r1, r0
sub r2, r4, r2
mov r4, r3
str r2, [sp, #0x20]
bl VEC_Normalize
add r1, sp, #0x18
add r2, sp, #0xc
mov r0, r5
bl VEC_CrossProduct
add r0, sp, #0xc
mov r1, r0
bl VEC_Normalize
add r0, sp, #0x18
add r1, sp, #0xc
add r2, sp, #0
bl VEC_CrossProduct
ldr r1, [sp, #0xc]
mov r0, r6
str r1, [r4]
ldr r2, [sp]
add r1, sp, #0xc
str r2, [r4, #4]
ldr r2, [sp, #0x18]
str r2, [r4, #8]
ldr r2, [sp, #0x10]
str r2, [r4, #0xc]
ldr r2, [sp, #4]
str r2, [r4, #0x10]
ldr r2, [sp, #0x1c]
str r2, [r4, #0x14]
ldr r2, [sp, #0x14]
str r2, [r4, #0x18]
ldr r2, [sp, #8]
str r2, [r4, #0x1c]
ldr r2, [sp, #0x20]
str r2, [r4, #0x20]
bl VEC_DotProduct
rsb r0, r0, #0
str r0, [r4, #0x24]
mov r0, r6
add r1, sp, #0
bl VEC_DotProduct
rsb r0, r0, #0
str r0, [r4, #0x28]
mov r0, r6
add r1, sp, #0x18
bl VEC_DotProduct
rsb r0, r0, #0
str r0, [r4, #0x2c]
add sp, sp, #0x24
ldmia sp!, {r3, r4, r5, r6, pc}
arm_func_end MTX_LookAt

801
lib/NitroSDK/asm/fx_mtx44.s Normal file
View File

@ -0,0 +1,801 @@
.include "asm/macros.inc"
.include "global.inc"
.text
arm_func_start MTX_Identity44_
MTX_Identity44_: ; 0x020CC044
mov r2, #0x1000
mov r3, #0
stmia r0!, {r2, r3}
mov r1, #0
stmia r0!, {r1, r3}
stmia r0!, {r1, r2, r3}
stmia r0!, {r1, r3}
stmia r0!, {r1, r2, r3}
stmia r0!, {r1, r3}
stmia r0!, {r1, r2}
bx lr
arm_func_end MTX_Identity44_
arm_func_start MTX_Copy44To43_
MTX_Copy44To43_: ; 0x020CC070
ldmia r0!, {r2, r3, ip}
add r0, r0, #4
stmia r1!, {r2, r3, ip}
ldmia r0!, {r2, r3, ip}
add r0, r0, #4
stmia r1!, {r2, r3, ip}
ldmia r0!, {r2, r3, ip}
add r0, r0, #4
stmia r1!, {r2, r3, ip}
ldmia r0!, {r2, r3, ip}
add r0, r0, #4
stmia r1!, {r2, r3, ip}
bx lr
arm_func_end MTX_Copy44To43_
arm_func_start MTX_TransApply44
MTX_TransApply44: ; 0x020CC0A4
stmdb sp!, {r3, r4, r5, r6, r7, lr}
mov r7, r0
mov r6, r1
mov r5, r2
mov r4, r3
cmp r7, r6
beq _020CC0C4
bl MI_Copy48B
_020CC0C4:
ldr r0, [r7, #0x10]
ldr r1, [r7]
smull r3, r2, r4, r0
smlal r3, r2, r5, r1
ldr r0, [sp, #0x18]
ldr r1, [r7, #0x20]
ldr ip, [r7, #0x30]
smlal r3, r2, r0, r1
mov r1, r3, lsr #0xc
orr r1, r1, r2, lsl #20
add r1, ip, r1
str r1, [r6, #0x30]
ldr r1, [r7, #0x14]
ldr r2, [r7, #4]
smull ip, r3, r4, r1
smlal ip, r3, r5, r2
ldr r1, [r7, #0x24]
ldr r2, [r7, #0x34]
smlal ip, r3, r0, r1
mov r1, ip, lsr #0xc
orr r1, r1, r3, lsl #20
add r1, r2, r1
str r1, [r6, #0x34]
ldr r1, [r7, #0x18]
ldr r2, [r7, #8]
smull ip, r3, r4, r1
smlal ip, r3, r5, r2
ldr r1, [r7, #0x28]
ldr r2, [r7, #0x38]
smlal ip, r3, r0, r1
mov r1, ip, lsr #0xc
orr r1, r1, r3, lsl #20
add r1, r2, r1
str r1, [r6, #0x38]
ldr r1, [r7, #0x1c]
ldr r2, [r7, #0xc]
smull ip, r3, r4, r1
smlal ip, r3, r5, r2
ldr r1, [r7, #0x2c]
ldr r2, [r7, #0x3c]
smlal ip, r3, r0, r1
mov r0, ip, lsr #0xc
orr r0, r0, r3, lsl #20
add r0, r2, r0
str r0, [r6, #0x3c]
ldmia sp!, {r3, r4, r5, r6, r7, pc}
arm_func_end MTX_TransApply44
thumb_func_start MTX_RotX44_
MTX_RotX44_: ; 0x020CC17C
str r2, [r0, #0x14]
str r2, [r0, #0x28]
str r1, [r0, #0x18]
neg r1, r1
str r1, [r0, #0x24]
mov r1, #1
mov r2, #0
lsl r1, r1, #0xc
mov r3, #0
stmia r0!, {r1, r2, r3}
stmia r0!, {r2, r3}
add r0, #8
stmia r0!, {r2, r3}
add r0, #8
stmia r0!, {r2, r3}
stmia r0!, {r2, r3}
str r1, [r0]
bx lr
thumb_func_end MTX_RotX44_
thumb_func_start MTX_RotY44_
MTX_RotY44_: ; 0x020CC1A0
str r2, [r0]
str r2, [r0, #0x28]
str r1, [r0, #0x20]
neg r1, r1
str r1, [r0, #8]
mov r3, #1
mov r1, #0
lsl r3, r3, #0xc
mov r2, #0
str r2, [r0, #4]
add r0, #0xc
stmia r0!, {r1, r2, r3}
stmia r0!, {r1, r2}
str r2, [r0, #4]
add r0, #0xc
stmia r0!, {r1, r2}
stmia r0!, {r1, r2, r3}
bx lr
thumb_func_end MTX_RotY44_
thumb_func_start MTX_RotZ44_
MTX_RotZ44_: ; 0x020CC1C4
str r2, [r0]
str r2, [r0, #0x14]
str r1, [r0, #4]
neg r1, r1
str r1, [r0, #0x10]
mov r3, #1
mov r1, #0
lsl r3, r3, #0xc
mov r2, #0
add r0, #8
stmia r0!, {r1, r2}
add r0, #8
stmia r0!, {r1, r2}
stmia r0!, {r1, r2, r3}
stmia r0!, {r1, r2}
stmia r0!, {r1, r2, r3}
bx lr
.align 2, 0
thumb_func_end MTX_RotZ44_
arm_func_start MTX_Concat44
MTX_Concat44: ; 0x020CC1E8
stmdb sp!, {r3, r4, r5, r6, r7, r8, sb, sl, fp, lr}
sub sp, sp, #0xe8
cmp r2, r1
addeq sl, sp, #0xa8
str r2, [sp]
movne sl, r2
ldr r4, [r0, #4]
ldr r2, [r1, #0x10]
ldr r5, [r0]
smull r8, r7, r4, r2
ldr r2, [r1]
ldr r3, [r0, #8]
smlal r8, r7, r5, r2
ldr r6, [r1, #0x20]
ldr r2, [r0, #0xc]
smlal r8, r7, r3, r6
ldr r6, [r1, #0x30]
smlal r8, r7, r2, r6
mov r6, r8, lsr #0xc
orr r6, r6, r7, lsl #20
str r6, [sl]
ldr r6, [r1, #0x14]
ldr r7, [r1, #4]
smull sb, r8, r4, r6
smlal sb, r8, r5, r7
ldr r6, [r1, #0x24]
ldr r7, [r1, #0x34]
smlal sb, r8, r3, r6
smlal sb, r8, r2, r7
mov r6, sb, lsr #0xc
orr r6, r6, r8, lsl #20
str r6, [sl, #4]
ldr r6, [r1, #0x1c]
ldr r7, [r1, #0xc]
smull sb, r8, r4, r6
smlal sb, r8, r5, r7
ldr r6, [r1, #0x2c]
ldr r7, [r1, #0x3c]
smlal sb, r8, r3, r6
smlal sb, r8, r2, r7
mov r6, sb, lsr #0xc
orr r6, r6, r8, lsl #20
str r6, [sl, #0xc]
ldr fp, [r1, #0x18]
ldr ip, [r1, #8]
smull r7, r6, r4, fp
ldr r8, [r1, #0x38]
smlal r7, r6, r5, ip
ldr sb, [r1, #0x28]
mov lr, r8, asr #0x1f
smlal r7, r6, r3, sb
smlal r7, r6, r2, r8
mov r2, r7, lsr #0xc
orr r2, r2, r6, lsl #20
str r2, [sl, #8]
mov r2, fp, asr #0x1f
str r2, [sp, #4]
mov r2, ip, asr #0x1f
str r2, [sp, #8]
mov r2, sb, asr #0x1f
str r2, [sp, #0x8c]
ldr r6, [r0, #0x14]
ldr r7, [r0, #0x10]
mov r2, r6, asr #0x1f
str r2, [sp, #0xc]
mov r2, r7, asr #0x1f
ldr r5, [r0, #0x18]
str r2, [sp, #0x10]
mov r2, r5, asr #0x1f
ldr r4, [r0, #0x1c]
str r2, [sp, #0x14]
mov r2, r4, asr #0x1f
str r2, [sp, #0x18]
umull r2, r3, r4, r8
str r2, [sp, #0x1c]
mla r3, r4, lr, r3
ldr r2, [sp, #0x18]
mla r3, r2, r8, r3
umull r8, r2, r5, sb
str r8, [sp, #0x20]
ldr r8, [sp, #0x8c]
mla r2, r5, r8, r2
ldr r8, [sp, #0x14]
mla r2, r8, sb, r2
ldr r8, [sp, #8]
umull lr, sb, r7, ip
mla sb, r7, r8, sb
ldr r8, [sp, #0x10]
mla sb, r8, ip, sb
umull ip, r8, r6, fp
adds lr, lr, ip
ldr ip, [sp, #4]
mla r8, r6, ip, r8
ldr ip, [sp, #0xc]
mla r8, ip, fp, r8
adc sb, sb, r8
ldr r8, [sp, #0x20]
adds fp, r8, lr
adc r8, r2, sb
ldr r2, [sp, #0x1c]
adds sb, r2, fp
adc r2, r3, r8
mov r3, sb, lsr #0xc
orr r3, r3, r2, lsl #20
str r3, [sl, #0x18]
ldr r2, [r1, #0x14]
ldr r3, [r1, #4]
smull fp, r2, r6, r2
smlal fp, r2, r7, r3
ldr r8, [r1, #0x24]
ldr sb, [r1, #0x34]
smlal fp, r2, r5, r8
smlal fp, r2, r4, sb
mov r3, fp, lsr #0xc
orr r3, r3, r2, lsl #20
str r3, [sl, #0x14]
ldr r2, [r1, #0x1c]
ldr r3, [r1, #0xc]
smull fp, r2, r6, r2
smlal fp, r2, r7, r3
ldr r8, [r1, #0x2c]
ldr sb, [r1, #0x3c]
smlal fp, r2, r5, r8
smlal fp, r2, r4, sb
mov r3, fp, lsr #0xc
orr r3, r3, r2, lsl #20
str r3, [sl, #0x1c]
ldr sb, [r1, #0x10]
ldr fp, [r1, #0x30]
smull ip, r8, r6, sb
ldr r3, [r1]
ldr r2, [r1, #0x20]
smlal ip, r8, r7, r3
smlal ip, r8, r5, r2
smlal ip, r8, r4, fp
mov r4, ip, lsr #0xc
orr r4, r4, r8, lsl #20
str r4, [sl, #0x10]
mov r4, r3, asr #0x1f
mov r5, sb, asr #0x1f
str r4, [sp, #0x28]
mov r4, r2, asr #0x1f
str r5, [sp, #0x24]
ldr r7, [r0, #0x24]
str r4, [sp, #0x2c]
mov r4, r7, asr #0x1f
ldr r8, [r0, #0x20]
ldr r6, [r0, #0x28]
ldr r5, [r0, #0x2c]
mov lr, fp, asr #0x1f
str r4, [sp, #0x90]
mov r4, r8, asr #0x1f
str r4, [sp, #0x30]
mov r4, r6, asr #0x1f
str r4, [sp, #0x34]
mov r4, r5, asr #0x1f
str r4, [sp, #0x38]
umull ip, r4, r5, fp
str ip, [sp, #0x3c]
mla r4, r5, lr, r4
ldr ip, [sp, #0x38]
mla r4, ip, fp, r4
umull fp, lr, r6, r2
str fp, [sp, #0x40]
ldr fp, [sp, #0x2c]
mla lr, r6, fp, lr
ldr fp, [sp, #0x34]
mla lr, fp, r2, lr
umull r2, ip, r8, r3
str r2, [sp, #0x44]
ldr r2, [sp, #0x28]
mla ip, r8, r2, ip
ldr r2, [sp, #0x30]
mla ip, r2, r3, ip
umull r3, fp, r7, sb
ldr r2, [sp, #0x44]
adds r3, r2, r3
ldr r2, [sp, #0x24]
mla fp, r7, r2, fp
ldr r2, [sp, #0x90]
mla fp, r2, sb, fp
ldr r2, [sp, #0x40]
adc sb, ip, fp
adds fp, r2, r3
ldr r2, [sp, #0x3c]
adc r3, lr, sb
adds sb, r2, fp
adc r2, r4, r3
mov r3, sb, lsr #0xc
orr r3, r3, r2, lsl #20
str r3, [sl, #0x20]
ldr r2, [r1, #0x14]
ldr lr, [r1, #4]
str r2, [sp, #0x48]
ldr r3, [sp, #0x48]
mov r2, r2, asr #0x1f
umull ip, fp, r7, r3
mla fp, r7, r2, fp
ldr r2, [sp, #0x90]
ldr r4, [r1, #0x24]
mla fp, r2, r3, fp
smlal ip, fp, r8, lr
smlal ip, fp, r6, r4
ldr sb, [r1, #0x34]
smlal ip, fp, r5, sb
mov r2, ip, lsr #0xc
orr r2, r2, fp, lsl #20
str r2, [sl, #0x24]
ldr r2, [r1, #0x1c]
ldr lr, [r1, #0xc]
str r2, [sp, #0x4c]
ldr r3, [sp, #0x4c]
mov r2, r2, asr #0x1f
umull ip, fp, r7, r3
mla fp, r7, r2, fp
ldr r2, [sp, #0x90]
ldr r4, [r1, #0x2c]
mla fp, r2, r3, fp
smlal ip, fp, r8, lr
smlal ip, fp, r6, r4
ldr sb, [r1, #0x3c]
smlal ip, fp, r5, sb
mov r2, ip, lsr #0xc
orr r2, r2, fp, lsl #20
str r2, [sl, #0x2c]
ldr fp, [r1, #0x18]
ldr r3, [r1, #0x38]
mov ip, fp, asr #0x1f
str r3, [sp, #0x50]
umull r4, r3, r7, fp
mla r3, r7, ip, r3
ldr r7, [sp, #0x90]
ldr r2, [r1, #8]
mla r3, r7, fp, r3
smlal r4, r3, r8, r2
ldr sb, [r1, #0x28]
smlal r4, r3, r6, sb
ldr r6, [sp, #0x50]
smlal r4, r3, r5, r6
mov r4, r4, lsr #0xc
orr r4, r4, r3, lsl #20
str r4, [sl, #0x28]
ldr r4, [r0, #0x34]
ldr r3, [r0, #0x30]
smull r6, r5, r4, fp
smlal r6, r5, r3, r2
mov r2, r4, asr #0x1f
str r2, [sp, #0x54]
mov r2, r3, asr #0x1f
str r2, [sp, #0x58]
ldr r2, [r0, #0x38]
ldr ip, [r0, #0x3c]
smlal r6, r5, r2, sb
ldr r0, [sp, #0x50]
smlal r6, r5, ip, r0
mov r0, r6, lsr #0xc
orr r0, r0, r5, lsl #20
str r0, [sl, #0x38]
mov r0, r2, asr #0x1f
str r0, [sp, #0x5c]
mov r0, ip, asr #0x1f
str r0, [sp, #0x60]
ldr r8, [r1, #0x24]
ldr r7, [r1, #4]
mov r0, r8, asr #0x1f
ldr sb, [r1, #0x34]
str r0, [sp, #0x98]
mov r0, r7, asr #0x1f
ldr r6, [r1, #0x14]
str r0, [sp, #0x6c]
mov r0, r6, asr #0x1f
str r0, [sp, #0x70]
umull r0, fp, ip, sb
mov lr, sb, asr #0x1f
str r0, [sp, #0x64]
mla fp, ip, lr, fp
ldr r0, [sp, #0x60]
add r5, sp, #0xa8
mla fp, r0, sb, fp
umull r0, sb, r2, r8
str r0, [sp, #0x94]
ldr r0, [sp, #0x98]
mla sb, r2, r0, sb
ldr r0, [sp, #0x5c]
mla sb, r0, r8, sb
umull r0, r8, r3, r7
str r0, [sp, #0x68]
ldr r0, [sp, #0x6c]
mla r8, r3, r0, r8
ldr r0, [sp, #0x58]
mla r8, r0, r7, r8
umull r7, lr, r4, r6
ldr r0, [sp, #0x68]
adds r7, r0, r7
ldr r0, [sp, #0x70]
mla lr, r4, r0, lr
ldr r0, [sp, #0x54]
mla lr, r0, r6, lr
ldr r0, [sp, #0x94]
adc r6, r8, lr
adds r7, r0, r7
ldr r0, [sp, #0x64]
adc r6, sb, r6
adds r7, r0, r7
adc r0, fp, r6
mov r6, r7, lsr #0xc
orr r6, r6, r0, lsl #20
str r6, [sl, #0x34]
ldr r8, [r1, #0x20]
ldr sb, [r1, #0x30]
mov r0, r8, asr #0x1f
ldr r7, [r1]
str r0, [sp, #0xa0]
mov r0, r7, asr #0x1f
ldr r6, [r1, #0x10]
str r0, [sp, #0x7c]
mov r0, r6, asr #0x1f
str r0, [sp, #0x80]
umull r0, fp, ip, sb
mov lr, sb, asr #0x1f
str r0, [sp, #0x74]
mla fp, ip, lr, fp
ldr r0, [sp, #0x60]
mla fp, r0, sb, fp
umull r0, sb, r2, r8
str r0, [sp, #0x9c]
ldr r0, [sp, #0xa0]
mla sb, r2, r0, sb
ldr r0, [sp, #0x5c]
mla sb, r0, r8, sb
umull r0, r8, r3, r7
str r0, [sp, #0x78]
ldr r0, [sp, #0x7c]
mla r8, r3, r0, r8
ldr r0, [sp, #0x58]
mla r8, r0, r7, r8
umull r7, lr, r4, r6
ldr r0, [sp, #0x78]
adds r7, r0, r7
ldr r0, [sp, #0x80]
mla lr, r4, r0, lr
ldr r0, [sp, #0x54]
mla lr, r0, r6, lr
ldr r0, [sp, #0x9c]
adc r6, r8, lr
adds r7, r0, r7
ldr r0, [sp, #0x74]
adc r6, sb, r6
adds r7, r0, r7
adc r0, fp, r6
mov r6, r7, lsr #0xc
orr r6, r6, r0, lsl #20
str r6, [sl, #0x30]
ldr r8, [r1, #0x3c]
ldr r6, [r1, #0xc]
mov r0, r8, asr #0x1f
str r0, [sp, #0x84]
ldr r7, [r1, #0x2c]
ldr fp, [sp, #0x84]
mov r0, r7, asr #0x1f
str r0, [sp, #0x88]
ldr r0, [r1, #0x1c]
mov lr, r6, asr #0x1f
mov r1, r0, asr #0x1f
str r1, [sp, #0xa4]
umull sb, r1, ip, r8
mla r1, ip, fp, r1
ldr fp, [sp, #0x60]
mla r1, fp, r8, r1
ldr r8, [sp, #0x88]
umull ip, fp, r2, r7
mla fp, r2, r8, fp
ldr r2, [sp, #0x5c]
ldr r8, [sp, #0xa4]
mla fp, r2, r7, fp
umull r7, r2, r3, r6
mla r2, r3, lr, r2
ldr r3, [sp, #0x58]
mla r2, r3, r6, r2
umull r6, r3, r4, r0
mla r3, r4, r8, r3
ldr r4, [sp, #0x54]
mla r3, r4, r0, r3
adds r4, r7, r6
adc r0, r2, r3
adds r2, ip, r4
adc r0, fp, r0
adds r2, sb, r2
adc r0, r1, r0
mov r1, r2, lsr #0xc
orr r1, r1, r0, lsl #20
cmp sl, r5
addne sp, sp, #0xe8
str r1, [sl, #0x3c]
ldmneia sp!, {r3, r4, r5, r6, r7, r8, sb, sl, fp, pc}
ldr r4, [sp]
ldmia r5!, {r0, r1, r2, r3}
stmia r4!, {r0, r1, r2, r3}
str r4, [sp]
ldmia r5!, {r0, r1, r2, r3}
stmia r4!, {r0, r1, r2, r3}
str r4, [sp]
ldmia r5!, {r0, r1, r2, r3}
stmia r4!, {r0, r1, r2, r3}
ldmia r5, {r0, r1, r2, r3}
stmia r4, {r0, r1, r2, r3}
str r4, [sp]
add sp, sp, #0xe8
ldmia sp!, {r3, r4, r5, r6, r7, r8, sb, sl, fp, pc}
arm_func_end MTX_Concat44
arm_func_start MTX_PerspectiveW
MTX_PerspectiveW: ; 0x020CC84C
stmdb sp!, {r4, r5, r6, r7, r8, lr}
mov r4, r0
mov r0, r1
mov r1, r4
mov r8, r2
mov r7, r3
ldr r6, [sp, #0x1c]
ldr r5, [sp, #0x20]
bl FX_Div
ldr r1, [sp, #0x18]
ldr r2, _020CC994 ; =0x04000290
mov r3, #0
str r3, [r2]
mov r3, #0x1000
str r3, [r2, #4]
sub r1, r7, r1
str r1, [r2, #8]
mov r1, #0
mov r4, r0
str r1, [r2, #0xc]
cmp r6, #0x1000
beq _020CC8B4
mul r1, r4, r6
mov r0, r1, asr #0xb
add r0, r1, r0, lsr #20
mov r4, r0, asr #0xc
_020CC8B4:
mov r1, #0
str r1, [r5, #4]
str r1, [r5, #8]
str r1, [r5, #0xc]
str r1, [r5, #0x10]
str r4, [r5, #0x14]
str r1, [r5, #0x18]
str r1, [r5, #0x1c]
str r1, [r5, #0x20]
str r1, [r5, #0x24]
rsb r0, r6, #0
str r0, [r5, #0x2c]
str r1, [r5, #0x30]
str r1, [r5, #0x34]
str r1, [r5, #0x3c]
bl FX_GetDivResultFx64c
ldr r2, _020CC994 ; =0x04000290
mov r3, #0
stmia r2, {r3, r4, r8}
str r3, [r2, #0xc]
cmp r6, #0x1000
beq _020CC930
mov r2, r6, asr #0x1f
umull r4, r3, r0, r6
mla r3, r0, r2, r3
mla r3, r1, r6, r3
mov r0, r4
mov r1, r3
mov r2, #0x1000
mov r3, #0
bl _ll_sdiv
_020CC930:
ldr r4, [sp, #0x18]
mov r2, r7, lsl #1
add r6, r4, r7
mov r3, r6, asr #0x1f
umull r8, r7, r0, r6
mla r7, r0, r3, r7
smull r4, r3, r2, r4
mla r7, r1, r6, r7
adds r2, r8, #0x80000000
adc r7, r7, #0
adds r4, r4, #0x800
adc r2, r3, #0
mov r3, r4, lsr #0xc
orr r3, r3, r2, lsl #20
umull r6, r4, r0, r3
mov r2, r3, asr #0x1f
mla r4, r0, r2, r4
mla r4, r1, r3, r4
adds r0, r6, #0x80000000
str r7, [r5, #0x28]
adc r0, r4, #0
str r0, [r5, #0x38]
bl FX_GetDivResult
str r0, [r5]
ldmia sp!, {r4, r5, r6, r7, r8, pc}
.align 2, 0
_020CC994: .word 0x04000290
arm_func_end MTX_PerspectiveW
arm_func_start MTX_OrthoW
MTX_OrthoW: ; 0x020CC998
stmdb sp!, {r3, r4, r5, r6, r7, r8, sb, sl, fp, lr}
sub sp, sp, #8
str r2, [sp]
mov sl, r0
ldr r0, [sp]
mov r2, r3
sub r0, r2, r0
ldr r8, [sp, #0x3c]
str r3, [sp, #4]
mov fp, r1
ldr sb, [sp, #0x38]
bl FX_InvAsync
mov r0, #0
str r0, [r8, #4]
str r0, [r8, #8]
str r0, [r8, #0xc]
str r0, [r8, #0x10]
str r0, [r8, #0x18]
str r0, [r8, #0x1c]
str r0, [r8, #0x20]
str r0, [r8, #0x24]
str r0, [r8, #0x2c]
str sb, [r8, #0x3c]
bl FX_GetDivResultFx64c
mov r6, r1
mov r4, r0
ldr r1, _020CCB9C ; =0x04000290
mov r3, #0
mov r2, #0x1000
str r3, [r1]
sub r0, sl, fp
str r2, [r1, #4]
str r0, [r1, #8]
mov r0, r3
cmp sb, #0x1000
str r0, [r1, #0xc]
beq _020CCA48
mov r5, sb, asr #0x1f
umull r0, r1, r4, sb
mla r1, r4, r5, r1
mla r1, r6, sb, r1
bl _ll_sdiv
mov r4, r0
mov r6, r1
_020CCA48:
mov r1, r6, lsl #0xd
mov r0, #0x80000000
orr r1, r1, r4, lsr #19
adds r0, r0, r4, lsl #13
adc r0, r1, #0
str r0, [r8]
bl FX_GetDivResultFx64c
mov r5, r0
mov r7, r1
mov r3, #0
ldr ip, _020CCB9C ; =0x04000290
ldr r1, [sp, #0x30]
ldr r0, [sp, #0x34]
str r3, [ip]
mov r2, #0x1000
str r2, [ip, #4]
sub r0, r1, r0
mov lr, r3
str r0, [ip, #8]
cmp sb, #0x1000
str lr, [ip, #0xc]
beq _020CCABC
mov ip, sb, asr #0x1f
umull r0, r1, r5, sb
mla r1, r5, ip, r1
mla r1, r7, sb, r1
bl _ll_sdiv
mov r5, r0
mov r7, r1
_020CCABC:
mov r1, r7, lsl #0xd
mov r0, #0x80000000
orr r1, r1, r5, lsr #19
adds r0, r0, r5, lsl #13
adc r0, r1, #0
str r0, [r8, #0x14]
bl FX_GetDivResultFx64c
cmp sb, #0x1000
beq _020CCB04
mov r2, sb, asr #0x1f
umull ip, r3, r0, sb
mla r3, r0, r2, r3
mla r3, r1, sb, r3
mov r0, ip
mov r1, r3
mov r2, #0x1000
mov r3, #0
bl _ll_sdiv
_020CCB04:
ldr r3, [sp, #4]
ldr r2, [sp]
add r2, r3, r2
rsb ip, r2, #0
add r2, sl, fp
rsb r3, r2, #0
ldr sl, [sp, #0x34]
ldr r2, [sp, #0x30]
mov sb, ip, asr #0x1f
add r2, sl, r2
umull fp, sl, r4, ip
mla sl, r4, sb, sl
mov r4, #0x80000000
mla sl, r6, ip, sl
adds r4, r4, r0, lsl #13
mov sb, r1, lsl #0xd
mov r6, r3, asr #0x1f
umull ip, r4, r5, r3
mla r4, r5, r6, r4
orr sb, sb, r0, lsr #19
mla r4, r7, r3, r4
adc r3, sb, #0
str r3, [r8, #0x28]
adds r3, fp, #0x80000000
adc r7, sl, #0
adds r3, ip, #0x80000000
mov r3, r2, asr #0x1f
umull r6, r5, r0, r2
mla r5, r0, r3, r5
adc r3, r4, #0
str r7, [r8, #0x30]
mla r5, r1, r2, r5
adds r0, r6, #0x80000000
str r3, [r8, #0x34]
adc r0, r5, #0
str r0, [r8, #0x38]
add sp, sp, #8
ldmia sp!, {r3, r4, r5, r6, r7, r8, sb, sl, fp, pc}
.align 2, 0
_020CCB9C: .word 0x04000290
arm_func_end MTX_OrthoW

3
lib/NitroSDK/asm/fx_sincos.s Normal file
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.include "asm/macros.inc"
.include "global.inc"
.text

215
lib/NitroSDK/asm/fx_trig.s Normal file
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.include "asm/macros.inc"
.include "global.inc"
.text
arm_func_start FX_SinFx64c_internal
FX_SinFx64c_internal: ; 0x020CD2FC
stmdb sp!, {r3, r4, r5, r6, r7, r8, sb, lr}
mov lr, #0
cmp r1, #1
cmpeq r0, #0
mov r2, #1
moveq r1, lr
ldreq r0, _020CD3CC ; =0xB504F334
ldmeqia sp!, {r3, r4, r5, r6, r7, r8, sb, pc}
umull r3, ip, r0, r0
mla ip, r0, r1, ip
mla ip, r1, r0, ip
ldr r4, _020CD3D0 ; =0x02317888
ldr r5, _020CD3D4 ; =0x03C2857C
umull r3, r8, ip, r4
umull r3, r7, ip, r5
mla r8, ip, lr, r8
mov r3, lr
mla r7, ip, lr, r7
mla r8, r3, r4, r8
subs sb, lr, r8
mla r7, r3, r5, r7
umull r4, r5, sb, r7
mla r5, sb, r3, r5
sbc r8, r2, #0
mla r5, r8, r7, r5
subs r8, lr, r5
ldr r6, _020CD3D8 ; =0x07E54B84
sbc r7, r2, #0
umull r4, r5, ip, r6
mla r5, ip, lr, r5
mla r5, r3, r6, r5
umull r4, r6, r8, r5
mla r6, r8, r3, r6
mla r6, r7, r5, r6
subs r8, lr, r6
sbc r7, r2, #0
ldr r2, _020CD3DC ; =0x14ABBCE6
ldr r6, _020CD3E0 ; =0xC90FDAA2
umull r4, r5, ip, r2
mla r5, ip, lr, r5
mla r5, r3, r2, r5
umull r2, r4, r8, r5
mla r4, r8, r3, r4
mla r4, r7, r5, r4
subs r6, r6, r4
umull r2, r4, r6, r0
mla r4, r6, r1, r4
sbc r5, lr, #0
mla r4, r5, r0, r4
mov r0, r4
mov r1, r3
ldmia sp!, {r3, r4, r5, r6, r7, r8, sb, pc}
.align 2, 0
_020CD3CC: .word 0xB504F334
_020CD3D0: .word 0x02317888
_020CD3D4: .word 0x03C2857C
_020CD3D8: .word 0x07E54B84
_020CD3DC: .word 0x14ABBCE6
_020CD3E0: .word 0xC90FDAA2
arm_func_end FX_SinFx64c_internal
arm_func_start FX_CosFx64c_internal
FX_CosFx64c_internal: ; 0x020CD3E4
stmdb sp!, {r4, r5, r6, r7, r8, lr}
mov ip, #0
cmp r1, #1
cmpeq r0, #0
mov r2, #1
moveq r1, ip
ldreq r0, _020CD49C ; =0xB504F334
ldmeqia sp!, {r4, r5, r6, r7, r8, pc}
umull r4, r3, r0, r0
mla r3, r0, r1, r3
mla r3, r1, r0, r3
ldr r1, _020CD4A0 ; =0x02D1E41D
ldr lr, _020CD4A4 ; =0x054387AD
umull r0, r6, r3, r1
umull r0, r5, r3, lr
mla r6, r3, ip, r6
mov r0, ip
mla r5, r3, ip, r5
mla r6, r0, r1, r6
subs r8, ip, r6
mla r5, r0, lr, r5
umull r1, r6, r8, r5
ldr r4, _020CD4A8 ; =0x0D28D331
mla r6, r8, r0, r6
umull r1, lr, r3, r4
mla lr, r3, ip, lr
sbc r7, r2, #0
mla r6, r7, r5, r6
subs r6, ip, r6
mla lr, r0, r4, lr
umull r1, r4, r6, lr
mla r4, r6, r0, r4
sbc r5, r2, #0
mla r4, r5, lr, r4
subs r6, ip, r4
ldr r1, _020CD4AC ; =0x4EF4F327
sbc r5, r2, #0
umull r4, lr, r3, r1
mla lr, r3, ip, lr
mla lr, r0, r1, lr
umull r1, r3, r6, lr
mla r3, r6, r0, r3
mla r3, r5, lr, r3
subs r0, ip, r3
sbc r1, r2, #0
ldmia sp!, {r4, r5, r6, r7, r8, pc}
.align 2, 0
_020CD49C: .word 0xB504F334
_020CD4A0: .word 0x02D1E41D
_020CD4A4: .word 0x054387AD
_020CD4A8: .word 0x0D28D331
_020CD4AC: .word 0x4EF4F327
arm_func_end FX_CosFx64c_internal
arm_func_start FX_SinFx64c
FX_SinFx64c: ; 0x020CD4B0
stmdb sp!, {r4, lr}
cmp r0, #0
bge _020CD4D0
rsb r0, r0, #0
bl FX_SinFx64c
rsbs r0, r0, #0
rsc r1, r1, #0
ldmia sp!, {r4, pc}
_020CD4D0:
ldr r1, _020CD544 ; =0x45F306DD
mov r2, #1
umull ip, lr, r0, r1
mla lr, r0, r2, lr
mov r0, r0, asr #0x1f
mla lr, r0, r1, lr
mov r3, #0
mov ip, ip, lsr #0xc
mov r4, lr, asr #0xc
orr ip, ip, lr, lsl #20
sub r0, r3, #1
tst r4, #1
and r1, r3, lr, asr #12
and r0, ip, r0
beq _020CD514
subs r0, r3, r0
sbc r1, r2, r1
_020CD514:
add r2, r4, #1
tst r2, #2
beq _020CD528
bl FX_CosFx64c_internal
b _020CD52C
_020CD528:
bl FX_SinFx64c_internal
_020CD52C:
and r2, r4, #7
cmp r2, #3
ldmleia sp!, {r4, pc}
rsbs r0, r0, #0
rsc r1, r1, #0
ldmia sp!, {r4, pc}
.align 2, 0
_020CD544: .word 0x45F306DD
arm_func_end FX_SinFx64c
arm_func_start FX_CosFx64c
FX_CosFx64c: ; 0x020CD548
stmdb sp!, {r4, lr}
cmp r0, #0
bge _020CD560
rsb r0, r0, #0
bl FX_CosFx64c
ldmia sp!, {r4, pc}
_020CD560:
ldr r1, _020CD5D8 ; =0x45F306DD
mov r2, #1
umull ip, lr, r0, r1
mla lr, r0, r2, lr
mov r0, r0, asr #0x1f
mla lr, r0, r1, lr
mov r3, #0
mov ip, ip, lsr #0xc
mov r4, lr, asr #0xc
orr ip, ip, lr, lsl #20
sub r0, r3, #1
tst r4, #1
and r1, r3, lr, asr #12
and r0, ip, r0
beq _020CD5A4
subs r0, r3, r0
sbc r1, r2, r1
_020CD5A4:
add r2, r4, #1
tst r2, #2
beq _020CD5B8
bl FX_SinFx64c_internal
b _020CD5BC
_020CD5B8:
bl FX_CosFx64c_internal
_020CD5BC:
add r2, r4, #2
and r2, r2, #7
cmp r2, #3
ldmleia sp!, {r4, pc}
rsbs r0, r0, #0
rsc r1, r1, #0
ldmia sp!, {r4, pc}
.align 2, 0
_020CD5D8: .word 0x45F306DD
arm_func_end FX_CosFx64c

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lib/NitroSDK/asm/fx_vec.s Normal file
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.include "asm/macros.inc"
.include "global.inc"
.text
arm_func_start VEC_Add
VEC_Add: ; 0x020CCD78
ldr ip, [r0]
ldr r3, [r1]
add r3, ip, r3
str r3, [r2]
ldr ip, [r0, #4]
ldr r3, [r1, #4]
add r3, ip, r3
str r3, [r2, #4]
ldr r3, [r0, #8]
ldr r0, [r1, #8]
add r0, r3, r0
str r0, [r2, #8]
bx lr
arm_func_end VEC_Add
arm_func_start VEC_Subtract
VEC_Subtract: ; 0x020CCDAC
ldr ip, [r0]
ldr r3, [r1]
sub r3, ip, r3
str r3, [r2]
ldr ip, [r0, #4]
ldr r3, [r1, #4]
sub r3, ip, r3
str r3, [r2, #4]
ldr r3, [r0, #8]
ldr r0, [r1, #8]
sub r0, r3, r0
str r0, [r2, #8]
bx lr
arm_func_end VEC_Subtract
arm_func_start VEC_Fx16Add
VEC_Fx16Add: ; 0x020CCDE0
ldrsh ip, [r0]
ldrsh r3, [r1]
add r3, ip, r3
strh r3, [r2]
ldrsh ip, [r0, #2]
ldrsh r3, [r1, #2]
add r3, ip, r3
strh r3, [r2, #2]
ldrsh r3, [r0, #4]
ldrsh r0, [r1, #4]
add r0, r3, r0
strh r0, [r2, #4]
bx lr
arm_func_end VEC_Fx16Add
arm_func_start VEC_DotProduct
VEC_DotProduct: ; 0x020CCE14
stmdb sp!, {r4, lr}
ldr r3, [r0, #4]
ldr r2, [r1, #4]
ldr ip, [r0]
smull r4, lr, r3, r2
ldr r2, [r1]
ldr r3, [r0, #8]
smlal r4, lr, ip, r2
ldr r0, [r1, #8]
smlal r4, lr, r3, r0
adds r0, r4, #0x800
adc r1, lr, #0
mov r0, r0, lsr #0xc
orr r0, r0, r1, lsl #20
ldmia sp!, {r4, pc}
arm_func_end VEC_DotProduct
arm_func_start VEC_Fx16DotProduct
VEC_Fx16DotProduct: ; 0x020CCE50
stmdb sp!, {r3, r4, r5, lr}
ldrsh lr, [r0, #2]
ldrsh ip, [r1, #2]
ldrsh r3, [r0, #4]
ldrsh r2, [r1, #4]
ldrsh r5, [r0]
ldrsh r4, [r1]
smulbb r1, lr, ip
smulbb r0, r3, r2
add r0, r0, #0x800
smlabb r1, r5, r4, r1
adds r2, r1, r0
mov r0, r0, asr #0x1f
adc r1, r0, r1, asr #31
mov r0, r2, lsr #0xc
orr r0, r0, r1, lsl #20
ldmia sp!, {r3, r4, r5, pc}
arm_func_end VEC_Fx16DotProduct
arm_func_start VEC_CrossProduct
VEC_CrossProduct: ; 0x020CCE94
stmdb sp!, {r4, r5, r6, r7, r8, lr}
ldmia r0, {r5, lr}
ldr r6, [r1, #8]
ldr r0, [r0, #8]
ldmia r1, {r4, ip}
smull r8, r7, lr, r6
smull r3, r1, r0, ip
subs r3, r8, r3
sbc r1, r7, r1
adds r3, r3, #0x800
smull r8, r7, r0, r4
smull r6, r0, r5, r6
adc r1, r1, #0
subs r6, r8, r6
mov r3, r3, lsr #0xc
orr r3, r3, r1, lsl #20
sbc r7, r7, r0
adds r0, r6, #0x800
smull ip, r6, r5, ip
adc r5, r7, #0
smull r4, r1, lr, r4
mov r7, r0, lsr #0xc
subs r4, ip, r4
sbc r0, r6, r1
adds r1, r4, #0x800
str r3, [r2]
orr r7, r7, r5, lsl #20
adc r0, r0, #0
mov r1, r1, lsr #0xc
str r7, [r2, #4]
orr r1, r1, r0, lsl #20
str r1, [r2, #8]
ldmia sp!, {r4, r5, r6, r7, r8, pc}
arm_func_end VEC_CrossProduct
arm_func_start VEC_Fx16CrossProduct
VEC_Fx16CrossProduct: ; 0x020CCF18
stmdb sp!, {r4, r5, r6, lr}
ldrsh r4, [r1, #4]
ldrsh ip, [r0, #2]
ldrsh lr, [r0]
ldrsh r3, [r1, #2]
ldrsh r6, [r0, #4]
ldrsh r1, [r1]
smulbb r5, ip, r4
smulbb r0, r6, r3
sub r0, r5, r0
add r0, r0, #0x800
mov r0, r0, asr #0xc
smulbb r5, r6, r1
smulbb r4, lr, r4
sub r4, r5, r4
add r4, r4, #0x800
smulbb r3, lr, r3
smulbb r1, ip, r1
sub r1, r3, r1
add r1, r1, #0x800
strh r0, [r2]
mov r0, r4, asr #0xc
strh r0, [r2, #2]
mov r0, r1, asr #0xc
strh r0, [r2, #4]
ldmia sp!, {r4, r5, r6, pc}
arm_func_end VEC_Fx16CrossProduct
arm_func_start VEC_Mag
VEC_Mag: ; 0x020CCF80
ldr r1, [r0, #4]
ldr r2, [r0]
smull ip, r3, r1, r1
smlal ip, r3, r2, r2
ldr r0, [r0, #8]
ldr r2, _020CCFD8 ; =0x040002B0
smlal ip, r3, r0, r0
mov r1, #1
mov r0, r3, lsl #2
strh r1, [r2]
mov r1, ip, lsl #2
str r1, [r2, #8]
orr r0, r0, ip, lsr #30
str r0, [r2, #0xc]
_020CCFB8:
ldrh r0, [r2]
tst r0, #0x8000
bne _020CCFB8
ldr r0, _020CCFDC ; =0x040002B4
ldr r0, [r0]
add r0, r0, #1
mov r0, r0, asr #1
bx lr
.align 2, 0
_020CCFD8: .word 0x040002B0
_020CCFDC: .word 0x040002B4
arm_func_end VEC_Mag
arm_func_start VEC_Normalize
VEC_Normalize: ; 0x020CCFE0
stmdb sp!, {r3, r4, r5, r6, r7, r8, sb, lr}
ldr r2, [r0, #4]
ldr r3, [r0]
smull r6, r5, r2, r2
smlal r6, r5, r3, r3
ldr r2, [r0, #8]
ldr r4, _020CD0EC ; =0x04000280
smlal r6, r5, r2, r2
mov r3, #2
strh r3, [r4]
mov r3, #0
str r3, [r4, #0x10]
mov r3, #0x1000000
str r3, [r4, #0x14]
str r6, [r4, #0x18]
mov r2, r5, lsl #2
str r5, [r4, #0x1c]
mov r3, #1
strh r3, [r4, #0x30]
mov r3, r6, lsl #2
str r3, [r4, #0x38]
orr r2, r2, r6, lsr #30
str r2, [r4, #0x3c]
_020CD03C:
ldrh r2, [r4, #0x30]
tst r2, #0x8000
bne _020CD03C
ldr r2, _020CD0F0 ; =0x040002B4
ldr ip, [r2]
sub r3, r2, #0x34
_020CD054:
ldrh r2, [r3]
tst r2, #0x8000
bne _020CD054
ldr sb, _020CD0F4 ; =0x040002A0
ldr r5, [r0]
ldr r8, [sb]
mov r7, ip, asr #0x1f
umull r3, r2, r8, ip
umull r6, lr, r3, r5
mov r4, r5, asr #0x1f
mla r2, r8, r7, r2
ldr r7, [sb, #4]
mla lr, r3, r4, lr
mla r2, r7, ip, r2
mla lr, r2, r5, lr
adds r4, r6, #0
adc r4, lr, #0x1000
mov r4, r4, asr #0xd
str r4, [r1]
ldr ip, [r0, #4]
umull r5, lr, r3, ip
mov r4, ip, asr #0x1f
mla lr, r3, r4, lr
mla lr, r2, ip, lr
adds r4, r5, #0
adc r4, lr, #0x1000
mov r4, r4, asr #0xd
str r4, [r1, #4]
ldr ip, [r0, #8]
umull r4, lr, r3, ip
mov r0, ip, asr #0x1f
mla lr, r3, r0, lr
mla lr, r2, ip, lr
adds r0, r4, #0
adc r0, lr, #0x1000
mov r0, r0, asr #0xd
str r0, [r1, #8]
ldmia sp!, {r3, r4, r5, r6, r7, r8, sb, pc}
.align 2, 0
_020CD0EC: .word 0x04000280
_020CD0F0: .word 0x040002B4
_020CD0F4: .word 0x040002A0
arm_func_end VEC_Normalize
arm_func_start VEC_Fx16Normalize
VEC_Fx16Normalize: ; 0x020CD0F8
stmdb sp!, {r3, r4, r5, r6, r7, r8, sb, lr}
ldrsh r5, [r0]
ldrsh r2, [r0, #2]
ldrsh r3, [r0, #4]
ldr r4, _020CD218 ; =0x04000280
smulbb r6, r2, r2
smulbb r8, r5, r5
mov r2, #2
strh r2, [r4]
mov r2, #0
str r2, [r4, #0x10]
mov r2, #0x1000000
smulbb r3, r3, r3
mov r5, r6, asr #0x1f
adds r7, r8, r6
adc r6, r5, r8, asr #31
adds r5, r7, r3
str r2, [r4, #0x14]
adc r3, r6, r3, asr #31
str r5, [r4, #0x18]
mov r2, r3, lsl #2
str r3, [r4, #0x1c]
mov r3, #1
strh r3, [r4, #0x30]
mov r3, r5, lsl #2
str r3, [r4, #0x38]
orr r2, r2, r5, lsr #30
str r2, [r4, #0x3c]
_020CD168:
ldrh r2, [r4, #0x30]
tst r2, #0x8000
bne _020CD168
ldr r2, _020CD21C ; =0x040002B4
ldr ip, [r2]
sub r3, r2, #0x34
_020CD180:
ldrh r2, [r3]
tst r2, #0x8000
bne _020CD180
ldr sb, _020CD220 ; =0x040002A0
ldrsh r5, [r0]
ldr r8, [sb]
mov r7, ip, asr #0x1f
umull r3, r2, r8, ip
umull r6, lr, r3, r5
mov r4, r5, asr #0x1f
mla r2, r8, r7, r2
ldr r7, [sb, #4]
mla lr, r3, r4, lr
mla r2, r7, ip, r2
mla lr, r2, r5, lr
adds r4, r6, #0
adc r4, lr, #0x1000
mov r4, r4, asr #0xd
strh r4, [r1]
ldrsh ip, [r0, #2]
umull r5, lr, r3, ip
mov r4, ip, asr #0x1f
mla lr, r3, r4, lr
mla lr, r2, ip, lr
adds r4, r5, #0
adc r4, lr, #0x1000
mov r4, r4, asr #0xd
strh r4, [r1, #2]
ldrsh ip, [r0, #4]
umull r4, lr, r3, ip
mov r0, ip, asr #0x1f
mla lr, r3, r0, lr
mla lr, r2, ip, lr
adds r0, r4, #0
adc r0, lr, #0x1000
mov r0, r0, asr #0xd
strh r0, [r1, #4]
ldmia sp!, {r3, r4, r5, r6, r7, r8, sb, pc}
.align 2, 0
_020CD218: .word 0x04000280
_020CD21C: .word 0x040002B4
_020CD220: .word 0x040002A0
arm_func_end VEC_Fx16Normalize
arm_func_start VEC_MultAdd
VEC_MultAdd: ; 0x020CD224
stmdb sp!, {r4, lr}
ldr r4, [r1]
ldr lr, [r2]
smull ip, r4, r0, r4
mov ip, ip, lsr #0xc
orr ip, ip, r4, lsl #20
add r4, lr, ip
str r4, [r3]
ldr ip, [r1, #4]
ldr r4, [r2, #4]
smull lr, ip, r0, ip
mov lr, lr, lsr #0xc
orr lr, lr, ip, lsl #20
add r4, r4, lr
str r4, [r3, #4]
ldr r1, [r1, #8]
ldr ip, [r2, #8]
smull r2, r1, r0, r1
mov r0, r2, lsr #0xc
orr r0, r0, r1, lsl #20
add r0, ip, r0
str r0, [r3, #8]
ldmia sp!, {r4, pc}
arm_func_end VEC_MultAdd
arm_func_start VEC_Distance
VEC_Distance: ; 0x020CD280
stmdb sp!, {r4, lr}
ldr r3, [r0, #4]
ldr r2, [r1, #4]
ldr r4, [r0]
sub r2, r3, r2
smull ip, r3, r2, r2
ldr lr, [r1]
ldr r2, [r0, #8]
sub r4, r4, lr
ldr r0, [r1, #8]
smlal ip, r3, r4, r4
sub r0, r2, r0
smlal ip, r3, r0, r0
mov r0, r3, lsl #2
ldr r2, _020CD2F4 ; =0x040002B0
mov r1, #1
strh r1, [r2]
mov r1, ip, lsl #2
str r1, [r2, #8]
orr r0, r0, ip, lsr #30
str r0, [r2, #0xc]
_020CD2D4:
ldrh r0, [r2]
tst r0, #0x8000
bne _020CD2D4
ldr r0, _020CD2F8 ; =0x040002B4
ldr r0, [r0]
add r0, r0, #1
mov r0, r0, asr #1
ldmia sp!, {r4, pc}
.align 2, 0
_020CD2F4: .word 0x040002B0
_020CD2F8: .word 0x040002B4
arm_func_end VEC_Distance

3002
lib/asm/nitro.s
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File diff suppressed because it is too large Load Diff

10
main.lsf
View File

@ -219,6 +219,16 @@ Static main
Object middleware.o
Object sdk.o
Object nnsys.o
Object fx_sincos.o
Object fx_mtx22.o
Object fx_mtx33.o
Object fx_mtx43.o
Object fx_mtx44.o
Object fx_cp.o
Object fx_vec.o
Object fx_trig.o
Object fx_atan.o
Object fx.o
Object nitro.o
Object msl.o
Object bss_temp.o