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mi_dma_hblank, mi_dma_gxcommand, mi_memory

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This commit is contained in:
PikalaxALT 2021-09-29 20:46:32 -04:00
parent 7033e9f777
commit 99ecf23170
8 changed files with 799 additions and 769 deletions
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4
asm/unk_02014A08.s
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@ -124,14 +124,14 @@ sub_02014AB0: ; 0x02014AB0
add r1, r6, #0
add r2, r5, #0
add r3, r4, #0
bl sub_020D43E8
bl MI_HBlankDmaCopy32
pop {r4, r5, r6, pc}
_02014ACA:
mov r0, #0
add r1, r6, #0
add r2, r5, #0
add r3, r4, #0
bl sub_020D4448
bl MI_HBlankDmaCopy16
pop {r4, r5, r6, pc}
thumb_func_end sub_02014AB0

12
global.inc
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@ -29265,14 +29265,14 @@
.public MI_DmaCopy16
.public MI_WaitDma
.public MI_StopDma
.public sub_020D43E8
.public sub_020D4448
.public sub_020D44A8
.public sub_020D46AC
.public MI_HBlankDmaCopy32
.public MI_HBlankDmaCopy16
.public MI_SendGXCommandAsync
.public MI_SendGXCommandAsyncFast
.public MIi_CpuClear16
.public sub_020D4830
.public MIi_CpuSend32
.public MI_Copy64B
.public sub_020D4BD0
.public MI_Zero36B
.public sub_020D4D5C
.public sub_020D5044
.public sub_020D5064

278
lib/NitroSDK/asm/mi_dma_gxcommand.s Normal file
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@ -0,0 +1,278 @@
.include "asm/macros.inc"
.include "global.inc"
.public MIi_CheckAnotherAutoDMA
.public MIi_CheckDma0SourceAddress
.public MIi_DmaSetParams
.public OSi_EnterDmaCallback
.bss
MIiGXDmaParam: ; 0x021E1A20
.space 0x20
.section .itcm,4,1,4
arm_func_start MI_SendGXCommand
MI_SendGXCommand: ; 0x01FF8580
stmdb sp!, {r3, r4, r5, r6, r7, r8, sb, sl, fp, lr}
movs r8, r2
mov sl, r0
mov sb, r1
ldmeqia sp!, {r3, r4, r5, r6, r7, r8, sb, sl, fp, pc}
mov r3, #0
bl MIi_CheckDma0SourceAddress
add r0, sl, sl, lsl #1
add r0, r0, #2
mov r0, r0, lsl #2
add r0, r0, #0xb0
add r6, r0, #0x4000000
_01FF85B0:
ldr r0, [r6]
tst r0, #-0x80000000
bne _01FF85B0
cmp r8, #0
beq _01FF85FC
ldr fp, _01FF860C ; =0x04000400
ldr r4, _01FF8610 ; =0x84400000
mov r5, #0x1d8
_01FF85D0:
cmp r8, #0x1d8
movhi r7, r5
movls r7, r8
mov r0, sl
mov r1, sb
mov r2, fp
orr r3, r4, r7, lsr #2
bl MIi_DmaSetParams
subs r8, r8, r7
add sb, sb, r7
bne _01FF85D0
_01FF85FC:
ldr r0, [r6]
tst r0, #-0x80000000
bne _01FF85FC
ldmia sp!, {r3, r4, r5, r6, r7, r8, sb, sl, fp, pc}
.align 2, 0
_01FF860C: .word 0x04000400
_01FF8610: .word 0x84400000
arm_func_end MI_SendGXCommand
.text
arm_func_start MI_SendGXCommandAsync
MI_SendGXCommandAsync: ; 0x020D44A8
stmdb sp!, {r4, lr}
mov r4, r0
cmp r2, #0
bne _020D44CC
cmp r3, #0
ldmeqia sp!, {r4, pc}
ldr r0, [sp, #8]
blx r3
ldmia sp!, {r4, pc}
_020D44CC:
ldr r0, _020D4594 ; =MIiGXDmaParam
_020D44D0:
ldr ip, [r0]
cmp ip, #0
bne _020D44D0
ldr ip, _020D4598 ; =0x04000600
_020D44E0:
ldr r0, [ip]
and r0, r0, #0x7000000
mov r0, r0, lsr #0x18
tst r0, #2
beq _020D44E0
ldr ip, _020D4594 ; =MIiGXDmaParam
mov r0, #1
str r0, [ip]
str r4, [ip, #4]
str r1, [ip, #8]
str r2, [ip, #0xc]
str r3, [ip, #0x10]
ldr lr, [sp, #8]
mov r0, r4
mov r3, #0
str lr, [ip, #0x14]
bl MIi_CheckDma0SourceAddress
mov r0, r4
bl MI_WaitDma
bl OS_DisableInterrupts
ldr r1, _020D4598 ; =0x04000600
mov r4, r0
ldr r0, [r1]
ldr r1, _020D4594 ; =MIiGXDmaParam
and r0, r0, #0xc0000000
mov r2, r0, lsr #0x1e
mov r0, #0x200000
str r2, [r1, #0x18]
bl OS_GetIrqFunction
ldr r1, _020D4594 ; =MIiGXDmaParam
ldr r2, _020D4598 ; =0x04000600
str r0, [r1, #0x1c]
ldr r0, [r2]
ldr r1, _020D459C ; =MIi_FIFOCallback
bic r0, r0, #0xc0000000
orr r3, r0, #0x40000000
mov r0, #0x200000
str r3, [r2]
bl OS_SetIrqFunction
mov r0, #0x200000
bl OS_EnableIrqMask
bl MIi_FIFOCallback
mov r0, r4
bl OS_RestoreInterrupts
ldmia sp!, {r4, pc}
.align 2, 0
_020D4594: .word MIiGXDmaParam
_020D4598: .word 0x04000600
_020D459C: .word MIi_FIFOCallback
arm_func_end MI_SendGXCommandAsync
arm_func_start MIi_FIFOCallback
MIi_FIFOCallback: ; 0x020D45A0
stmdb sp!, {r3, r4, r5, lr}
ldr r0, _020D463C ; =MIiGXDmaParam
ldr r5, [r0, #0xc]
cmp r5, #0
ldmeqia sp!, {r3, r4, r5, pc}
ldr r0, _020D463C ; =MIiGXDmaParam
cmp r5, #0x1d8
ldr r1, [r0, #0xc]
movhs r5, #0x1d8
ldr r4, [r0, #8]
subs r1, r1, r5
str r1, [r0, #0xc]
add r1, r4, r5
str r1, [r0, #8]
bne _020D4618
ldr r0, [r0, #4]
ldr r1, _020D4640 ; =MIi_DMACallback
mov r2, #0
bl OSi_EnterDmaCallback
ldr r0, _020D463C ; =MIiGXDmaParam
mov r3, #0x3bc00000
rsb r3, r3, #0
ldr r0, [r0, #4]
ldr r2, _020D4644 ; =0x04000400
mov r1, r4
orr r3, r3, r5, lsr #2
bl MIi_DmaSetParams
mov r0, #0x200000
bl OS_ResetRequestIrqMask
ldmia sp!, {r3, r4, r5, pc}
_020D4618:
ldr r3, _020D4648 ; =0x84400000
ldr r0, [r0, #4]
ldr r2, _020D4644 ; =0x04000400
mov r1, r4
orr r3, r3, r5, lsr #2
bl MIi_DmaSetParams
mov r0, #0x200000
bl OS_ResetRequestIrqMask
ldmia sp!, {r3, r4, r5, pc}
.align 2, 0
_020D463C: .word MIiGXDmaParam
_020D4640: .word MIi_DMACallback
_020D4644: .word 0x04000400
_020D4648: .word 0x84400000
arm_func_end MIi_FIFOCallback
arm_func_start MIi_DMACallback
MIi_DMACallback: ; 0x020D464C
stmdb sp!, {r3, lr}
mov r0, #0x200000
bl OS_DisableIrqMask
ldr r2, _020D46A4 ; =0x04000600
ldr r0, _020D46A8 ; =MIiGXDmaParam
ldr r1, [r2]
ldr r3, [r0, #0x18]
bic r1, r1, #0xc0000000
orr r1, r1, r3, lsl #30
str r1, [r2]
ldr r1, [r0, #0x1c]
mov r0, #0x200000
bl OS_SetIrqFunction
ldr r0, _020D46A8 ; =MIiGXDmaParam
mov r1, #0
str r1, [r0]
ldr r1, [r0, #0x10]
ldr r0, [r0, #0x14]
cmp r1, #0
ldmeqia sp!, {r3, pc}
blx r1
ldmia sp!, {r3, pc}
.align 2, 0
_020D46A4: .word 0x04000600
_020D46A8: .word MIiGXDmaParam
arm_func_end MIi_DMACallback
arm_func_start MI_SendGXCommandAsyncFast
MI_SendGXCommandAsyncFast: ; 0x020D46AC
stmdb sp!, {r4, r5, r6, lr}
movs r4, r2
mov r6, r0
mov r5, r1
bne _020D46D4
cmp r3, #0
ldmeqia sp!, {r4, r5, r6, pc}
ldr r0, [sp, #0x10]
blx r3
ldmia sp!, {r4, r5, r6, pc}
_020D46D4:
ldr r0, _020D4758 ; =MIiGXDmaParam
_020D46D8:
ldr r1, [r0]
cmp r1, #0
bne _020D46D8
ldr r2, _020D4758 ; =MIiGXDmaParam
mov r0, #1
str r0, [r2]
str r6, [r2, #4]
ldr ip, [sp, #0x10]
str r3, [r2, #0x10]
mov r0, r6
mov r1, #0x38000000
str ip, [r2, #0x14]
bl MIi_CheckAnotherAutoDMA
mov r0, r6
mov r1, r5
mov r2, r4
mov r3, #0
bl MIi_CheckDma0SourceAddress
mov r0, r6
bl MI_WaitDma
mov r0, r6
ldr r1, _020D475C ; =MIi_DMAFastCallback
mov r2, #0
bl OSi_EnterDmaCallback
mov r0, r6
mov r1, r5
ldr r2, _020D4760 ; =0x04000400
mov r3, #0x3c00000
rsb r3, r3, #0
orr r3, r3, r4, lsr #2
bl MIi_DmaSetParams
ldmia sp!, {r4, r5, r6, pc}
.align 2, 0
_020D4758: .word MIiGXDmaParam
_020D475C: .word MIi_DMAFastCallback
_020D4760: .word 0x04000400
arm_func_end MI_SendGXCommandAsyncFast
arm_func_start MIi_DMAFastCallback
MIi_DMAFastCallback: ; 0x020D4764
stmdb sp!, {r3, lr}
ldr r0, _020D478C ; =MIiGXDmaParam
mov r1, #0
str r1, [r0]
ldr r1, [r0, #0x10]
ldr r0, [r0, #0x14]
cmp r1, #0
ldmeqia sp!, {r3, pc}
blx r1
ldmia sp!, {r3, pc}
.align 2, 0
_020D478C: .word MIiGXDmaParam
arm_func_end MIi_DMAFastCallback

66
lib/NitroSDK/asm/mi_dma_hblank.s Normal file
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@ -0,0 +1,66 @@
.include "asm/macros.inc"
.include "global.inc"
.public MIi_CheckAnotherAutoDMA
.public MIi_CheckDma0SourceAddress
.public MIi_DmaSetParams
.text
arm_func_start MI_HBlankDmaCopy32
MI_HBlankDmaCopy32: ; 0x020D43E8
stmdb sp!, {r3, r4, r5, r6, r7, lr}
mov r6, r1
mov r7, r0
mov r4, r3
mov r1, #0x10000000
mov r5, r2
bl MIi_CheckAnotherAutoDMA
mov r0, r7
mov r1, r6
mov r2, r4
mov r3, #0
bl MIi_CheckDma0SourceAddress
cmp r4, #0
ldmeqia sp!, {r3, r4, r5, r6, r7, pc}
mov r0, r7
bl MI_WaitDma
ldr r3, _020D4444 ; =0x96600000
mov r0, r7
mov r1, r6
mov r2, r5
orr r3, r3, r4, lsr #2
bl MIi_DmaSetParams
ldmia sp!, {r3, r4, r5, r6, r7, pc}
.align 2, 0
_020D4444: .word 0x96600000
arm_func_end MI_HBlankDmaCopy32
arm_func_start MI_HBlankDmaCopy16
MI_HBlankDmaCopy16: ; 0x020D4448
stmdb sp!, {r3, r4, r5, r6, r7, lr}
mov r6, r1
mov r7, r0
mov r4, r3
mov r1, #0x10000000
mov r5, r2
bl MIi_CheckAnotherAutoDMA
mov r0, r7
mov r1, r6
mov r2, r4
mov r3, #0
bl MIi_CheckDma0SourceAddress
cmp r4, #0
ldmeqia sp!, {r3, r4, r5, r6, r7, pc}
mov r0, r7
bl MI_WaitDma
ldr r3, _020D44A4 ; =0x92600000
mov r0, r7
mov r1, r6
mov r2, r5
orr r3, r3, r4, lsr #1
bl MIi_DmaSetParams
ldmia sp!, {r3, r4, r5, r6, r7, pc}
.align 2, 0
_020D44A4: .word 0x92600000
arm_func_end MI_HBlankDmaCopy16

421
lib/NitroSDK/asm/mi_memory.s Normal file
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@ -0,0 +1,421 @@
.include "asm/macros.inc"
.include "global.inc"
.text
arm_func_start MIi_CpuClear16
MIi_CpuClear16: ; 0x020D4790
mov r3, #0
_020D4794:
cmp r3, r2
blt _020D47A0
b _020D47A4
_020D47A0:
strh r0, [r1, r3]
_020D47A4:
blt _020D47AC
b _020D47B0
_020D47AC:
add r3, r3, #2
_020D47B0:
blt _020D4794
bx lr
arm_func_end MIi_CpuClear16
arm_func_start MIi_CpuCopy16
MIi_CpuCopy16: ; 0x020D47B8
mov ip, #0
_020D47BC:
cmp ip, r2
blt _020D47C8
b _020D47CC
_020D47C8:
ldrh r3, [r0, ip]
_020D47CC:
blt _020D47D4
b _020D47D8
_020D47D4:
strh r3, [r1, ip]
_020D47D8:
blt _020D47E0
b _020D47E4
_020D47E0:
add ip, ip, #2
_020D47E4:
blt _020D47BC
bx lr
arm_func_end MIi_CpuCopy16
arm_func_start MIi_CpuClear32
MIi_CpuClear32: ; 0x020D47EC
add ip, r1, r2
_020D47F0:
cmp r1, ip
blt _020D47FC
b _020D4800
_020D47FC:
stmia r1!, {r0}
_020D4800:
blt _020D47F0
bx lr
arm_func_end MIi_CpuClear32
arm_func_start MIi_CpuCopy32
MIi_CpuCopy32: ; 0x020D4808
add ip, r1, r2
_020D480C:
cmp r1, ip
blt _020D4818
b _020D481C
_020D4818:
ldmia r0!, {r2}
_020D481C:
blt _020D4824
b _020D4828
_020D4824:
stmia r1!, {r2}
_020D4828:
blt _020D480C
bx lr
arm_func_end MIi_CpuCopy32
arm_func_start MIi_CpuSend32
MIi_CpuSend32: ; 0x020D4830
add ip, r0, r2
_020D4834:
cmp r0, ip
blt _020D4840
b _020D4844
_020D4840:
ldmia r0!, {r2}
_020D4844:
blt _020D484C
b _020D4850
_020D484C:
str r2, [r1]
_020D4850:
blt _020D4834
bx lr
arm_func_end MIi_CpuSend32
arm_func_start MIi_CpuClearFast
MIi_CpuClearFast: ; 0x020D4858
stmdb sp!, {r4, r5, r6, r7, r8, sb}
add sb, r1, r2
mov ip, r2, lsr #5
add ip, r1, ip, lsl #5
mov r2, r0
mov r3, r2
mov r4, r2
mov r5, r2
mov r6, r2
mov r7, r2
mov r8, r2
_020D4884:
cmp r1, ip
blt _020D4890
b _020D4894
_020D4890:
stmia r1!, {r0, r2, r3, r4, r5, r6, r7, r8}
_020D4894:
blt _020D4884
_020D4898:
cmp r1, sb
blt _020D48A4
b _020D48A8
_020D48A4:
stmia r1!, {r0}
_020D48A8:
blt _020D4898
ldmia sp!, {r4, r5, r6, r7, r8, sb}
bx lr
arm_func_end MIi_CpuClearFast
arm_func_start MIi_CpuCopyFast
MIi_CpuCopyFast: ; 0x020D48B4
stmdb sp!, {r4, r5, r6, r7, r8, sb, sl}
add sl, r1, r2
mov ip, r2, lsr #5
add ip, r1, ip, lsl #5
_020D48C4:
cmp r1, ip
blt _020D48D0
b _020D48D4
_020D48D0:
ldmia r0!, {r2, r3, r4, r5, r6, r7, r8, sb}
_020D48D4:
blt _020D48DC
b _020D48E0
_020D48DC:
stmia r1!, {r2, r3, r4, r5, r6, r7, r8, sb}
_020D48E0:
blt _020D48C4
_020D48E4:
cmp r1, sl
blt _020D48F0
b _020D48F4
_020D48F0:
ldmia r0!, {r2}
_020D48F4:
blt _020D48FC
b _020D4900
_020D48FC:
stmia r1!, {r2}
_020D4900:
blt _020D48E4
ldmia sp!, {r4, r5, r6, r7, r8, sb, sl}
bx lr
arm_func_end MIi_CpuCopyFast
arm_func_start MI_Copy32B
MI_Copy32B: ; 0x020D490C
ldmia r0!, {r2, r3, ip}
stmia r1!, {r2, r3, ip}
ldmia r0!, {r2, r3, ip}
stmia r1!, {r2, r3, ip}
ldmia r0!, {r2, r3}
stmia r1!, {r2, r3}
bx lr
arm_func_end MI_Copy32B
arm_func_start MI_Copy36B
MI_Copy36B: ; 0x020D4928
ldmia r0!, {r2, r3, ip}
stmia r1!, {r2, r3, ip}
ldmia r0!, {r2, r3, ip}
stmia r1!, {r2, r3, ip}
ldmia r0!, {r2, r3, ip}
stmia r1!, {r2, r3, ip}
bx lr
arm_func_end MI_Copy36B
arm_func_start MI_Copy48B
MI_Copy48B: ; 0x020D4944
ldmia r0!, {r2, r3, ip}
stmia r1!, {r2, r3, ip}
ldmia r0!, {r2, r3, ip}
stmia r1!, {r2, r3, ip}
ldmia r0!, {r2, r3, ip}
stmia r1!, {r2, r3, ip}
ldmia r0!, {r2, r3, ip}
stmia r1!, {r2, r3, ip}
bx lr
arm_func_end MI_Copy48B
arm_func_start MI_Copy64B
MI_Copy64B: ; 0x020D4968
ldmia r0!, {r2, r3, ip}
stmia r1!, {r2, r3, ip}
ldmia r0!, {r2, r3, ip}
stmia r1!, {r2, r3, ip}
ldmia r0!, {r2, r3, ip}
stmia r1!, {r2, r3, ip}
ldmia r0!, {r2, r3, ip}
stmia r1!, {r2, r3, ip}
ldmia r0, {r0, r2, r3, ip}
stmia r1!, {r0, r2, r3, ip}
bx lr
arm_func_end MI_Copy64B
arm_func_start MI_CpuFill8
MI_CpuFill8: ; 0x020D4994
cmp r2, #0
beq _020D49A0
b _020D49A4
_020D49A0:
bx lr
_020D49A4:
tst r0, #1
beq _020D49D0
ldrh ip, [r0, #-1]
and ip, ip, #0xff
orr r3, ip, r1, lsl #8
strh r3, [r0, #-1]
add r0, r0, #1
subs r2, r2, #1
beq _020D49CC
b _020D49D0
_020D49CC:
bx lr
_020D49D0:
cmp r2, #2
blo _020D4A28
orr r1, r1, r1, lsl #8
tst r0, #2
beq _020D49F8
strh r1, [r0], #2
subs r2, r2, #2
beq _020D49F4
b _020D49F8
_020D49F4:
bx lr
_020D49F8:
orr r1, r1, r1, lsl #16
bics r3, r2, #3
beq _020D4A18
sub r2, r2, r3
add ip, r3, r0
_020D4A0C:
str r1, [r0], #4
cmp r0, ip
blo _020D4A0C
_020D4A18:
tst r2, #2
bne _020D4A24
b _020D4A28
_020D4A24:
strh r1, [r0], #2
_020D4A28:
tst r2, #1
beq _020D4A34
b _020D4A38
_020D4A34:
bx lr
_020D4A38:
ldrh r3, [r0]
and r3, r3, #0xff00
and r1, r1, #0xff
orr r1, r1, r3
strh r1, [r0]
bx lr
arm_func_end MI_CpuFill8
arm_func_start MI_CpuCopy8
MI_CpuCopy8: ; 0x020D4A50
cmp r2, #0
beq _020D4A5C
b _020D4A60
_020D4A5C:
bx lr
_020D4A60:
tst r1, #1
beq _020D4AB8
ldrh ip, [r1, #-1]
and ip, ip, #0xff
tst r0, #1
bne _020D4A7C
b _020D4A80
_020D4A7C:
ldrh r3, [r0, #-1]
_020D4A80:
bne _020D4A88
b _020D4A8C
_020D4A88:
mov r3, r3, lsr #8
_020D4A8C:
beq _020D4A94
b _020D4A98
_020D4A94:
ldrh r3, [r0]
_020D4A98:
orr r3, ip, r3, lsl #8
strh r3, [r1, #-1]
add r0, r0, #1
add r1, r1, #1
subs r2, r2, #1
beq _020D4AB4
b _020D4AB8
_020D4AB4:
bx lr
_020D4AB8:
eor ip, r1, r0
tst ip, #1
beq _020D4B14
bic r0, r0, #1
ldrh ip, [r0], #2
mov r3, ip, lsr #8
subs r2, r2, #2
blo _020D4AF0
_020D4AD8:
ldrh ip, [r0], #2
orr ip, r3, ip, lsl #8
strh ip, [r1], #2
mov r3, ip, lsr #0x10
subs r2, r2, #2
bhs _020D4AD8
_020D4AF0:
tst r2, #1
beq _020D4AFC
b _020D4B00
_020D4AFC:
bx lr
_020D4B00:
ldrh ip, [r1]
and ip, ip, #0xff00
orr ip, ip, r3
strh ip, [r1]
bx lr
_020D4B14:
tst ip, #2
beq _020D4B40
bics r3, r2, #1
beq _020D4BA4
sub r2, r2, r3
add ip, r3, r1
_020D4B2C:
ldrh r3, [r0], #2
strh r3, [r1], #2
cmp r1, ip
blo _020D4B2C
b _020D4BA4
_020D4B40:
cmp r2, #2
blo _020D4BA4
tst r1, #2
beq _020D4B68
ldrh r3, [r0], #2
strh r3, [r1], #2
subs r2, r2, #2
beq _020D4B64
b _020D4B68
_020D4B64:
bx lr
_020D4B68:
bics r3, r2, #3
beq _020D4B88
sub r2, r2, r3
add ip, r3, r1
_020D4B78:
ldr r3, [r0], #4
str r3, [r1], #4
cmp r1, ip
blo _020D4B78
_020D4B88:
tst r2, #2
bne _020D4B94
b _020D4B98
_020D4B94:
ldrh r3, [r0], #2
_020D4B98:
bne _020D4BA0
b _020D4BA4
_020D4BA0:
strh r3, [r1], #2
_020D4BA4:
tst r2, #1
beq _020D4BB0
b _020D4BB4
_020D4BB0:
bx lr
_020D4BB4:
ldrh r2, [r1]
ldrh r0, [r0]
and r2, r2, #0xff00
and r0, r0, #0xff
orr r0, r2, r0
strh r0, [r1]
bx lr
arm_func_end MI_CpuCopy8
thumb_func_start MI_Zero36B
MI_Zero36B: ; 0x020D4BD0
mov r1, #0
mov r2, #0
mov r3, #0
stmia r0!, {r1, r2, r3}
stmia r0!, {r1, r2, r3}
stmia r0!, {r1, r2, r3}
bx lr
thumb_func_end MI_Zero36B
.balign 4, 0

743
lib/asm/nitro.s
View File

@ -80,703 +80,11 @@
.public OS_GetCpsrIrq
.public OSi_SendToPxi
_021E1A20:
.space 0x3970
_021E1A40:
.space 0x3950
.text
arm_func_start sub_020D43E8
sub_020D43E8: ; 0x020D43E8
stmdb sp!, {r3, r4, r5, r6, r7, lr}
mov r6, r1
mov r7, r0
mov r4, r3
mov r1, #0x10000000
mov r5, r2
bl MIi_CheckAnotherAutoDMA
mov r0, r7
mov r1, r6
mov r2, r4
mov r3, #0
bl MIi_CheckDma0SourceAddress
cmp r4, #0
ldmeqia sp!, {r3, r4, r5, r6, r7, pc}
mov r0, r7
bl MI_WaitDma
ldr r3, _020D4444 ; =0x96600000
mov r0, r7
mov r1, r6
mov r2, r5
orr r3, r3, r4, lsr #2
bl MIi_DmaSetParams
ldmia sp!, {r3, r4, r5, r6, r7, pc}
.align 2, 0
_020D4444: .word 0x96600000
arm_func_end sub_020D43E8
arm_func_start sub_020D4448
sub_020D4448: ; 0x020D4448
stmdb sp!, {r3, r4, r5, r6, r7, lr}
mov r6, r1
mov r7, r0
mov r4, r3
mov r1, #0x10000000
mov r5, r2
bl MIi_CheckAnotherAutoDMA
mov r0, r7
mov r1, r6
mov r2, r4
mov r3, #0
bl MIi_CheckDma0SourceAddress
cmp r4, #0
ldmeqia sp!, {r3, r4, r5, r6, r7, pc}
mov r0, r7
bl MI_WaitDma
ldr r3, _020D44A4 ; =0x92600000
mov r0, r7
mov r1, r6
mov r2, r5
orr r3, r3, r4, lsr #1
bl MIi_DmaSetParams
ldmia sp!, {r3, r4, r5, r6, r7, pc}
.align 2, 0
_020D44A4: .word 0x92600000
arm_func_end sub_020D4448
arm_func_start sub_020D44A8
sub_020D44A8: ; 0x020D44A8
stmdb sp!, {r4, lr}
mov r4, r0
cmp r2, #0
bne _020D44CC
cmp r3, #0
ldmeqia sp!, {r4, pc}
ldr r0, [sp, #8]
blx r3
ldmia sp!, {r4, pc}
_020D44CC:
ldr r0, _020D4594 ; =0x021E1A20
_020D44D0:
ldr ip, [r0]
cmp ip, #0
bne _020D44D0
ldr ip, _020D4598 ; =0x04000600
_020D44E0:
ldr r0, [ip]
and r0, r0, #0x7000000
mov r0, r0, lsr #0x18
tst r0, #2
beq _020D44E0
ldr ip, _020D4594 ; =0x021E1A20
mov r0, #1
str r0, [ip]
str r4, [ip, #4]
str r1, [ip, #8]
str r2, [ip, #0xc]
str r3, [ip, #0x10]
ldr lr, [sp, #8]
mov r0, r4
mov r3, #0
str lr, [ip, #0x14]
bl MIi_CheckDma0SourceAddress
mov r0, r4
bl MI_WaitDma
bl OS_DisableInterrupts
ldr r1, _020D4598 ; =0x04000600
mov r4, r0
ldr r0, [r1]
ldr r1, _020D4594 ; =0x021E1A20
and r0, r0, #0xc0000000
mov r2, r0, lsr #0x1e
mov r0, #0x200000
str r2, [r1, #0x18]
bl OS_GetIrqFunction
ldr r1, _020D4594 ; =0x021E1A20
ldr r2, _020D4598 ; =0x04000600
str r0, [r1, #0x1c]
ldr r0, [r2]
ldr r1, _020D459C ; =sub_020D45A0
bic r0, r0, #0xc0000000
orr r3, r0, #0x40000000
mov r0, #0x200000
str r3, [r2]
bl OS_SetIrqFunction
mov r0, #0x200000
bl OS_EnableIrqMask
bl sub_020D45A0
mov r0, r4
bl OS_RestoreInterrupts
ldmia sp!, {r4, pc}
.align 2, 0
_020D4594: .word 0x021E1A20
_020D4598: .word 0x04000600
_020D459C: .word sub_020D45A0
arm_func_end sub_020D44A8
arm_func_start sub_020D45A0
sub_020D45A0: ; 0x020D45A0
stmdb sp!, {r3, r4, r5, lr}
ldr r0, _020D463C ; =0x021E1A20
ldr r5, [r0, #0xc]
cmp r5, #0
ldmeqia sp!, {r3, r4, r5, pc}
ldr r0, _020D463C ; =0x021E1A20
cmp r5, #0x1d8
ldr r1, [r0, #0xc]
movhs r5, #0x1d8
ldr r4, [r0, #8]
subs r1, r1, r5
str r1, [r0, #0xc]
add r1, r4, r5
str r1, [r0, #8]
bne _020D4618
ldr r0, [r0, #4]
ldr r1, _020D4640 ; =sub_020D464C
mov r2, #0
bl OSi_EnterDmaCallback
ldr r0, _020D463C ; =0x021E1A20
mov r3, #0x3bc00000
rsb r3, r3, #0
ldr r0, [r0, #4]
ldr r2, _020D4644 ; =0x04000400
mov r1, r4
orr r3, r3, r5, lsr #2
bl MIi_DmaSetParams
mov r0, #0x200000
bl OS_ResetRequestIrqMask
ldmia sp!, {r3, r4, r5, pc}
_020D4618:
ldr r3, _020D4648 ; =0x84400000
ldr r0, [r0, #4]
ldr r2, _020D4644 ; =0x04000400
mov r1, r4
orr r3, r3, r5, lsr #2
bl MIi_DmaSetParams
mov r0, #0x200000
bl OS_ResetRequestIrqMask
ldmia sp!, {r3, r4, r5, pc}
.align 2, 0
_020D463C: .word 0x021E1A20
_020D4640: .word sub_020D464C
_020D4644: .word 0x04000400
_020D4648: .word 0x84400000
arm_func_end sub_020D45A0
arm_func_start sub_020D464C
sub_020D464C: ; 0x020D464C
stmdb sp!, {r3, lr}
mov r0, #0x200000
bl OS_DisableIrqMask
ldr r2, _020D46A4 ; =0x04000600
ldr r0, _020D46A8 ; =0x021E1A20
ldr r1, [r2]
ldr r3, [r0, #0x18]
bic r1, r1, #0xc0000000
orr r1, r1, r3, lsl #30
str r1, [r2]
ldr r1, [r0, #0x1c]
mov r0, #0x200000
bl OS_SetIrqFunction
ldr r0, _020D46A8 ; =0x021E1A20
mov r1, #0
str r1, [r0]
ldr r1, [r0, #0x10]
ldr r0, [r0, #0x14]
cmp r1, #0
ldmeqia sp!, {r3, pc}
blx r1
ldmia sp!, {r3, pc}
.align 2, 0
_020D46A4: .word 0x04000600
_020D46A8: .word 0x021E1A20
arm_func_end sub_020D464C
arm_func_start sub_020D46AC
sub_020D46AC: ; 0x020D46AC
stmdb sp!, {r4, r5, r6, lr}
movs r4, r2
mov r6, r0
mov r5, r1
bne _020D46D4
cmp r3, #0
ldmeqia sp!, {r4, r5, r6, pc}
ldr r0, [sp, #0x10]
blx r3
ldmia sp!, {r4, r5, r6, pc}
_020D46D4:
ldr r0, _020D4758 ; =0x021E1A20
_020D46D8:
ldr r1, [r0]
cmp r1, #0
bne _020D46D8
ldr r2, _020D4758 ; =0x021E1A20
mov r0, #1
str r0, [r2]
str r6, [r2, #4]
ldr ip, [sp, #0x10]
str r3, [r2, #0x10]
mov r0, r6
mov r1, #0x38000000
str ip, [r2, #0x14]
bl MIi_CheckAnotherAutoDMA
mov r0, r6
mov r1, r5
mov r2, r4
mov r3, #0
bl MIi_CheckDma0SourceAddress
mov r0, r6
bl MI_WaitDma
mov r0, r6
ldr r1, _020D475C ; =sub_020D4764
mov r2, #0
bl OSi_EnterDmaCallback
mov r0, r6
mov r1, r5
ldr r2, _020D4760 ; =0x04000400
mov r3, #0x3c00000
rsb r3, r3, #0
orr r3, r3, r4, lsr #2
bl MIi_DmaSetParams
ldmia sp!, {r4, r5, r6, pc}
.align 2, 0
_020D4758: .word 0x021E1A20
_020D475C: .word sub_020D4764
_020D4760: .word 0x04000400
arm_func_end sub_020D46AC
arm_func_start sub_020D4764
sub_020D4764: ; 0x020D4764
stmdb sp!, {r3, lr}
ldr r0, _020D478C ; =0x021E1A20
mov r1, #0
str r1, [r0]
ldr r1, [r0, #0x10]
ldr r0, [r0, #0x14]
cmp r1, #0
ldmeqia sp!, {r3, pc}
blx r1
ldmia sp!, {r3, pc}
.align 2, 0
_020D478C: .word 0x021E1A20
arm_func_end sub_020D4764
arm_func_start MIi_CpuClear16
MIi_CpuClear16: ; 0x020D4790
mov r3, #0
_020D4794:
cmp r3, r2
blt _020D47A0
b _020D47A4
_020D47A0:
strh r0, [r1, r3]
_020D47A4:
blt _020D47AC
b _020D47B0
_020D47AC:
add r3, r3, #2
_020D47B0:
blt _020D4794
bx lr
arm_func_end MIi_CpuClear16
arm_func_start MIi_CpuCopy16
MIi_CpuCopy16: ; 0x020D47B8
mov ip, #0
_020D47BC:
cmp ip, r2
blt _020D47C8
b _020D47CC
_020D47C8:
ldrh r3, [r0, ip]
_020D47CC:
blt _020D47D4
b _020D47D8
_020D47D4:
strh r3, [r1, ip]
_020D47D8:
blt _020D47E0
b _020D47E4
_020D47E0:
add ip, ip, #2
_020D47E4:
blt _020D47BC
bx lr
arm_func_end MIi_CpuCopy16
arm_func_start MIi_CpuClear32
MIi_CpuClear32: ; 0x020D47EC
add ip, r1, r2
_020D47F0:
cmp r1, ip
blt _020D47FC
b _020D4800
_020D47FC:
stmia r1!, {r0}
_020D4800:
blt _020D47F0
bx lr
arm_func_end MIi_CpuClear32
arm_func_start MIi_CpuCopy32
MIi_CpuCopy32: ; 0x020D4808
add ip, r1, r2
_020D480C:
cmp r1, ip
blt _020D4818
b _020D481C
_020D4818:
ldmia r0!, {r2}
_020D481C:
blt _020D4824
b _020D4828
_020D4824:
stmia r1!, {r2}
_020D4828:
blt _020D480C
bx lr
arm_func_end MIi_CpuCopy32
arm_func_start sub_020D4830
sub_020D4830: ; 0x020D4830
add ip, r0, r2
_020D4834:
cmp r0, ip
blt _020D4840
b _020D4844
_020D4840:
ldmia r0!, {r2}
_020D4844:
blt _020D484C
b _020D4850
_020D484C:
str r2, [r1]
_020D4850:
blt _020D4834
bx lr
arm_func_end sub_020D4830
arm_func_start MIi_CpuClearFast
MIi_CpuClearFast: ; 0x020D4858
stmdb sp!, {r4, r5, r6, r7, r8, sb}
add sb, r1, r2
mov ip, r2, lsr #5
add ip, r1, ip, lsl #5
mov r2, r0
mov r3, r2
mov r4, r2
mov r5, r2
mov r6, r2
mov r7, r2
mov r8, r2
_020D4884:
cmp r1, ip
blt _020D4890
b _020D4894
_020D4890:
stmia r1!, {r0, r2, r3, r4, r5, r6, r7, r8}
_020D4894:
blt _020D4884
_020D4898:
cmp r1, sb
blt _020D48A4
b _020D48A8
_020D48A4:
stmia r1!, {r0}
_020D48A8:
blt _020D4898
ldmia sp!, {r4, r5, r6, r7, r8, sb}
bx lr
arm_func_end MIi_CpuClearFast
arm_func_start MIi_CpuCopyFast
MIi_CpuCopyFast: ; 0x020D48B4
stmdb sp!, {r4, r5, r6, r7, r8, sb, sl}
add sl, r1, r2
mov ip, r2, lsr #5
add ip, r1, ip, lsl #5
_020D48C4:
cmp r1, ip
blt _020D48D0
b _020D48D4
_020D48D0:
ldmia r0!, {r2, r3, r4, r5, r6, r7, r8, sb}
_020D48D4:
blt _020D48DC
b _020D48E0
_020D48DC:
stmia r1!, {r2, r3, r4, r5, r6, r7, r8, sb}
_020D48E0:
blt _020D48C4
_020D48E4:
cmp r1, sl
blt _020D48F0
b _020D48F4
_020D48F0:
ldmia r0!, {r2}
_020D48F4:
blt _020D48FC
b _020D4900
_020D48FC:
stmia r1!, {r2}
_020D4900:
blt _020D48E4
ldmia sp!, {r4, r5, r6, r7, r8, sb, sl}
bx lr
arm_func_end MIi_CpuCopyFast
arm_func_start MI_Copy32B
MI_Copy32B: ; 0x020D490C
ldmia r0!, {r2, r3, ip}
stmia r1!, {r2, r3, ip}
ldmia r0!, {r2, r3, ip}
stmia r1!, {r2, r3, ip}
ldmia r0!, {r2, r3}
stmia r1!, {r2, r3}
bx lr
arm_func_end MI_Copy32B
arm_func_start MI_Copy36B
MI_Copy36B: ; 0x020D4928
ldmia r0!, {r2, r3, ip}
stmia r1!, {r2, r3, ip}
ldmia r0!, {r2, r3, ip}
stmia r1!, {r2, r3, ip}
ldmia r0!, {r2, r3, ip}
stmia r1!, {r2, r3, ip}
bx lr
arm_func_end MI_Copy36B
arm_func_start MI_Copy48B
MI_Copy48B: ; 0x020D4944
ldmia r0!, {r2, r3, ip}
stmia r1!, {r2, r3, ip}
ldmia r0!, {r2, r3, ip}
stmia r1!, {r2, r3, ip}
ldmia r0!, {r2, r3, ip}
stmia r1!, {r2, r3, ip}
ldmia r0!, {r2, r3, ip}
stmia r1!, {r2, r3, ip}
bx lr
arm_func_end MI_Copy48B
arm_func_start MI_Copy64B
MI_Copy64B: ; 0x020D4968
ldmia r0!, {r2, r3, ip}
stmia r1!, {r2, r3, ip}
ldmia r0!, {r2, r3, ip}
stmia r1!, {r2, r3, ip}
ldmia r0!, {r2, r3, ip}
stmia r1!, {r2, r3, ip}
ldmia r0!, {r2, r3, ip}
stmia r1!, {r2, r3, ip}
ldmia r0, {r0, r2, r3, ip}
stmia r1!, {r0, r2, r3, ip}
bx lr
arm_func_end MI_Copy64B
arm_func_start MI_CpuFill8
MI_CpuFill8: ; 0x020D4994
cmp r2, #0
beq _020D49A0
b _020D49A4
_020D49A0:
bx lr
_020D49A4:
tst r0, #1
beq _020D49D0
ldrh ip, [r0, #-1]
and ip, ip, #0xff
orr r3, ip, r1, lsl #8
strh r3, [r0, #-1]
add r0, r0, #1
subs r2, r2, #1
beq _020D49CC
b _020D49D0
_020D49CC:
bx lr
_020D49D0:
cmp r2, #2
blo _020D4A28
orr r1, r1, r1, lsl #8
tst r0, #2
beq _020D49F8
strh r1, [r0], #2
subs r2, r2, #2
beq _020D49F4
b _020D49F8
_020D49F4:
bx lr
_020D49F8:
orr r1, r1, r1, lsl #16
bics r3, r2, #3
beq _020D4A18
sub r2, r2, r3
add ip, r3, r0
_020D4A0C:
str r1, [r0], #4
cmp r0, ip
blo _020D4A0C
_020D4A18:
tst r2, #2
bne _020D4A24
b _020D4A28
_020D4A24:
strh r1, [r0], #2
_020D4A28:
tst r2, #1
beq _020D4A34
b _020D4A38
_020D4A34:
bx lr
_020D4A38:
ldrh r3, [r0]
and r3, r3, #0xff00
and r1, r1, #0xff
orr r1, r1, r3
strh r1, [r0]
bx lr
arm_func_end MI_CpuFill8
arm_func_start MI_CpuCopy8
MI_CpuCopy8: ; 0x020D4A50
cmp r2, #0
beq _020D4A5C
b _020D4A60
_020D4A5C:
bx lr
_020D4A60:
tst r1, #1
beq _020D4AB8
ldrh ip, [r1, #-1]
and ip, ip, #0xff
tst r0, #1
bne _020D4A7C
b _020D4A80
_020D4A7C:
ldrh r3, [r0, #-1]
_020D4A80:
bne _020D4A88
b _020D4A8C
_020D4A88:
mov r3, r3, lsr #8
_020D4A8C:
beq _020D4A94
b _020D4A98
_020D4A94:
ldrh r3, [r0]
_020D4A98:
orr r3, ip, r3, lsl #8
strh r3, [r1, #-1]
add r0, r0, #1
add r1, r1, #1
subs r2, r2, #1
beq _020D4AB4
b _020D4AB8
_020D4AB4:
bx lr
_020D4AB8:
eor ip, r1, r0
tst ip, #1
beq _020D4B14
bic r0, r0, #1
ldrh ip, [r0], #2
mov r3, ip, lsr #8
subs r2, r2, #2
blo _020D4AF0
_020D4AD8:
ldrh ip, [r0], #2
orr ip, r3, ip, lsl #8
strh ip, [r1], #2
mov r3, ip, lsr #0x10
subs r2, r2, #2
bhs _020D4AD8
_020D4AF0:
tst r2, #1
beq _020D4AFC
b _020D4B00
_020D4AFC:
bx lr
_020D4B00:
ldrh ip, [r1]
and ip, ip, #0xff00
orr ip, ip, r3
strh ip, [r1]
bx lr
_020D4B14:
tst ip, #2
beq _020D4B40
bics r3, r2, #1
beq _020D4BA4
sub r2, r2, r3
add ip, r3, r1
_020D4B2C:
ldrh r3, [r0], #2
strh r3, [r1], #2
cmp r1, ip
blo _020D4B2C
b _020D4BA4
_020D4B40:
cmp r2, #2
blo _020D4BA4
tst r1, #2
beq _020D4B68
ldrh r3, [r0], #2
strh r3, [r1], #2
subs r2, r2, #2
beq _020D4B64
b _020D4B68
_020D4B64:
bx lr
_020D4B68:
bics r3, r2, #3
beq _020D4B88
sub r2, r2, r3
add ip, r3, r1
_020D4B78:
ldr r3, [r0], #4
str r3, [r1], #4
cmp r1, ip
blo _020D4B78
_020D4B88:
tst r2, #2
bne _020D4B94
b _020D4B98
_020D4B94:
ldrh r3, [r0], #2
_020D4B98:
bne _020D4BA0
b _020D4BA4
_020D4BA0:
strh r3, [r1], #2
_020D4BA4:
tst r2, #1
beq _020D4BB0
b _020D4BB4
_020D4BB0:
bx lr
_020D4BB4:
ldrh r2, [r1]
ldrh r0, [r0]
and r2, r2, #0xff00
and r0, r0, #0xff
orr r0, r2, r0
strh r0, [r1]
bx lr
arm_func_end MI_CpuCopy8
thumb_func_start sub_020D4BD0
sub_020D4BD0: ; 0x020D4BD0
mov r1, #0
mov r2, #0
mov r3, #0
stmia r0!, {r1, r2, r3}
stmia r0!, {r1, r2, r3}
stmia r0!, {r1, r2, r3}
bx lr
thumb_func_end sub_020D4BD0
.balign 4, 0
arm_func_start MI_SwapWord
MI_SwapWord: ; 0x020D4BE0
swp r0, r0, [r1]
@ -20411,50 +19719,3 @@ _02110FC4:
.byte 0x00, 0x00, 0x00, 0x00
_02110FC8:
.byte 0x00, 0x00, 0x00, 0x00
.section .itcm,4,1,4
arm_func_start MI_SendGXCommand
MI_SendGXCommand: ; 0x01FF8580
stmdb sp!, {r3, r4, r5, r6, r7, r8, sb, sl, fp, lr}
movs r8, r2
mov sl, r0
mov sb, r1
ldmeqia sp!, {r3, r4, r5, r6, r7, r8, sb, sl, fp, pc}
mov r3, #0
bl MIi_CheckDma0SourceAddress
add r0, sl, sl, lsl #1
add r0, r0, #2
mov r0, r0, lsl #2
add r0, r0, #0xb0
add r6, r0, #0x4000000
_01FF85B0:
ldr r0, [r6]
tst r0, #-0x80000000
bne _01FF85B0
cmp r8, #0
beq _01FF85FC
ldr fp, _01FF860C ; =0x04000400
ldr r4, _01FF8610 ; =0x84400000
mov r5, #0x1d8
_01FF85D0:
cmp r8, #0x1d8
movhi r7, r5
movls r7, r8
mov r0, sl
mov r1, sb
mov r2, fp
orr r3, r4, r7, lsr #2
bl MIi_DmaSetParams
subs r8, r8, r7
add sb, sb, r7
bne _01FF85D0
_01FF85FC:
ldr r0, [r6]
tst r0, #-0x80000000
bne _01FF85FC
ldmia sp!, {r3, r4, r5, r6, r7, r8, sb, sl, fp, pc}
.align 2, 0
_01FF860C: .word 0x04000400
_01FF8610: .word 0x84400000
arm_func_end MI_SendGXCommand

40
lib/asm/nnsys.s
View File

@ -14486,7 +14486,7 @@ _020C0924:
str r1, [sp]
ldrsh r1, [r6, #2]
str r1, [sp, #4]
bl sub_020D4BD0
bl MI_Zero36B
ldrh r0, [r7]
ldr r2, _020C0B38 ; =0x02109494
ldr r1, _020C0B3C ; =0x02109495
@ -14755,17 +14755,17 @@ _020C0CC0:
ldr r0, _020C0E40 ; =_02110B10
mov r2, #8
str r3, [r1]
bl sub_020D4830
bl MIi_CpuSend32
bl sub_020BF418
ldr r1, _020C0E30 ; =0x04000400
mov r2, #0x30
bl sub_020D4830
bl MIi_CpuSend32
ldr r2, _020C0E44 ; =0x00001B19
ldr r1, _020C0E30 ; =0x04000400
ldr r0, _020C0E48 ; =_02110B18
str r2, [r1]
mov r2, #0x3c
bl sub_020D4830
bl MIi_CpuSend32
b _020C0DA4
_020C0D50:
tst r0, #2
@ -14774,22 +14774,22 @@ _020C0D50:
ldr r0, _020C0E40 ; =_02110B10
mov r2, #8
str r3, [r1]
bl sub_020D4830
bl MIi_CpuSend32
bl sub_020BF0F8
ldr r1, _020C0E30 ; =0x04000400
mov r2, #0x30
bl sub_020D4830
bl MIi_CpuSend32
ldr r2, _020C0E44 ; =0x00001B19
ldr r1, _020C0E30 ; =0x04000400
ldr r0, _020C0E48 ; =_02110B18
str r2, [r1]
mov r2, #0x3c
bl sub_020D4830
bl MIi_CpuSend32
b _020C0DA4
_020C0D98:
ldr r0, _020C0E4C ; =_02110B0C
mov r2, #0x48
bl sub_020D4830
bl MIi_CpuSend32
_020C0DA4:
cmp r7, #3
movne r0, #0
@ -14991,17 +14991,17 @@ _020C1060:
ldr r0, _020C11A8 ; =_02110B58
mov r2, #8
str r3, [r1]
bl sub_020D4830
bl MIi_CpuSend32
bl sub_020BF418
ldr r1, _020C1198 ; =0x04000400
mov r2, #0x30
bl sub_020D4830
bl MIi_CpuSend32
ldr r2, _020C11AC ; =0x00001B19
ldr r1, _020C1198 ; =0x04000400
ldr r0, _020C1190 ; =_02110B60
str r2, [r1]
mov r2, #0x3c
bl sub_020D4830
bl MIi_CpuSend32
b _020C1108
_020C10B4:
tst r0, #2
@ -15010,22 +15010,22 @@ _020C10B4:
ldr r0, _020C11A8 ; =_02110B58
mov r2, #8
str r3, [r1]
bl sub_020D4830
bl MIi_CpuSend32
bl sub_020BF0F8
ldr r1, _020C1198 ; =0x04000400
mov r2, #0x30
bl sub_020D4830
bl MIi_CpuSend32
ldr r2, _020C11AC ; =0x00001B19
ldr r1, _020C1198 ; =0x04000400
ldr r0, _020C1190 ; =_02110B60
str r2, [r1]
mov r2, #0x3c
bl sub_020D4830
bl MIi_CpuSend32
b _020C1108
_020C10FC:
ldr r0, _020C11B0 ; =_02110B54
mov r2, #0x48
bl sub_020D4830
bl MIi_CpuSend32
_020C1108:
cmp r8, #3
movne r0, #0
@ -16352,7 +16352,7 @@ _020C240C:
ldr r1, _020C244C ; =0x04000400
add r0, r0, #4
mov r2, r2, lsl #2
bl sub_020D4830
bl MIi_CpuSend32
ldr r0, _020C2448 ; =0x021DD404
mov r1, #0
ldr r0, [r0]
@ -16416,7 +16416,7 @@ _020C24B4:
ldr r3, _020C2524 ; =sub_020C2468
mov r1, r5
mov r2, r4
bl sub_020D46AC
bl MI_SendGXCommandAsyncFast
ldmia sp!, {r3, r4, r5, pc}
_020C24F4:
ldr r1, _020C2520 ; =0x021DD408
@ -16426,7 +16426,7 @@ _020C24F4:
ldr r3, _020C2524 ; =sub_020C2468
mov r1, r5
mov r2, r4
bl sub_020D44A8
bl MI_SendGXCommandAsync
ldmia sp!, {r3, r4, r5, pc}
.align 2, 0
_020C2518: .word GXi_DmaId
@ -16494,7 +16494,7 @@ _020C25EC:
mov r0, r5
mov r2, r4, lsl #2
str r6, [r1]
bl sub_020D4830
bl MIi_CpuSend32
ldmia sp!, {r4, r5, r6, pc}
.align 2, 0
_020C2604: .word 0x021DD404
@ -18505,7 +18505,7 @@ _020C3F30:
mov r4, r2, asr #4
ldrsh r7, [r1]
ldrsh r6, [r1, #2]
bl sub_020D4BD0
bl MI_Zero36B
ldrh r0, [r5]
ldr r1, _020C403C ; =0x021094B8
mov r3, #0x1000

4
main.lsf
View File

@ -279,6 +279,9 @@ Static main
Object os_terminate_proc.o
Object mi_wram.o
Object mi_dma.o
Object mi_dma_hblank.o
Object mi_dma_gxcommand.o
Object mi_memory.o
Object nitro.o
Object msl.o
}
@ -289,6 +292,7 @@ Autoload ITCM
Object os_irqHandler.o (.itcm)
Object os_reset.o (.itcm)
Object mi_dma.o (.itcm)
Object mi_dma_gxcommand.o (.itcm)
Object nitro.o (.itcm)
}