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150 lines
4.4 KiB
C
150 lines
4.4 KiB
C
#ifndef NITRO_GX_GX_H_
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#define NITRO_GX_GX_H_
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#include <nitro/hw/io_reg.h>
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typedef enum {
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GX_DISPMODE_GRAPHICS = 0x01,
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GX_DISPMODE_VRAM_A = 0x02,
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GX_DISPMODE_VRAM_B = 0x06,
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GX_DISPMODE_VRAM_C = 0x0a,
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GX_DISPMODE_VRAM_D = 0x0e,
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GX_DISPMODE_MMEM = 0x03
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} GXDispMode;
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typedef enum {
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GX_BGMODE_0 = 0,
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GX_BGMODE_1 = 1,
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GX_BGMODE_2 = 2,
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GX_BGMODE_3 = 3,
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GX_BGMODE_4 = 4,
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GX_BGMODE_5 = 5,
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GX_BGMODE_6 = 6
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} GXBGMode;
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typedef enum {
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GX_BG0_AS_2D = 0,
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GX_BG0_AS_3D = 1
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} GXBG0As;
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typedef enum {
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GX_BGSCROFFSET_0x00000 = 0x00,
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GX_BGSCROFFSET_0x10000 = 0x01,
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GX_BGSCROFFSET_0x20000 = 0x02,
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GX_BGSCROFFSET_0x30000 = 0x03,
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GX_BGSCROFFSET_0x40000 = 0x04,
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GX_BGSCROFFSET_0x50000 = 0x05,
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GX_BGSCROFFSET_0x60000 = 0x06,
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GX_BGSCROFFSET_0x70000 = 0x07
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} GXBGScrOffset;
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typedef enum {
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GX_BGCHAROFFSET_0x00000 = 0x00,
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GX_BGCHAROFFSET_0x10000 = 0x01,
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GX_BGCHAROFFSET_0x20000 = 0x02,
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GX_BGCHAROFFSET_0x30000 = 0x03,
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GX_BGCHAROFFSET_0x40000 = 0x04,
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GX_BGCHAROFFSET_0x50000 = 0x05,
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GX_BGCHAROFFSET_0x60000 = 0x06,
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GX_BGCHAROFFSET_0x70000 = 0x07
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} GXBGCharOffset;
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typedef enum {
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GX_OBJVRAMMODE_CHAR_2D = (0 << REG_GX_DISPCNT_OBJMAP_SHIFT) | (0 << REG_GX_DISPCNT_EXOBJ_SHIFT),
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GX_OBJVRAMMODE_CHAR_1D_32K =
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(1 << REG_GX_DISPCNT_OBJMAP_SHIFT) | (0 << REG_GX_DISPCNT_EXOBJ_SHIFT),
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GX_OBJVRAMMODE_CHAR_1D_64K =
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(1 << REG_GX_DISPCNT_OBJMAP_SHIFT) | (1 << REG_GX_DISPCNT_EXOBJ_SHIFT),
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GX_OBJVRAMMODE_CHAR_1D_128K =
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(1 << REG_GX_DISPCNT_OBJMAP_SHIFT) | (2 << REG_GX_DISPCNT_EXOBJ_SHIFT),
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GX_OBJVRAMMODE_CHAR_1D_256K =
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(1 << REG_GX_DISPCNT_OBJMAP_SHIFT) | (3 << REG_GX_DISPCNT_EXOBJ_SHIFT)
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} GXOBJVRamModeChar;
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typedef enum {
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GX_POWER_OFF = 0,
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GX_POWER_2D_MAIN = 1 << REG_GX_POWCNT_E2DG_SHIFT,
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GX_POWER_2D_SUB = 1 << REG_GX_POWCNT_E2DGB_SHIFT,
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GX_POWER_RE = 1 << REG_GX_POWCNT_RE_SHIFT,
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GX_POWER_GE = 1 << REG_GX_POWCNT_GE_SHIFT,
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GX_POWER_2D = GX_POWER_2D_MAIN | GX_POWER_2D_SUB,
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GX_POWER_3D = GX_POWER_RE | GX_POWER_GE,
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GX_POWER_ALL = GX_POWER_2D | GX_POWER_3D
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} GXPower;
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typedef enum {
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GX_DISP_SELECT_SUB_MAIN = 0,
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GX_DISP_SELECT_MAIN_SUB = 1
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} GXDispSelect;
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void GX_SetGraphicsMode(GXDispMode dispMode, GXBGMode bgMode, GXBG0As bg0_2d3d);
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void GXS_SetGraphicsMode(GXBGMode bgMode);
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static inline s32 GX_GetVCount() {
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return reg_GX_VCOUNT;
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}
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static inline s32 GX_GetVCountEqVal(void) {
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u16 val = reg_GX_DISPSTAT;
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return ((val >> 8) & 0x00ff) | ((val << 1) & 0x0100);
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}
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static inline void GX_VCountEqIntr(BOOL enable) {
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if (enable) {
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reg_GX_DISPSTAT |= REG_GX_DISPSTAT_VQI_MASK;
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} else {
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reg_GX_DISPSTAT &= ~REG_GX_DISPSTAT_VQI_MASK;
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}
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}
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static inline void GX_SetVCountEqVal(s32 val) {
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reg_GX_DISPSTAT = (u16)(reg_GX_DISPSTAT & (REG_GX_DISPSTAT_VBLK_MASK | REG_GX_DISPSTAT_HBLK_MASK | REG_GX_DISPSTAT_LYC_MASK | REG_GX_DISPSTAT_VBI_MASK | REG_GX_DISPSTAT_HBI_MASK | REG_GX_DISPSTAT_VQI_MASK) | ((val & 0xFF) << 8) | ((val & 0x100) >> 1));
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}
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static inline void GX_SetBGScrOffset(GXBGScrOffset offset)
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{
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reg_GX_DISPCNT = (u32)((reg_GX_DISPCNT & ~REG_GX_DISPCNT_BGSCREENOFFSET_MASK) |
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(offset << REG_GX_DISPCNT_BGSCREENOFFSET_SHIFT));
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}
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static inline void GX_SetBGCharOffset(GXBGCharOffset offset) {
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reg_GX_DISPCNT = (u32)((reg_GX_DISPCNT & ~REG_GX_DISPCNT_BGCHAROFFSET_MASK) |
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(offset << REG_GX_DISPCNT_BGCHAROFFSET_SHIFT));
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}
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s32 GX_VBlankIntr(BOOL enable);
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s32 GX_HBlankIntr(BOOL enable);
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void GX_Init(void);
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void GX_DispOff(void);
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void GX_DispOn(void);
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static inline void GX_SetPower(GXPower gxbit_power) {
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reg_GX_POWCNT = (reg_GX_POWCNT & ~GX_POWER_ALL) | gxbit_power;
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}
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static inline void GXS_DispOff(void) {
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reg_GXS_DB_DISPCNT &= ~REG_GXS_DB_DISPCNT_MODE_MASK;
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}
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static inline void GXS_DispOn(void) {
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reg_GXS_DB_DISPCNT |= REG_GXS_DB_DISPCNT_MODE_MASK;
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}
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static inline void GX_SetDispSelect(GXDispSelect sel) {
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reg_GX_POWCNT = (reg_GX_POWCNT & ~REG_GX_POWCNT_DSEL_MASK) | (sel << REG_GX_POWCNT_DSEL_SHIFT);
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}
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static inline void GX_SetVisiblePlane(int plane) {
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reg_GX_DISPCNT = (u32)((reg_GX_DISPCNT & ~REG_GX_DISPCNT_DISPLAY_MASK) | (plane << REG_GX_DISPCNT_DISPLAY_SHIFT));
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}
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static inline void GXS_SetVisiblePlane(int plane) {
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reg_GXS_DB_DISPCNT = (u32)((reg_GXS_DB_DISPCNT & ~REG_GXS_DB_DISPCNT_DISPLAY_MASK) | (plane << REG_GXS_DB_DISPCNT_DISPLAY_SHIFT));
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}
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#endif //NITRO_GX_GX_H_
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