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26af4db82d
* update from dtk-template and start work towards using clangd * include <a> -> "a" * Update build.yml * remove/add non-trivial class in union warning
339 lines
9.4 KiB
C
339 lines
9.4 KiB
C
#ifndef RVL_SDK_PPC_ARCH_H
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#define RVL_SDK_PPC_ARCH_H
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#include "common.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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u32 PPCMfmsr(void);
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void PPCMtmsr(u32 val);
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u32 PPCMfhid0(void);
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void PPCMthid0(u32 val);
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u32 PPCMfl2cr(void);
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void PPCMtl2cr(u32 val);
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void PPCMtdec(u32 val);
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void PPCSync(void);
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void PPCHalt(void);
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void PPCMtmmcr0(u32 val);
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void PPCMtmmcr1(u32 val);
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void PPCMtpmc1(u32 val);
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void PPCMtpmc2(u32 val);
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void PPCMtpmc3(u32 val);
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void PPCMtpmc4(u32 val);
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u32 PPCMffpscr(void);
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void PPCMtfpscr(u32 val);
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u32 PPCMfhid2(void);
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void PPCMthid2(u32 val);
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u32 PPCMfwpar(void);
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void PPCMtwpar(u32 val);
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void PPCDisableSpeculation(void);
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void PPCSetFpNonIEEEMode(void);
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void PPCMthid4(u32 val);
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#ifdef __cplusplus
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}
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#endif
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#endif
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/**
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* MSR
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* Machine Status Register
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*/
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// Power management enable
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#define MSR_POW (1 << (31 - 13))
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// Exception little-endian mode
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#define MSR_ILE (1 << (31 - 15))
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// External interrupt enable
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#define MSR_EE (1 << (31 - 16))
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// Privilege level
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#define MSR_PR (1 << (31 - 17))
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// Floating-point available
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#define MSR_FP (1 << (31 - 18))
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// Machine check enable
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#define MSR_ME (1 << (31 - 19))
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// IEEE floating-point exception mode 0
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#define MSR_FE0 (1 << (31 - 20))
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// Single-step trace enable
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#define MSR_SE (1 << (31 - 21))
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// Branch trace enable
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#define MSR_BE (1 << (31 - 22))
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// IEEE floating-point exception mode 1
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#define MSR_FE1 (1 << (31 - 23))
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// Exception prefix
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#define MSR_IP (1 << (31 - 25))
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// Instruction address translation
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#define MSR_IR (1 << (31 - 26))
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// Data address translation
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#define MSR_DR (1 << (31 - 27))
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// Performance monitor marked mode
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#define MSR_PM (1 << (31 - 29))
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// Indicates whether system reset or machine check exception is recoverable
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#define MSR_RI (1 << (31 - 30))
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// Little-endian mode enable
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#define MSR_LE (1 << (31 - 31))
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/**
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* HID0
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* Hardware Implementation-Dependent Register 0
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*/
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// Enable MCP
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#define HID0_EMCP (1 << (31 - 0))
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// Enable/disable 60x bus address and data parity generation
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#define HID0_DBP (1 << (31 - 1))
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// Enable/disable 60x bus address parity checking
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#define HID0_EBA (1 << (31 - 2))
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// Enable 60x bus data parity checking
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#define HID0_EBD (1 << (31 - 3))
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// CLK_OUT enable
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#define HID0_BCLK (1 << (31 - 4))
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// CLK_OUT enable
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#define HID0_ECLK (1 << (31 - 6))
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// Disable precharge of ARTRY
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#define HID0_PAR (1 << (31 - 7))
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// Doze mode enable
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#define HID0_DOZE (1 << (31 - 8))
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// Nap mode enable
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#define HID0_NAP (1 << (31 - 9))
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// Sleep mode enable
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#define HID0_SLEEP (1 << (31 - 10))
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// Dynamic power management enable
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#define HID0_DPM (1 << (31 - 11))
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// Not hard reset (software-use only)
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#define HID0_NHR (1 << (31 - 15))
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// Instruction cache enable
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#define HID0_ICE (1 << (31 - 16))
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// Data cache enable
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#define HID0_DCE (1 << (31 - 17))
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// Instruction cache lock
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#define HID0_ILOCK (1 << (31 - 18))
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// Data cache lock
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#define HID0_DLOCK (1 << (31 - 19))
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// Instruction cache flash invalidate
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#define HID0_ICFI (1 << (31 - 20))
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// Data cache flash invalidate
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#define HID0_DCFI (1 << (31 - 21))
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// Speculative cache access disable
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#define HID0_SPD (1 << (31 - 22))
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// Enable M bit on bus for instruction fetches
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#define HID0_IFEM (1 << (31 - 23))
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// Store gathering enable
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#define HID0_SGE (1 << (31 - 24))
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// Data cache flush assist
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#define HID0_DCFA (1 << (31 - 25))
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// Branch Target Instruction Cache enable
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#define HID0_BTIC (1 << (31 - 26))
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// Address broadcast enable
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#define HID0_ABE (1 << (31 - 28))
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// Branch history table enable
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#define HID0_BHT (1 << (31 - 29))
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// No-op the data cache touch instructions
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#define HID0_NOOPTI (1 << (31 - 31))
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/**
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* HID1
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* Hardware Implementation-Dependent Register 1
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*/
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// PLL configuration bits (read-only)
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#define HID1_PC0 (1 << (31 - 0))
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#define HID1_PC1 (1 << (31 - 1))
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#define HID1_PC2 (1 << (31 - 2))
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#define HID1_PC3 (1 << (31 - 3))
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#define HID1_PC4 (1 << (31 - 4))
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/**
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* L2CR
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* L2 Control Register
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*/
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// L2 enable
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#define L2CR_L2E (1 << (31 - 0))
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// L2 Checkstop enable
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#define L2CR_L2CE (1 << (31 - 1))
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// L2 data-only
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#define L2CR_L2DO (1 << (31 - 9))
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// L2 global invalidate
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#define L2CR_L2I (1 << (31 - 10))
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// L2 write-through
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#define L2CR_L2WT (1 << (31 - 12))
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// L2 test support
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#define L2CR_L2TS (1 << (31 - 13))
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// L2 global invalidate in progress (read only)
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#define L2CR_L2IP (1 << (31 - 31))
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/**
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* PMC1-PMC4
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* Performance Monitor Counter Registers
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*/
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// Overflow
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#define PMC_OV (1 << (31 - 0))
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/**
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* FPSCR
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* Floating-Point Status and Control Register
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*/
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// Floating-point exception summary
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#define FPSCR_FX (1 << (31 - 0))
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// Floating-point enabled exception summary
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#define FPSCR_FEX (1 << (31 - 1))
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// Floating-point invalid operation exception summary
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#define FPSCR_VX (1 << (31 - 2))
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// Floating-point overflow exception
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#define FPSCR_OX (1 << (31 - 3))
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// Floating-point underflow exception
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#define FPSCR_UX (1 << (31 - 4))
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// Floating-point zero divide exception
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#define FPSCR_ZX (1 << (31 - 5))
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// Floating-point inexact exception
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#define FPSCR_XX (1 << (31 - 6))
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// Floating-point invalid operation exception for SNaN
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#define FPSCR_VXSNAN (1 << (31 - 7))
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// Floating-point invalid operation exception for (inf - inf)
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#define FPSCR_VXISI (1 << (31 - 8))
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// Floating-point invalid operation exception for (inf / inf)
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#define FPSCR_VXIDI (1 << (31 - 9))
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// Floating-point invalid operation exception for (0 / 0)
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#define FPSCR_VXZDZ (1 << (31 - 10))
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// Floating-point invalid operation exception for (inf * 0)
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#define FPSCR_VXIMZ (1 << (31 - 11))
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// Floating-point invalid operation exception for invalid compare
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#define FPSCR_VXVC (1 << (31 - 12))
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// Floating-point fraction rounded
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#define FPSCR_FR (1 << (31 - 13))
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// Floating-point fraction inexact
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#define FPSCR_FI (1 << (31 - 14))
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// Floating-point result flags
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#define FPSCR_FPRF (0x1F << (31 - 19))
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// Unknown
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#define FPSCR_UNK20 (1 << (31 - 20))
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// Floating-point invalid operation exception for software request
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#define FPSCR_VXSOFT (1 << (31 - 21))
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// Floating-point invalid operation exception for invalid square root
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#define FPSCR_VXSQRT (1 << (31 - 22))
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// Floating-point invalid operation exception for invalid integer convert
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#define FPSCR_VXCVI (1 << (31 - 23))
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// Floating-point invalid operation exception enable
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#define FPSCR_VE (1 << (31 - 24))
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// IEEE floating-point overflow exception enable
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#define FPSCR_OE (1 << (31 - 25))
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// IEEE floating-point underflow exception enable
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#define FPSCR_UE (1 << (31 - 26))
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// IEEE floating-point zero divide exception enable
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#define FPSCR_ZE (1 << (31 - 27))
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// Floating-point inexact exception enable
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#define FPSCR_XE (1 << (31 - 28))
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// Floating-point non-IEEE mode
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#define FPSCR_NI (1 << (31 - 29))
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// Floating-point rounding control
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#define FPSCR_RN (0x3 << (31 - 31))
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/**
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* HID2
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* Hardware Implementation-Dependent Register 2
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*/
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// Write pipe enable
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#define HID2_WPE (1 << (31 - 1))
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// Paired-single enable
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#define HID2_PSE (1 << (31 - 2))
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// Locked cache enable
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#define HID2_LCE (1 << (31 - 3))
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// DMA queue length (read only)
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#define HID2_DMAQL ((1 << (31 - 4)) | (1 << (31 - 5)) | (1 << (31 - 6)) | (1 << (31 - 7)))
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// dcbz_l cache hit error
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#define HID2_DCHERR (1 << (31 - 8))
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// DMA access to normal cache error
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#define HID2_DNCERR (1 << (31 - 9))
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// DMA cache miss error
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#define HID2_DCMERR (1 << (31 - 10))
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// DMA queue overflow error
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#define HID2_DQOERR (1 << (31 - 11))
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// dcbz_l cache hit error enable
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#define HID2_DCHEE (1 << (31 - 12))
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// DMA access to normal cache error enable
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#define HID2_DNCEE (1 << (31 - 13))
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// DMA cache miss error enable
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#define HID2_DCMEE (1 << (31 - 14))
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// DMA queue overflow error enable
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#define HID2_DQOEE (1 << (31 - 15))
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/**
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* WPAR
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* Write Pipe Address Register
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*/
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// High order address bits of the data to be gathered
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#define WPAR_GB_ADDR (0x07FFFFFF << (31 - 26))
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// Buffer not empty (read only)
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#define WPAR_BNE (1 << (31 - 31))
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/**
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* DMAU
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* Direct Memory Access Upper Register
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*/
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// High order address bits of starting address in external memory of the DMA
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// transfer
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#define DMAU_MEM_ADDR (0x07FFFFFF << (31 - 26))
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// High order bits of transfer length, in cache lines. Low order bits are in
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// DMAL
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#define DMAU_DMA_LEN_U (0x0000001F << (31 - 31))
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/**
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* DMAL
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* Direct Memory Access Lower Register
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*/
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// High order address bits of starting address in locked cache of the DMA
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// transfer
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#define DMAL_LC_ADDR (0x07FFFFFF << (31 - 26))
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// DMA load command
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#define DMAL_DMA_LD (1 << (31 - 27))
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// Low order bits of transfer length, in cache lines. High order bits are in
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// DMAU
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#define DMAL_DMA_LEN_L (0x3 << (31 - 29))
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// Trigger bit
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#define DMAL_DMA_T (1 << (31 - 30))
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// Flush bit
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#define DMAL_DMA_F (1 << (31 - 31))
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/**
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* PVR
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* Processor Version Register
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*/
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// A 16-bit number that uniquely identifies a particular processor version
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#define PVR_VER (0xFFFF0000)
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// A 16-bit number that distinguishes between various releases of a particular
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// version (that is, an engineering change level)
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#define PVR_REV (0x0000FFFF)
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/**
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* HID4
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* Hardware Implementation-Dependent Register 4
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*/
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// Unknown
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#define HID4_H4A (1 << (31 - 0))
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// L2 fetch mode
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#define HID4_L2FM (0x3 << (31 - 2))
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// Bus pipeline depth
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#define HID4_BPD (0x3 << (31 - 4))
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// L2 second castout buffer enable
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#define HID4_BCO (1 << (31 - 5))
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// Secondary BAT enable
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#define HID4_SBE (1 << (31 - 6))
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// Paired-singles control bit 1
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#define HID4_PS1_CTL (1 << (31 - 7))
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// Data bus parking
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#define HID4_DBP (1 << (31 - 9))
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// L2 MUM enable
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#define HID4_L2MUM (1 << (31 - 10))
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// L2CFI - L2 complete castout prior to L2 flash invalidate
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#define HID4_L2_CCFI (1 << (31 - 11))
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// Paired-singles control bit 2
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#define HID4_PSS2_CTL (1 << (31 - 12))
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