Commit Graph
1 Commits
Author SHA1 Message Date
velzie 1948ce2245 Decode and lift the scalar Advanced SIMD group
C++ was dying on SIGILL at `cmge d0, d0, #0`. The scalar AdvSIMD forms
share the `11110` group with scalar floating point and are told apart by
bit 30, which the decoder was not looking at, so they all fell through to
the FP path and out the bottom as undecoded.

They are the vector instructions restricted to lane 0, so rather than a
parallel set of opcodes they get a `scalar` flag on VArr: decoding reuses
the three-same, two-reg-misc, shift-immediate and pairwise tables, and
lifting reuses the vector lowerings with commit_vector masking the result
down to one lane instead of to 64 bits.

The pairwise forms needed real work in the formatter -- they are spelled
`-p` rather than `-v` and read a two-lane source -- and that turned up an
existing conflation of fmaxv with fmaxnmv, now separate opcodes.

Corpus: 414 undecoded -> 311, mnemonic mismatches 0 across 746k
instructions. C++ with STL containers, ostringstream and exceptions now
matches QEMU byte for byte, static and dynamic; the dynamic build throws
across the libstdc++/libgcc_s boundary, so the guest interpreter is
relocating and unwinding real shared objects. Both are in the suite: 32
comparisons, all passing.
2026-08-05 04:49:33 -04:00