2013-11-27 04:11:31 +00:00
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This file credits all the contributors of the Capstone engine project.
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Key developers
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==============
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2021-12-22 08:29:37 +00:00
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Nguyen Anh Quynh <aquynh -at- gmail.com>
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Chenxu Wu (kabeor) kabeor@qiling.io
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2013-11-27 04:11:31 +00:00
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2021-12-22 08:29:37 +00:00
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Past key developers
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===================
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Tan Sheng Di <shengdi -at- coseinc.com>
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2013-11-27 04:11:31 +00:00
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- Bindings: Ruby
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2021-12-22 08:29:37 +00:00
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Ben Nagy <ben -at- coseinc.com>
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2013-11-27 04:11:31 +00:00
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- Bindings: Ruby, Go
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2021-12-22 08:29:37 +00:00
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Dang Hoang Vu <dang.hvu -at- gmail.com>
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2013-11-27 04:11:31 +00:00
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- Bindings: Java
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2013-11-27 08:15:38 +00:00
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Beta testers (in random order)
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==============================
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Pancake
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Van Hauser
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FX of Phenoelit
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2013-11-27 09:00:32 +00:00
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The Grugq, The Grugq <-- our hero for submitting the first ever patch!
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2013-11-27 08:15:38 +00:00
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Isaac Dawson, Veracode Inc
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Patroklos Argyroudis, Census Inc. (http://census-labs.com)
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Attila Suszter
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Le Dinh Long
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Nicolas Ruff
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Gunther
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Alex Ionescu, Winsider Seminars & Solutions Inc.
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Snare
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2013-11-27 14:19:58 +00:00
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Daniel Godas-Lopez
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2013-11-27 10:03:59 +00:00
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Joshua J. Drake
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2013-11-27 13:24:39 +00:00
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Edgar Barbosa
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2013-11-27 14:29:29 +00:00
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Ralf-Philipp Weinmann
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2013-12-01 15:47:11 +00:00
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Hugo Fortier
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2013-12-03 09:26:57 +00:00
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Joxean Koret
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2013-12-04 04:14:28 +00:00
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Bruce Dang
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2013-12-05 02:08:03 +00:00
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Andrew Dunham
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2014-05-01 13:44:45 +00:00
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Contributors (in no particular order)
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=====================================
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(Please let us know if you want to have your name here)
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Ole André Vadla Ravnås (author of the 100th Pull-Request in our Github repo, thanks!)
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2014-05-15 14:01:15 +00:00
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Axel "0vercl0k" Souchet (@0vercl0k) & Alex Ionescu: port to MSVC.
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2014-05-28 08:37:01 +00:00
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Daniel Pistelli: Cmake support.
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2014-05-31 04:12:18 +00:00
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Peter Hlavaty: integrate Capstone for Windows kernel drivers.
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2014-06-26 14:49:16 +00:00
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Guillaume Jeanne: Ocaml binding.
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2018-07-04 14:50:28 +00:00
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Martin Tofall, Obsidium Software: Optimize X86 performance & size + x86 encoding features.
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2015-05-13 09:23:29 +00:00
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David Martínez Moreno & Hilko Bengen: Debian package.
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2014-10-06 16:20:42 +00:00
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Félix Cloutier: Xcode project.
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2014-10-06 16:33:35 +00:00
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Benoit Lecocq: OpenBSD package.
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2014-10-15 12:54:00 +00:00
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Christophe Avoinne (Hlide): Improve memory management for better performance.
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2015-01-30 02:54:52 +00:00
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Michael Cohen & Nguyen Tan Cong: Python module installer.
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2015-05-13 08:09:26 +00:00
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Adel Gadllah, Francisco Alonso & Stefan Cornelius: RPM package.
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2015-06-16 09:18:26 +00:00
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Felix Gröbert (Google): fuzz testing harness.
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2016-01-19 13:42:41 +00:00
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Xipiter LLC: Capstone logo redesigned.
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2016-04-10 02:46:13 +00:00
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Satoshi Tanda: Support Windows kernel driver.
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2016-10-10 07:21:29 +00:00
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Tang Yuhang: cstool.
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2016-10-25 20:59:26 +00:00
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Andrew Dutcher: better Python setup.
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2016-11-11 14:14:23 +00:00
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Ruben Boonen: PowerShell binding.
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2017-04-17 02:24:31 +00:00
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David Zimmer: VB6 binding.
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2018-06-25 11:57:50 +00:00
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Philippe Antoine: Integration with oss-fuzz and various fixes.
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2015-02-24 14:05:48 +00:00
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Bui Dinh Cuong: Explicit registers accessed for Arm64.
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2015-02-24 15:33:04 +00:00
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Vincent Bénony: Explicit registers accessed for X86.
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2015-05-13 08:09:26 +00:00
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Adel Gadllah, Francisco Alonso & Stefan Cornelius: RPM package.
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2015-06-16 09:18:26 +00:00
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Felix Gröbert (Google): fuzz testing harness.
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2015-10-06 13:56:36 +00:00
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Daniel Collin & Nicolas Planel: M68K architecture.
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2016-03-01 03:09:17 +00:00
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Pranith Kumar: Explicit registers accessed for Arm64.
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2016-05-12 04:48:32 +00:00
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Xipiter LLC: Capstone logo redesigned.
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Satoshi Tanda: Support Windows kernel driver.
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2016-04-12 07:26:47 +00:00
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Koutheir Attouchi: Support for Windows CE.
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2016-05-03 13:37:52 +00:00
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Fotis Loukos: TMS320C64x architecture.
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M680X: Target ready for pull request (#1034)
* Added new M680X target. Supports M6800/1/2/3/9, HD6301
* M680X: Reformat for coding guide lines. Set alphabetical order in HACK.TXT
* M680X: Prepare for python binding. Move cs_m680x, m680x_insn to m680x_info. Chec
> k cpu type, no default.
* M680X: Add python bindings. Added python tests.
* M680X: Added cpu types to usage message.
* cstool: Avoid segfault for invalid <arch+mode>.
* Make test_m680x.c/test_m680x.py output comparable (diff params: -bu). Keep xprint.py untouched.
* M680X: Update CMake/make for m680x support. Update .gitignore.
* M680X: Reduce compiler warnings.
* M680X: Reduce compiler warnings.
* M680X: Reduce compiler warnings.
* M680X: Make test_m680x.c/test_m680x.py output comparable (diff params: -bu).
* M680X: Add ocaml bindings and tests.
* M680X: Add java bindings and tests.
* M680X: Added tests for all indexed addressing modes. C/Python/Ocaml
* M680X: Naming, use page1 for PAGE1 instructions (without prefix).
* M680X: Naming, use page1 for PAGE1 instructions (without prefix).
* M680X: Used M680X_FIRST_OP_IN_MNEM in tests C/python/java/ocaml.
* M680X: Added access property to cs_m680x_op.
* M680X: Added operand size.
* M680X: Remove compiler warnings.
* M680X: Added READ/WRITE access property per operator.
* M680X: Make reg_inherent_hdlr independent of CPU type.
* M680X: Add HD6309 support + bug fixes
* M680X: Remove errors and warning.
* M680X: Add Bcc/LBcc to group BRAREL (relative branch).
* M680X: Add group JUMP to BVS/BVC/LBVS/LBVC. Remove BRAREL from BRN/LBRN.
* M680X: Remove LBRN from group BRAREL.
* M680X: Refactored cpu_type initialization for better readability.
* M680X: Add two operands for insn having two reg. in mnemonic. e.g. ABX.
* M680X: Remove typo in cstool.c
* M680X: Some format improvements in changed_regs.
* M680X: Remove insn id string list from tests (C/python/java/ocaml).
* M680X: SEXW, set access of reg. D to WRITE.
* M680X: Sort changed_regs in increasing m680x_insn order.
* M680X: Add M68HC11 support + Reduced from two to one INDEXED operand.
* M680X: cstool, also write '(in mnemonic)' for second reg. operand.
* M680X: Add BRN/LBRN to group JUMP and BRAREL.
* M680X: For Bcc/LBcc/BRSET/BRCLR set reg. CC to read access.
* M680X: Correctly print negative immediate values with option CS_OPT_UNSIGNED.
* M680X: Rename some instruction handlers.
* M680X: Add M68HC05 support.
* M680X: Dont print prefix '<' for direct addr. mode.
* M680X: Add M68HC08 support + resorted tables + bug fixes.
* M680X: Add Freescale HCS08 support.
* M680X: Changed group names, avoid spaces.
* M680X: Refactoring, rename addessing mode handlers.
* M680X: indexed addr. mode, changed pre/post inc-/decrement representation.
* M680X: Rename some M6809/HD6309 specific functions.
* M680X: Add CPU12 (68HC12/HCS12) support.
* M680X: Correctly display illegal instruction as FCB .
* M680X: bugfix: BRA/BRN/BSR/LBRA/LBRN/LBSR does not read CC reg.
* M680X: bugfix: Correctly check for sufficient code size for M6809 indexed addressing.
* M680X: Better support for changing insn id within handler for addessing mode.
* M680X: Remove warnings.
* M680X: In set_changed_regs_read_write_counts use own access_mode.
* M680X: Split cpu specific tables into separate *.inc files.
* M680X: Remove warnings.
* M680X: Removed address_mode. Addressing mode is available in operand.type
* M680X: Bugfix: BSET/BCLR/BRSET/BRCLR correct read/modify CC reg.
* M680X: Remove register TMP1. It is first visible in CPU12X.
* M680X: Performance improvement + bug fixes.
* M680X: Performance improvement, make cpu_tables const static.
* M680X: Simplify operand decoding by using two handlers.
* M680X: Replace M680X_OP_INDEX by M680X_OP_CONSTANT + bugfix in java/python/ocaml bindings.
* M680X: Format with astyle.
* M680X: Update documentation.
* M680X: Corrected author for m680x specific files.
* M680X: Make max. number of architectures single source.
2017-10-21 13:44:36 +00:00
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Wolfgang Schwotzer: M680X architecture.
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2018-06-01 14:41:17 +00:00
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Philippe Antoine: Integration with oss-fuzz and various fixes.
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2018-07-04 14:47:55 +00:00
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Stephen Eckels (stevemk14ebr): x86 encoding features
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2019-02-01 15:03:47 +00:00
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Tong Yu(Spike) & Kai Jern, Lau (xwings): WASM architecture.
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2018-12-04 18:09:38 +00:00
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Sebastian Macke: MOS65XX architecture
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2018-12-16 13:48:51 +00:00
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Ilya Leoshkevich: SystemZ architecture improvements.
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2019-02-11 17:00:34 +00:00
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Do Minh Tuan: Regression testing tool (cstest)
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2019-02-18 09:39:51 +00:00
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david942j: BPF (both classic and extended) architecture.
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RISCV support ISRV32/ISRV64 (#1401)
* Added RISCV dir to contain the RISCV architecture engine code. Adding the TableGen files generated from llvm-tblgen. Add Disassembler.h
* Started working on RISCVDisassembler.c - RISCV_init(), RISCVDisassembler_getInstruction, and RISCV_getInstruction
* Added all functions to RISCVDisassembler.c and needed modifications to RISCVGenDisassemblerTables.inc. Add and modified RISCVGenSubtargetInfo.inc. Start creation of RISCVInstPrinter.h
* Finished RISCVGenAsmWriter.inc. Finished RISCVGenRegisterInfo.inc. Minor fixes to RISCVDisassembler.c. Working on RISCVInstPrinter
* Finished RISCVInstPrinter, RISCVMapping, RISCVBaseInfo, RISCVGenInstrInfo.inc, RISCVModule.c. Working on riscv.h
* Backport it from: https://github.com/porto703/capstone/commit/0db412ce3bed9d963caf598a2cb7dc76b41a5a2b
* All RISCV files added. Compiled correctly and initial test for ADD, ADDI, AND works properly.
* Add refactored cs.c for RISCV
* Testing all I instructions in test_riscv.c
* Modify the orignal backport for RISCVGenRegisterInfo.inc, capstone.h and test_iter to work w/ the current code strcuture
* Fix issue with RISCVGenRegisterInfo.inc - RISCVRegDesc[] (Excess elements in struct initializer). Added RISCV tests to test_iter.c
* fixed bug related to incorrect initialization of memory after malloc
* fix compile bug
* Fix compile errors.
* move riscv.h to include/capstone
* fix indentation issues
* fix coding style issues
* Fix indentation issues
* fix coding style
* Move variable declaration to the top of the block
* Fix coding indentation
* Move some stuff into RISCVMappingInsn.inc
* Fix code sytle
* remove cs_mode support for RISCV
* update asmwriter-inc to LLVM upstream
* update the .inc files to riscv upstream
* update riscv disassembler function for suport 16bit instructions
* update printer & tablegen inc files which have fixed arguments mismatch
* update headers and mapping source
* add riscv architecture specific test code
* fix all RISCV tons of compiler errors
* pass final tests
* add riscv tablegen patchs
* merge with upstream/next
* fix cstool missing riscv file
* fix root Makefile
* add new TableGen patchs for riscv
* fix cmakefile.txt of missing one riscv file
* fix declaration conflict
* fix incompatible declaration type
* change riscvc from arch to mode
* fix test_riscv warnning
* fix code style and add riscv part of test_basic
* add RISCV64 mode
* add suite for riscv
* crack fuzz test
* fix getfeaturebits test add riscvc
* fix test missing const qualifier warnning
* fix testcase type mismatch
* fix return value missing
* change getfeaturebits test
* add test cs files
* using a winder type contain the decode string
* fix a copy typo
* remove useless mode for riscv
* change cs file blank type
* add repo for update_riscv & fix cstool missing riscv mode
* fix typo
* add riscv for cstool useage
* add TableGen patch for riscv asmwriter
* clean ctags file
* remove black comment line
* fix fuzz related something
* fix missing RISCV string of fuzz
* update readme, etc..
* add riscv *.s.cs file
* add riscv *.s.cs file & clear ctags
* clear useless array declarations at capstone_test
* update to 5e4069f
* update readme change name more formal
* change position of riscv after bpf and modify copyright more uniform
* clear useless ctags file
* change blank with tab in riscv.h
* add riscv python bindings
* add riscv in __init__.py
* fix riscv define value for python binding
* fix test_riscv.py typo
* add missing riscvc in __init__.py of python bindings
* fix alias-insn printer bug, remove useless newline
* change inst print delimter from tab to bankspace for travis
* add riscv tablegen patch
* fix inst output more consistency
* add TableGen patch which fix inst output formal
* crack the effective address output for detail and change register print function
* fix not detail crash bug
* change item declaration position at cs_riscv
* update riscv.py
* change function name more meaningfull
* update python binding makefile
* fix register enum sequence according to riscvgenreginfo.inc
* test function name
* add enum s0/fp in riscv.h & update riscv_const.py
* add register name enum
2019-03-09 00:41:12 +00:00
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fanfuqiang & citypw & porto703 : RISCV architecture.
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2021-12-22 08:29:37 +00:00
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Josh "blacktop" Maine: Arm64 architecture improvements.
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2022-09-30 15:21:58 +00:00
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Finn Wilkinson: AArch64 update to Armv9.2-a (SME + SVE2 support)
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2023-04-24 14:18:07 +00:00
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Billow & Sidneyp : TriCore architecture.
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2024-03-26 05:58:56 +00:00
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Dmitry Sibirtsev: Alpha & HPPA architecture.
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