2014-03-05 15:50:41 +00:00
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# Capstone Disassembly Engine
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2014-03-11 06:14:30 +00:00
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# By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2014
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2013-12-31 15:38:28 +00:00
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2013-12-20 04:43:01 +00:00
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include config.mk
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2014-03-07 09:11:18 +00:00
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include pkgconfig.mk # package version
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2014-05-01 14:53:52 +00:00
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include functions.mk
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2013-11-27 04:11:31 +00:00
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2014-05-01 13:22:25 +00:00
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# Verbose output?
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V ?= 0
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2018-05-16 23:55:44 +00:00
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OS := $(shell uname)
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ifeq ($(OS),Darwin)
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2019-01-25 04:36:37 +00:00
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LIBARCHS ?= x86_64
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2018-05-16 23:55:44 +00:00
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PREFIX ?= /usr/local
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endif
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2014-05-01 13:22:25 +00:00
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ifeq ($(PKG_EXTRA),)
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PKG_VERSION = $(PKG_MAJOR).$(PKG_MINOR)
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else
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PKG_VERSION = $(PKG_MAJOR).$(PKG_MINOR).$(PKG_EXTRA)
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endif
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2014-01-16 13:07:59 +00:00
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ifeq ($(CROSS),)
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RANLIB ?= ranlib
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2019-07-26 16:16:01 +00:00
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else ifeq ($(ANDROID), 1)
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CC = $(CROSS)/../../bin/clang
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AR = $(CROSS)/ar
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RANLIB = $(CROSS)/ranlib
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STRIP = $(CROSS)/strip
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2014-01-16 13:07:59 +00:00
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else
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CC = $(CROSS)gcc
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AR = $(CROSS)ar
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RANLIB = $(CROSS)ranlib
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STRIP = $(CROSS)strip
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endif
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2013-11-27 04:11:31 +00:00
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2014-04-28 23:11:55 +00:00
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ifneq (,$(findstring yes,$(CAPSTONE_DIET)))
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CFLAGS ?= -Os
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CFLAGS += -DCAPSTONE_DIET
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else
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CFLAGS ?= -O3
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endif
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2014-08-17 18:59:05 +00:00
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ifneq (,$(findstring yes,$(CAPSTONE_X86_ATT_DISABLE)))
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CFLAGS += -DCAPSTONE_X86_ATT_DISABLE
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endif
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2019-01-21 13:23:30 +00:00
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CFLAGS += -fPIC -Wall -Wwrite-strings -Wmissing-prototypes -Iinclude
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2014-01-05 15:41:31 +00:00
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2014-04-29 06:25:15 +00:00
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ifeq ($(CAPSTONE_USE_SYS_DYN_MEM),yes)
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2014-05-10 11:26:32 +00:00
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CFLAGS += -DCAPSTONE_USE_SYS_DYN_MEM
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2014-01-05 15:41:31 +00:00
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endif
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2015-04-09 17:28:19 +00:00
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ifeq ($(CAPSTONE_HAS_OSXKERNEL), yes)
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CFLAGS += -DCAPSTONE_HAS_OSXKERNEL
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2015-11-10 22:02:26 +00:00
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SDKROOT ?= $(shell xcodebuild -version -sdk macosx Path)
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CFLAGS += -mmacosx-version-min=10.5 \
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-isysroot$(SDKROOT) \
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-I$(SDKROOT)/System/Library/Frameworks/Kernel.framework/Headers \
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-mkernel \
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-fno-builtin
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2015-04-09 17:28:19 +00:00
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endif
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2013-11-27 14:38:44 +00:00
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PREFIX ?= /usr
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DESTDIR ?=
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2014-04-29 07:00:34 +00:00
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ifndef BUILDDIR
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2014-04-29 08:29:55 +00:00
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BLDIR = .
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2014-04-29 07:00:34 +00:00
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OBJDIR = .
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else
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2014-04-29 22:06:41 +00:00
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BLDIR = $(abspath $(BUILDDIR))
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2014-04-29 08:29:55 +00:00
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OBJDIR = $(BLDIR)/obj
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2014-04-29 07:00:34 +00:00
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endif
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2015-11-08 11:05:41 +00:00
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INCDIR ?= $(PREFIX)/include
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2013-12-25 14:47:28 +00:00
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2014-03-29 13:09:35 +00:00
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UNAME_S := $(shell uname -s)
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2014-04-08 15:34:44 +00:00
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2014-04-14 05:36:46 +00:00
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LIBDIRARCH ?= lib
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# Uncomment the below line to installs x86_64 libs to lib64/ directory.
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# Or better, pass 'LIBDIRARCH=lib64' to 'make install/uninstall' via 'make.sh'.
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#LIBDIRARCH ?= lib64
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LIBDIR = $(DESTDIR)$(PREFIX)/$(LIBDIRARCH)
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2016-10-10 14:54:16 +00:00
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BINDIR = $(DESTDIR)$(PREFIX)/bin
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2013-11-27 14:38:44 +00:00
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2014-03-23 01:19:59 +00:00
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LIBDATADIR = $(LIBDIR)
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2015-07-27 02:03:48 +00:00
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# Don't redefine $LIBDATADIR when global environment variable
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# USE_GENERIC_LIBDATADIR is set. This is used by the pkgsrc framework.
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ifndef USE_GENERIC_LIBDATADIR
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2014-03-23 01:19:59 +00:00
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ifeq ($(UNAME_S), FreeBSD)
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2015-11-08 11:05:41 +00:00
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LIBDATADIR = $(PREFIX)/libdata
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2014-03-23 01:19:59 +00:00
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endif
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2014-03-23 18:10:13 +00:00
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ifeq ($(UNAME_S), DragonFly)
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2015-11-08 11:05:41 +00:00
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LIBDATADIR = $(PREFIX)/libdata
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2014-03-23 18:10:13 +00:00
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endif
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2015-07-27 02:03:48 +00:00
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endif
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2014-03-23 01:19:59 +00:00
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2014-01-17 12:55:21 +00:00
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INSTALL_BIN ?= install
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INSTALL_DATA ?= $(INSTALL_BIN) -m0644
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2014-03-23 01:19:59 +00:00
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INSTALL_LIB ?= $(INSTALL_BIN) -m0755
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2013-11-27 14:38:44 +00:00
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2013-11-27 04:11:31 +00:00
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LIBNAME = capstone
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2013-12-06 16:03:41 +00:00
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2013-12-29 16:15:25 +00:00
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2014-02-28 15:09:04 +00:00
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DEP_ARM =
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2017-10-20 15:17:30 +00:00
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DEP_ARM += $(wildcard arch/ARM/ARM*.inc)
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2014-02-28 15:09:04 +00:00
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LIBOBJ_ARM =
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2014-01-15 08:01:55 +00:00
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ifneq (,$(findstring arm,$(CAPSTONE_ARCHS)))
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CFLAGS += -DCAPSTONE_HAS_ARM
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2017-10-21 13:47:38 +00:00
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LIBSRC_ARM += $(wildcard arch/ARM/ARM*.c)
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LIBOBJ_ARM += $(LIBSRC_ARM:%.c=$(OBJDIR)/%.o)
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2014-02-28 15:09:04 +00:00
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endif
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DEP_ARM64 =
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2017-10-20 15:17:30 +00:00
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DEP_ARM64 += $(wildcard arch/AArch64/AArch64*.inc)
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2014-02-28 15:09:04 +00:00
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LIBOBJ_ARM64 =
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ifneq (,$(findstring aarch64,$(CAPSTONE_ARCHS)))
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CFLAGS += -DCAPSTONE_HAS_ARM64
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2017-10-21 13:47:38 +00:00
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LIBSRC_ARM64 += $(wildcard arch/AArch64/AArch64*.c)
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LIBOBJ_ARM64 += $(LIBSRC_ARM64:%.c=$(OBJDIR)/%.o)
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2014-01-15 08:01:55 +00:00
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endif
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2014-02-28 15:09:04 +00:00
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2015-08-03 16:45:08 +00:00
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DEP_M68K =
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2019-03-02 02:53:30 +00:00
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DEP_M68K += $(wildcard arch/M68K/M68K*.inc)
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2017-10-20 15:17:30 +00:00
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DEP_M68K += $(wildcard arch/M68K/M68K*.h)
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2015-08-03 16:45:08 +00:00
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LIBOBJ_M68K =
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ifneq (,$(findstring m68k,$(CAPSTONE_ARCHS)))
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CFLAGS += -DCAPSTONE_HAS_M68K
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2017-10-21 13:47:38 +00:00
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LIBSRC_M68K += $(wildcard arch/M68K/M68K*.c)
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LIBOBJ_M68K += $(LIBSRC_M68K:%.c=$(OBJDIR)/%.o)
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2015-08-03 16:45:08 +00:00
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endif
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2014-02-28 15:09:04 +00:00
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DEP_MIPS =
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2017-10-20 15:17:30 +00:00
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DEP_MIPS += $(wildcard arch/Mips/Mips*.inc)
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2014-02-28 15:09:04 +00:00
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LIBOBJ_MIPS =
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2014-01-14 15:08:20 +00:00
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ifneq (,$(findstring mips,$(CAPSTONE_ARCHS)))
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CFLAGS += -DCAPSTONE_HAS_MIPS
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2017-10-21 13:47:38 +00:00
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LIBSRC_MIPS += $(wildcard arch/Mips/Mips*.c)
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LIBOBJ_MIPS += $(LIBSRC_MIPS:%.c=$(OBJDIR)/%.o)
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2014-01-14 15:08:20 +00:00
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endif
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2014-02-28 15:09:04 +00:00
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DEP_PPC =
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2017-10-20 15:17:30 +00:00
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DEP_PPC += $(wildcard arch/PowerPC/PPC*.inc)
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2014-02-28 15:09:04 +00:00
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LIBOBJ_PPC =
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2013-12-29 16:15:25 +00:00
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ifneq (,$(findstring powerpc,$(CAPSTONE_ARCHS)))
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2014-01-09 04:06:44 +00:00
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CFLAGS += -DCAPSTONE_HAS_POWERPC
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2017-10-21 13:47:38 +00:00
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LIBSRC_PPC += $(wildcard arch/PowerPC/PPC*.c)
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LIBOBJ_PPC += $(LIBSRC_PPC:%.c=$(OBJDIR)/%.o)
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2013-12-29 16:15:25 +00:00
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endif
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2014-02-28 15:09:04 +00:00
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2014-03-10 03:58:57 +00:00
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DEP_SPARC =
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2017-10-20 15:17:30 +00:00
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DEP_SPARC += $(wildcard arch/Sparc/Sparc*.inc)
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2014-03-10 03:58:57 +00:00
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LIBOBJ_SPARC =
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ifneq (,$(findstring sparc,$(CAPSTONE_ARCHS)))
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CFLAGS += -DCAPSTONE_HAS_SPARC
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2017-10-21 13:47:38 +00:00
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LIBSRC_SPARC += $(wildcard arch/Sparc/Sparc*.c)
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LIBOBJ_SPARC += $(LIBSRC_SPARC:%.c=$(OBJDIR)/%.o)
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2014-03-10 03:58:57 +00:00
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endif
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2014-03-23 00:35:45 +00:00
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DEP_SYSZ =
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2017-10-20 15:17:30 +00:00
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DEP_SYSZ += $(wildcard arch/SystemZ/SystemZ*.inc)
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2014-03-23 00:35:45 +00:00
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LIBOBJ_SYSZ =
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ifneq (,$(findstring systemz,$(CAPSTONE_ARCHS)))
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CFLAGS += -DCAPSTONE_HAS_SYSZ
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2017-10-21 13:47:38 +00:00
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LIBSRC_SYSZ += $(wildcard arch/SystemZ/SystemZ*.c)
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LIBOBJ_SYSZ += $(LIBSRC_SYSZ:%.c=$(OBJDIR)/%.o)
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2014-03-23 00:35:45 +00:00
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endif
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2014-03-25 15:20:41 +00:00
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# by default, we compile full X86 instruction sets
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2014-03-27 02:54:44 +00:00
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X86_REDUCE =
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ifneq (,$(findstring yes,$(CAPSTONE_X86_REDUCE)))
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X86_REDUCE = _reduce
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2014-03-28 02:28:57 +00:00
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CFLAGS += -DCAPSTONE_X86_REDUCE -Os
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2014-03-25 15:20:41 +00:00
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endif
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2019-02-26 07:19:51 +00:00
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2014-02-28 15:09:04 +00:00
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DEP_X86 =
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2019-02-26 07:19:51 +00:00
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DEP_X86 += $(wildcard arch/X86/X86*.inc)
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2014-02-28 15:09:04 +00:00
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LIBOBJ_X86 =
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ifneq (,$(findstring x86,$(CAPSTONE_ARCHS)))
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CFLAGS += -DCAPSTONE_HAS_X86
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2014-04-29 07:00:34 +00:00
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LIBOBJ_X86 += $(OBJDIR)/arch/X86/X86DisassemblerDecoder.o
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LIBOBJ_X86 += $(OBJDIR)/arch/X86/X86Disassembler.o
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2019-02-26 13:51:30 +00:00
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LIBOBJ_X86 += $(OBJDIR)/arch/X86/X86InstPrinterCommon.o
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2014-04-29 07:00:34 +00:00
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LIBOBJ_X86 += $(OBJDIR)/arch/X86/X86IntelInstPrinter.o
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2014-05-14 04:26:53 +00:00
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# assembly syntax is irrelevant in Diet mode, when this info is suppressed
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ifeq (,$(findstring yes,$(CAPSTONE_DIET)))
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2014-08-17 18:59:05 +00:00
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ifeq (,$(findstring yes,$(CAPSTONE_X86_ATT_DISABLE)))
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2014-04-29 07:00:34 +00:00
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LIBOBJ_X86 += $(OBJDIR)/arch/X86/X86ATTInstPrinter.o
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2014-08-17 18:59:05 +00:00
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endif
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2014-05-14 04:26:53 +00:00
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endif
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2014-04-29 07:00:34 +00:00
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LIBOBJ_X86 += $(OBJDIR)/arch/X86/X86Mapping.o
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LIBOBJ_X86 += $(OBJDIR)/arch/X86/X86Module.o
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2013-12-20 06:57:12 +00:00
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endif
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2013-12-29 16:15:25 +00:00
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2014-05-26 15:02:48 +00:00
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DEP_XCORE =
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2017-10-20 15:17:30 +00:00
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DEP_XCORE += $(wildcard arch/XCore/XCore*.inc)
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2014-05-26 15:02:48 +00:00
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LIBOBJ_XCORE =
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ifneq (,$(findstring xcore,$(CAPSTONE_ARCHS)))
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CFLAGS += -DCAPSTONE_HAS_XCORE
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2017-10-21 13:47:38 +00:00
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LIBSRC_XCORE += $(wildcard arch/XCore/XCore*.c)
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LIBOBJ_XCORE += $(LIBSRC_XCORE:%.c=$(OBJDIR)/%.o)
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2014-05-26 15:02:48 +00:00
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endif
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2016-05-03 12:52:11 +00:00
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DEP_TMS320C64X =
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2017-10-20 15:17:30 +00:00
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DEP_TMS320C64X += $(wildcard arch/TMS320C64x/TMS320C64x*.inc)
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2016-05-03 12:52:11 +00:00
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LIBOBJ_TMS320C64X =
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ifneq (,$(findstring tms320c64x,$(CAPSTONE_ARCHS)))
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CFLAGS += -DCAPSTONE_HAS_TMS320C64X
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2017-10-21 13:47:38 +00:00
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LIBSRC_TMS320C64X += $(wildcard arch/TMS320C64x/TMS320C64x*.c)
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LIBOBJ_TMS320C64X += $(LIBSRC_TMS320C64X:%.c=$(OBJDIR)/%.o)
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2016-05-03 12:52:11 +00:00
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endif
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M680X: Target ready for pull request (#1034)
* Added new M680X target. Supports M6800/1/2/3/9, HD6301
* M680X: Reformat for coding guide lines. Set alphabetical order in HACK.TXT
* M680X: Prepare for python binding. Move cs_m680x, m680x_insn to m680x_info. Chec
> k cpu type, no default.
* M680X: Add python bindings. Added python tests.
* M680X: Added cpu types to usage message.
* cstool: Avoid segfault for invalid <arch+mode>.
* Make test_m680x.c/test_m680x.py output comparable (diff params: -bu). Keep xprint.py untouched.
* M680X: Update CMake/make for m680x support. Update .gitignore.
* M680X: Reduce compiler warnings.
* M680X: Reduce compiler warnings.
* M680X: Reduce compiler warnings.
* M680X: Make test_m680x.c/test_m680x.py output comparable (diff params: -bu).
* M680X: Add ocaml bindings and tests.
* M680X: Add java bindings and tests.
* M680X: Added tests for all indexed addressing modes. C/Python/Ocaml
* M680X: Naming, use page1 for PAGE1 instructions (without prefix).
* M680X: Naming, use page1 for PAGE1 instructions (without prefix).
* M680X: Used M680X_FIRST_OP_IN_MNEM in tests C/python/java/ocaml.
* M680X: Added access property to cs_m680x_op.
* M680X: Added operand size.
* M680X: Remove compiler warnings.
* M680X: Added READ/WRITE access property per operator.
* M680X: Make reg_inherent_hdlr independent of CPU type.
* M680X: Add HD6309 support + bug fixes
* M680X: Remove errors and warning.
* M680X: Add Bcc/LBcc to group BRAREL (relative branch).
* M680X: Add group JUMP to BVS/BVC/LBVS/LBVC. Remove BRAREL from BRN/LBRN.
* M680X: Remove LBRN from group BRAREL.
* M680X: Refactored cpu_type initialization for better readability.
* M680X: Add two operands for insn having two reg. in mnemonic. e.g. ABX.
* M680X: Remove typo in cstool.c
* M680X: Some format improvements in changed_regs.
* M680X: Remove insn id string list from tests (C/python/java/ocaml).
* M680X: SEXW, set access of reg. D to WRITE.
* M680X: Sort changed_regs in increasing m680x_insn order.
* M680X: Add M68HC11 support + Reduced from two to one INDEXED operand.
* M680X: cstool, also write '(in mnemonic)' for second reg. operand.
* M680X: Add BRN/LBRN to group JUMP and BRAREL.
* M680X: For Bcc/LBcc/BRSET/BRCLR set reg. CC to read access.
* M680X: Correctly print negative immediate values with option CS_OPT_UNSIGNED.
* M680X: Rename some instruction handlers.
* M680X: Add M68HC05 support.
* M680X: Dont print prefix '<' for direct addr. mode.
* M680X: Add M68HC08 support + resorted tables + bug fixes.
* M680X: Add Freescale HCS08 support.
* M680X: Changed group names, avoid spaces.
* M680X: Refactoring, rename addessing mode handlers.
* M680X: indexed addr. mode, changed pre/post inc-/decrement representation.
* M680X: Rename some M6809/HD6309 specific functions.
* M680X: Add CPU12 (68HC12/HCS12) support.
* M680X: Correctly display illegal instruction as FCB .
* M680X: bugfix: BRA/BRN/BSR/LBRA/LBRN/LBSR does not read CC reg.
* M680X: bugfix: Correctly check for sufficient code size for M6809 indexed addressing.
* M680X: Better support for changing insn id within handler for addessing mode.
* M680X: Remove warnings.
* M680X: In set_changed_regs_read_write_counts use own access_mode.
* M680X: Split cpu specific tables into separate *.inc files.
* M680X: Remove warnings.
* M680X: Removed address_mode. Addressing mode is available in operand.type
* M680X: Bugfix: BSET/BCLR/BRSET/BRCLR correct read/modify CC reg.
* M680X: Remove register TMP1. It is first visible in CPU12X.
* M680X: Performance improvement + bug fixes.
* M680X: Performance improvement, make cpu_tables const static.
* M680X: Simplify operand decoding by using two handlers.
* M680X: Replace M680X_OP_INDEX by M680X_OP_CONSTANT + bugfix in java/python/ocaml bindings.
* M680X: Format with astyle.
* M680X: Update documentation.
* M680X: Corrected author for m680x specific files.
* M680X: Make max. number of architectures single source.
2017-10-21 13:44:36 +00:00
|
|
|
DEP_M680X =
|
2017-10-21 07:05:02 +00:00
|
|
|
DEP_M680X += $(wildcard arch/M680X/*.inc)
|
|
|
|
DEP_M680X += $(wildcard arch/M680X/M680X*.h)
|
M680X: Target ready for pull request (#1034)
* Added new M680X target. Supports M6800/1/2/3/9, HD6301
* M680X: Reformat for coding guide lines. Set alphabetical order in HACK.TXT
* M680X: Prepare for python binding. Move cs_m680x, m680x_insn to m680x_info. Chec
> k cpu type, no default.
* M680X: Add python bindings. Added python tests.
* M680X: Added cpu types to usage message.
* cstool: Avoid segfault for invalid <arch+mode>.
* Make test_m680x.c/test_m680x.py output comparable (diff params: -bu). Keep xprint.py untouched.
* M680X: Update CMake/make for m680x support. Update .gitignore.
* M680X: Reduce compiler warnings.
* M680X: Reduce compiler warnings.
* M680X: Reduce compiler warnings.
* M680X: Make test_m680x.c/test_m680x.py output comparable (diff params: -bu).
* M680X: Add ocaml bindings and tests.
* M680X: Add java bindings and tests.
* M680X: Added tests for all indexed addressing modes. C/Python/Ocaml
* M680X: Naming, use page1 for PAGE1 instructions (without prefix).
* M680X: Naming, use page1 for PAGE1 instructions (without prefix).
* M680X: Used M680X_FIRST_OP_IN_MNEM in tests C/python/java/ocaml.
* M680X: Added access property to cs_m680x_op.
* M680X: Added operand size.
* M680X: Remove compiler warnings.
* M680X: Added READ/WRITE access property per operator.
* M680X: Make reg_inherent_hdlr independent of CPU type.
* M680X: Add HD6309 support + bug fixes
* M680X: Remove errors and warning.
* M680X: Add Bcc/LBcc to group BRAREL (relative branch).
* M680X: Add group JUMP to BVS/BVC/LBVS/LBVC. Remove BRAREL from BRN/LBRN.
* M680X: Remove LBRN from group BRAREL.
* M680X: Refactored cpu_type initialization for better readability.
* M680X: Add two operands for insn having two reg. in mnemonic. e.g. ABX.
* M680X: Remove typo in cstool.c
* M680X: Some format improvements in changed_regs.
* M680X: Remove insn id string list from tests (C/python/java/ocaml).
* M680X: SEXW, set access of reg. D to WRITE.
* M680X: Sort changed_regs in increasing m680x_insn order.
* M680X: Add M68HC11 support + Reduced from two to one INDEXED operand.
* M680X: cstool, also write '(in mnemonic)' for second reg. operand.
* M680X: Add BRN/LBRN to group JUMP and BRAREL.
* M680X: For Bcc/LBcc/BRSET/BRCLR set reg. CC to read access.
* M680X: Correctly print negative immediate values with option CS_OPT_UNSIGNED.
* M680X: Rename some instruction handlers.
* M680X: Add M68HC05 support.
* M680X: Dont print prefix '<' for direct addr. mode.
* M680X: Add M68HC08 support + resorted tables + bug fixes.
* M680X: Add Freescale HCS08 support.
* M680X: Changed group names, avoid spaces.
* M680X: Refactoring, rename addessing mode handlers.
* M680X: indexed addr. mode, changed pre/post inc-/decrement representation.
* M680X: Rename some M6809/HD6309 specific functions.
* M680X: Add CPU12 (68HC12/HCS12) support.
* M680X: Correctly display illegal instruction as FCB .
* M680X: bugfix: BRA/BRN/BSR/LBRA/LBRN/LBSR does not read CC reg.
* M680X: bugfix: Correctly check for sufficient code size for M6809 indexed addressing.
* M680X: Better support for changing insn id within handler for addessing mode.
* M680X: Remove warnings.
* M680X: In set_changed_regs_read_write_counts use own access_mode.
* M680X: Split cpu specific tables into separate *.inc files.
* M680X: Remove warnings.
* M680X: Removed address_mode. Addressing mode is available in operand.type
* M680X: Bugfix: BSET/BCLR/BRSET/BRCLR correct read/modify CC reg.
* M680X: Remove register TMP1. It is first visible in CPU12X.
* M680X: Performance improvement + bug fixes.
* M680X: Performance improvement, make cpu_tables const static.
* M680X: Simplify operand decoding by using two handlers.
* M680X: Replace M680X_OP_INDEX by M680X_OP_CONSTANT + bugfix in java/python/ocaml bindings.
* M680X: Format with astyle.
* M680X: Update documentation.
* M680X: Corrected author for m680x specific files.
* M680X: Make max. number of architectures single source.
2017-10-21 13:44:36 +00:00
|
|
|
|
|
|
|
LIBOBJ_M680X =
|
|
|
|
ifneq (,$(findstring m680x,$(CAPSTONE_ARCHS)))
|
|
|
|
CFLAGS += -DCAPSTONE_HAS_M680X
|
2017-10-21 07:05:02 +00:00
|
|
|
LIBSRC_M680X += $(wildcard arch/M680X/*.c)
|
|
|
|
LIBOBJ_M680X += $(LIBSRC_M680X:%.c=$(OBJDIR)/%.o)
|
M680X: Target ready for pull request (#1034)
* Added new M680X target. Supports M6800/1/2/3/9, HD6301
* M680X: Reformat for coding guide lines. Set alphabetical order in HACK.TXT
* M680X: Prepare for python binding. Move cs_m680x, m680x_insn to m680x_info. Chec
> k cpu type, no default.
* M680X: Add python bindings. Added python tests.
* M680X: Added cpu types to usage message.
* cstool: Avoid segfault for invalid <arch+mode>.
* Make test_m680x.c/test_m680x.py output comparable (diff params: -bu). Keep xprint.py untouched.
* M680X: Update CMake/make for m680x support. Update .gitignore.
* M680X: Reduce compiler warnings.
* M680X: Reduce compiler warnings.
* M680X: Reduce compiler warnings.
* M680X: Make test_m680x.c/test_m680x.py output comparable (diff params: -bu).
* M680X: Add ocaml bindings and tests.
* M680X: Add java bindings and tests.
* M680X: Added tests for all indexed addressing modes. C/Python/Ocaml
* M680X: Naming, use page1 for PAGE1 instructions (without prefix).
* M680X: Naming, use page1 for PAGE1 instructions (without prefix).
* M680X: Used M680X_FIRST_OP_IN_MNEM in tests C/python/java/ocaml.
* M680X: Added access property to cs_m680x_op.
* M680X: Added operand size.
* M680X: Remove compiler warnings.
* M680X: Added READ/WRITE access property per operator.
* M680X: Make reg_inherent_hdlr independent of CPU type.
* M680X: Add HD6309 support + bug fixes
* M680X: Remove errors and warning.
* M680X: Add Bcc/LBcc to group BRAREL (relative branch).
* M680X: Add group JUMP to BVS/BVC/LBVS/LBVC. Remove BRAREL from BRN/LBRN.
* M680X: Remove LBRN from group BRAREL.
* M680X: Refactored cpu_type initialization for better readability.
* M680X: Add two operands for insn having two reg. in mnemonic. e.g. ABX.
* M680X: Remove typo in cstool.c
* M680X: Some format improvements in changed_regs.
* M680X: Remove insn id string list from tests (C/python/java/ocaml).
* M680X: SEXW, set access of reg. D to WRITE.
* M680X: Sort changed_regs in increasing m680x_insn order.
* M680X: Add M68HC11 support + Reduced from two to one INDEXED operand.
* M680X: cstool, also write '(in mnemonic)' for second reg. operand.
* M680X: Add BRN/LBRN to group JUMP and BRAREL.
* M680X: For Bcc/LBcc/BRSET/BRCLR set reg. CC to read access.
* M680X: Correctly print negative immediate values with option CS_OPT_UNSIGNED.
* M680X: Rename some instruction handlers.
* M680X: Add M68HC05 support.
* M680X: Dont print prefix '<' for direct addr. mode.
* M680X: Add M68HC08 support + resorted tables + bug fixes.
* M680X: Add Freescale HCS08 support.
* M680X: Changed group names, avoid spaces.
* M680X: Refactoring, rename addessing mode handlers.
* M680X: indexed addr. mode, changed pre/post inc-/decrement representation.
* M680X: Rename some M6809/HD6309 specific functions.
* M680X: Add CPU12 (68HC12/HCS12) support.
* M680X: Correctly display illegal instruction as FCB .
* M680X: bugfix: BRA/BRN/BSR/LBRA/LBRN/LBSR does not read CC reg.
* M680X: bugfix: Correctly check for sufficient code size for M6809 indexed addressing.
* M680X: Better support for changing insn id within handler for addessing mode.
* M680X: Remove warnings.
* M680X: In set_changed_regs_read_write_counts use own access_mode.
* M680X: Split cpu specific tables into separate *.inc files.
* M680X: Remove warnings.
* M680X: Removed address_mode. Addressing mode is available in operand.type
* M680X: Bugfix: BSET/BCLR/BRSET/BRCLR correct read/modify CC reg.
* M680X: Remove register TMP1. It is first visible in CPU12X.
* M680X: Performance improvement + bug fixes.
* M680X: Performance improvement, make cpu_tables const static.
* M680X: Simplify operand decoding by using two handlers.
* M680X: Replace M680X_OP_INDEX by M680X_OP_CONSTANT + bugfix in java/python/ocaml bindings.
* M680X: Format with astyle.
* M680X: Update documentation.
* M680X: Corrected author for m680x specific files.
* M680X: Make max. number of architectures single source.
2017-10-21 13:44:36 +00:00
|
|
|
endif
|
2016-05-03 12:52:11 +00:00
|
|
|
|
2018-03-31 09:29:22 +00:00
|
|
|
|
|
|
|
DEP_EVM =
|
|
|
|
DEP_EVM += $(wildcard arch/EVM/EVM*.inc)
|
|
|
|
|
|
|
|
LIBOBJ_EVM =
|
|
|
|
ifneq (,$(findstring evm,$(CAPSTONE_ARCHS)))
|
|
|
|
CFLAGS += -DCAPSTONE_HAS_EVM
|
|
|
|
LIBSRC_EVM += $(wildcard arch/EVM/EVM*.c)
|
|
|
|
LIBOBJ_EVM += $(LIBSRC_EVM:%.c=$(OBJDIR)/%.o)
|
2014-05-26 15:02:48 +00:00
|
|
|
endif
|
|
|
|
|
RISCV support ISRV32/ISRV64 (#1401)
* Added RISCV dir to contain the RISCV architecture engine code. Adding the TableGen files generated from llvm-tblgen. Add Disassembler.h
* Started working on RISCVDisassembler.c - RISCV_init(), RISCVDisassembler_getInstruction, and RISCV_getInstruction
* Added all functions to RISCVDisassembler.c and needed modifications to RISCVGenDisassemblerTables.inc. Add and modified RISCVGenSubtargetInfo.inc. Start creation of RISCVInstPrinter.h
* Finished RISCVGenAsmWriter.inc. Finished RISCVGenRegisterInfo.inc. Minor fixes to RISCVDisassembler.c. Working on RISCVInstPrinter
* Finished RISCVInstPrinter, RISCVMapping, RISCVBaseInfo, RISCVGenInstrInfo.inc, RISCVModule.c. Working on riscv.h
* Backport it from: https://github.com/porto703/capstone/commit/0db412ce3bed9d963caf598a2cb7dc76b41a5a2b
* All RISCV files added. Compiled correctly and initial test for ADD, ADDI, AND works properly.
* Add refactored cs.c for RISCV
* Testing all I instructions in test_riscv.c
* Modify the orignal backport for RISCVGenRegisterInfo.inc, capstone.h and test_iter to work w/ the current code strcuture
* Fix issue with RISCVGenRegisterInfo.inc - RISCVRegDesc[] (Excess elements in struct initializer). Added RISCV tests to test_iter.c
* fixed bug related to incorrect initialization of memory after malloc
* fix compile bug
* Fix compile errors.
* move riscv.h to include/capstone
* fix indentation issues
* fix coding style issues
* Fix indentation issues
* fix coding style
* Move variable declaration to the top of the block
* Fix coding indentation
* Move some stuff into RISCVMappingInsn.inc
* Fix code sytle
* remove cs_mode support for RISCV
* update asmwriter-inc to LLVM upstream
* update the .inc files to riscv upstream
* update riscv disassembler function for suport 16bit instructions
* update printer & tablegen inc files which have fixed arguments mismatch
* update headers and mapping source
* add riscv architecture specific test code
* fix all RISCV tons of compiler errors
* pass final tests
* add riscv tablegen patchs
* merge with upstream/next
* fix cstool missing riscv file
* fix root Makefile
* add new TableGen patchs for riscv
* fix cmakefile.txt of missing one riscv file
* fix declaration conflict
* fix incompatible declaration type
* change riscvc from arch to mode
* fix test_riscv warnning
* fix code style and add riscv part of test_basic
* add RISCV64 mode
* add suite for riscv
* crack fuzz test
* fix getfeaturebits test add riscvc
* fix test missing const qualifier warnning
* fix testcase type mismatch
* fix return value missing
* change getfeaturebits test
* add test cs files
* using a winder type contain the decode string
* fix a copy typo
* remove useless mode for riscv
* change cs file blank type
* add repo for update_riscv & fix cstool missing riscv mode
* fix typo
* add riscv for cstool useage
* add TableGen patch for riscv asmwriter
* clean ctags file
* remove black comment line
* fix fuzz related something
* fix missing RISCV string of fuzz
* update readme, etc..
* add riscv *.s.cs file
* add riscv *.s.cs file & clear ctags
* clear useless array declarations at capstone_test
* update to 5e4069f
* update readme change name more formal
* change position of riscv after bpf and modify copyright more uniform
* clear useless ctags file
* change blank with tab in riscv.h
* add riscv python bindings
* add riscv in __init__.py
* fix riscv define value for python binding
* fix test_riscv.py typo
* add missing riscvc in __init__.py of python bindings
* fix alias-insn printer bug, remove useless newline
* change inst print delimter from tab to bankspace for travis
* add riscv tablegen patch
* fix inst output more consistency
* add TableGen patch which fix inst output formal
* crack the effective address output for detail and change register print function
* fix not detail crash bug
* change item declaration position at cs_riscv
* update riscv.py
* change function name more meaningfull
* update python binding makefile
* fix register enum sequence according to riscvgenreginfo.inc
* test function name
* add enum s0/fp in riscv.h & update riscv_const.py
* add register name enum
2019-03-09 00:41:12 +00:00
|
|
|
DEP_RISCV =
|
|
|
|
DEP_RISCV += $(wildcard arch/RISCV/RISCV*.inc)
|
|
|
|
|
|
|
|
LIBOBJ_RISCV =
|
|
|
|
ifneq (,$(findstring riscv,$(CAPSTONE_ARCHS)))
|
|
|
|
CFLAGS += -DCAPSTONE_HAS_RISCV
|
|
|
|
LIBSRC_RISCV += $(wildcard arch/RISCV/RISCV*.c)
|
|
|
|
LIBOBJ_RISCV += $(LIBSRC_RISCV:%.c=$(OBJDIR)/%.o)
|
|
|
|
endif
|
|
|
|
|
2019-02-01 15:03:47 +00:00
|
|
|
DEP_WASM =
|
|
|
|
DEP_WASM += $(wildcard arch/WASM/WASM*.inc)
|
|
|
|
|
|
|
|
LIBOBJ_WASM =
|
|
|
|
ifneq (,$(findstring wasm,$(CAPSTONE_ARCHS)))
|
|
|
|
CFLAGS += -DCAPSTONE_HAS_WASM
|
|
|
|
LIBSRC_WASM += $(wildcard arch/WASM/WASM*.c)
|
|
|
|
LIBOBJ_WASM += $(LIBSRC_WASM:%.c=$(OBJDIR)/%.o)
|
|
|
|
endif
|
|
|
|
|
2014-05-26 15:02:48 +00:00
|
|
|
|
2018-12-02 20:39:41 +00:00
|
|
|
DEP_MOS65XX =
|
|
|
|
DEP_MOS65XX += $(wildcard arch/MOS65XX/MOS65XX*.inc)
|
|
|
|
|
|
|
|
LIBOBJ_MOS65XX =
|
|
|
|
ifneq (,$(findstring mos65xx,$(CAPSTONE_ARCHS)))
|
|
|
|
CFLAGS += -DCAPSTONE_HAS_MOS65XX
|
|
|
|
LIBSRC_MOS65XX += $(wildcard arch/MOS65XX/MOS65XX*.c)
|
|
|
|
LIBOBJ_MOS65XX += $(LIBSRC_MOS65XX:%.c=$(OBJDIR)/%.o)
|
|
|
|
endif
|
|
|
|
|
|
|
|
|
2019-02-18 09:39:51 +00:00
|
|
|
DEP_BPF =
|
|
|
|
DEP_BPF += $(wildcard arch/BPF/BPF*.inc)
|
|
|
|
|
|
|
|
LIBOBJ_BPF =
|
|
|
|
ifneq (,$(findstring bpf,$(CAPSTONE_ARCHS)))
|
|
|
|
CFLAGS += -DCAPSTONE_HAS_BPF
|
|
|
|
LIBSRC_BPF += $(wildcard arch/BPF/BPF*.c)
|
|
|
|
LIBOBJ_BPF += $(LIBSRC_BPF:%.c=$(OBJDIR)/%.o)
|
|
|
|
endif
|
|
|
|
|
|
|
|
|
2014-02-28 15:09:04 +00:00
|
|
|
LIBOBJ =
|
2014-04-29 07:00:34 +00:00
|
|
|
LIBOBJ += $(OBJDIR)/cs.o $(OBJDIR)/utils.o $(OBJDIR)/SStream.o $(OBJDIR)/MCInstrDesc.o $(OBJDIR)/MCRegisterInfo.o
|
RISCV support ISRV32/ISRV64 (#1401)
* Added RISCV dir to contain the RISCV architecture engine code. Adding the TableGen files generated from llvm-tblgen. Add Disassembler.h
* Started working on RISCVDisassembler.c - RISCV_init(), RISCVDisassembler_getInstruction, and RISCV_getInstruction
* Added all functions to RISCVDisassembler.c and needed modifications to RISCVGenDisassemblerTables.inc. Add and modified RISCVGenSubtargetInfo.inc. Start creation of RISCVInstPrinter.h
* Finished RISCVGenAsmWriter.inc. Finished RISCVGenRegisterInfo.inc. Minor fixes to RISCVDisassembler.c. Working on RISCVInstPrinter
* Finished RISCVInstPrinter, RISCVMapping, RISCVBaseInfo, RISCVGenInstrInfo.inc, RISCVModule.c. Working on riscv.h
* Backport it from: https://github.com/porto703/capstone/commit/0db412ce3bed9d963caf598a2cb7dc76b41a5a2b
* All RISCV files added. Compiled correctly and initial test for ADD, ADDI, AND works properly.
* Add refactored cs.c for RISCV
* Testing all I instructions in test_riscv.c
* Modify the orignal backport for RISCVGenRegisterInfo.inc, capstone.h and test_iter to work w/ the current code strcuture
* Fix issue with RISCVGenRegisterInfo.inc - RISCVRegDesc[] (Excess elements in struct initializer). Added RISCV tests to test_iter.c
* fixed bug related to incorrect initialization of memory after malloc
* fix compile bug
* Fix compile errors.
* move riscv.h to include/capstone
* fix indentation issues
* fix coding style issues
* Fix indentation issues
* fix coding style
* Move variable declaration to the top of the block
* Fix coding indentation
* Move some stuff into RISCVMappingInsn.inc
* Fix code sytle
* remove cs_mode support for RISCV
* update asmwriter-inc to LLVM upstream
* update the .inc files to riscv upstream
* update riscv disassembler function for suport 16bit instructions
* update printer & tablegen inc files which have fixed arguments mismatch
* update headers and mapping source
* add riscv architecture specific test code
* fix all RISCV tons of compiler errors
* pass final tests
* add riscv tablegen patchs
* merge with upstream/next
* fix cstool missing riscv file
* fix root Makefile
* add new TableGen patchs for riscv
* fix cmakefile.txt of missing one riscv file
* fix declaration conflict
* fix incompatible declaration type
* change riscvc from arch to mode
* fix test_riscv warnning
* fix code style and add riscv part of test_basic
* add RISCV64 mode
* add suite for riscv
* crack fuzz test
* fix getfeaturebits test add riscvc
* fix test missing const qualifier warnning
* fix testcase type mismatch
* fix return value missing
* change getfeaturebits test
* add test cs files
* using a winder type contain the decode string
* fix a copy typo
* remove useless mode for riscv
* change cs file blank type
* add repo for update_riscv & fix cstool missing riscv mode
* fix typo
* add riscv for cstool useage
* add TableGen patch for riscv asmwriter
* clean ctags file
* remove black comment line
* fix fuzz related something
* fix missing RISCV string of fuzz
* update readme, etc..
* add riscv *.s.cs file
* add riscv *.s.cs file & clear ctags
* clear useless array declarations at capstone_test
* update to 5e4069f
* update readme change name more formal
* change position of riscv after bpf and modify copyright more uniform
* clear useless ctags file
* change blank with tab in riscv.h
* add riscv python bindings
* add riscv in __init__.py
* fix riscv define value for python binding
* fix test_riscv.py typo
* add missing riscvc in __init__.py of python bindings
* fix alias-insn printer bug, remove useless newline
* change inst print delimter from tab to bankspace for travis
* add riscv tablegen patch
* fix inst output more consistency
* add TableGen patch which fix inst output formal
* crack the effective address output for detail and change register print function
* fix not detail crash bug
* change item declaration position at cs_riscv
* update riscv.py
* change function name more meaningfull
* update python binding makefile
* fix register enum sequence according to riscvgenreginfo.inc
* test function name
* add enum s0/fp in riscv.h & update riscv_const.py
* add register name enum
2019-03-09 00:41:12 +00:00
|
|
|
LIBOBJ += $(LIBOBJ_ARM) $(LIBOBJ_ARM64) $(LIBOBJ_M68K) $(LIBOBJ_MIPS) $(LIBOBJ_PPC) $(LIBOBJ_RISCV) $(LIBOBJ_SPARC) $(LIBOBJ_SYSZ)
|
2019-02-18 09:39:51 +00:00
|
|
|
LIBOBJ += $(LIBOBJ_X86) $(LIBOBJ_XCORE) $(LIBOBJ_TMS320C64X) $(LIBOBJ_M680X) $(LIBOBJ_EVM) $(LIBOBJ_MOS65XX) $(LIBOBJ_WASM) $(LIBOBJ_BPF)
|
2014-04-29 07:00:34 +00:00
|
|
|
LIBOBJ += $(OBJDIR)/MCInst.o
|
2013-11-27 04:11:31 +00:00
|
|
|
|
2014-02-28 15:09:04 +00:00
|
|
|
|
2015-05-21 04:58:38 +00:00
|
|
|
ifeq ($(PKG_EXTRA),)
|
|
|
|
PKGCFGDIR = $(LIBDATADIR)/pkgconfig
|
|
|
|
else
|
2014-04-12 15:10:46 +00:00
|
|
|
PKGCFGDIR ?= $(LIBDATADIR)/pkgconfig
|
2017-04-14 10:43:06 +00:00
|
|
|
ifeq ($(PKGCFGDIR),)
|
|
|
|
PKGCFGDIR = $(LIBDATADIR)/pkgconfig
|
|
|
|
endif
|
2015-05-21 04:58:38 +00:00
|
|
|
endif
|
|
|
|
|
2015-02-24 03:55:55 +00:00
|
|
|
API_MAJOR=$(shell echo `grep -e CS_API_MAJOR include/capstone/capstone.h | grep -v = | awk '{print $$3}'` | awk '{print $$1}')
|
2014-03-17 09:31:33 +00:00
|
|
|
VERSION_EXT =
|
2014-02-24 07:17:40 +00:00
|
|
|
|
2017-02-06 12:24:33 +00:00
|
|
|
IS_APPLE := $(shell $(CC) -dM -E - < /dev/null 2> /dev/null | grep __apple_build_version__ | wc -l | tr -d " ")
|
2014-05-01 12:14:57 +00:00
|
|
|
ifeq ($(IS_APPLE),1)
|
2018-07-27 16:24:14 +00:00
|
|
|
# on MacOS, do not build in Universal format by default
|
|
|
|
MACOS_UNIVERSAL ?= no
|
2017-09-05 14:45:48 +00:00
|
|
|
ifeq ($(MACOS_UNIVERSAL),yes)
|
|
|
|
CFLAGS += $(foreach arch,$(LIBARCHS),-arch $(arch))
|
|
|
|
LDFLAGS += $(foreach arch,$(LIBARCHS),-arch $(arch))
|
|
|
|
endif
|
2013-11-27 04:11:31 +00:00
|
|
|
EXT = dylib
|
2014-02-04 07:37:55 +00:00
|
|
|
VERSION_EXT = $(API_MAJOR).$(EXT)
|
2014-05-14 07:13:36 +00:00
|
|
|
$(LIBNAME)_LDFLAGS += -dynamiclib -install_name lib$(LIBNAME).$(VERSION_EXT) -current_version $(PKG_MAJOR).$(PKG_MINOR).$(PKG_EXTRA) -compatibility_version $(PKG_MAJOR).$(PKG_MINOR)
|
2013-12-25 15:54:45 +00:00
|
|
|
AR_EXT = a
|
2014-04-12 10:02:55 +00:00
|
|
|
# Homebrew wants to make sure its formula does not disable FORTIFY_SOURCE
|
2014-04-29 06:25:15 +00:00
|
|
|
# However, this is not really necessary because 'CAPSTONE_USE_SYS_DYN_MEM=yes' by default
|
2014-03-29 14:36:05 +00:00
|
|
|
ifneq ($(HOMEBREW_CAPSTONE),1)
|
2014-04-29 06:25:15 +00:00
|
|
|
ifneq ($(CAPSTONE_USE_SYS_DYN_MEM),yes)
|
2014-03-07 14:06:51 +00:00
|
|
|
# remove string check because OSX kernel complains about missing symbols
|
|
|
|
CFLAGS += -D_FORTIFY_SOURCE=0
|
|
|
|
endif
|
2014-03-29 14:36:05 +00:00
|
|
|
endif
|
2013-11-27 14:38:44 +00:00
|
|
|
else
|
2017-09-05 14:45:48 +00:00
|
|
|
CFLAGS += $(foreach arch,$(LIBARCHS),-arch $(arch))
|
|
|
|
LDFLAGS += $(foreach arch,$(LIBARCHS),-arch $(arch))
|
2014-05-14 07:13:36 +00:00
|
|
|
$(LIBNAME)_LDFLAGS += -shared
|
2013-11-28 18:22:50 +00:00
|
|
|
# Cygwin?
|
2017-02-06 12:24:33 +00:00
|
|
|
IS_CYGWIN := $(shell $(CC) -dumpmachine 2>/dev/null | grep -i cygwin | wc -l)
|
2013-11-28 18:22:50 +00:00
|
|
|
ifeq ($(IS_CYGWIN),1)
|
|
|
|
EXT = dll
|
2014-05-14 06:53:51 +00:00
|
|
|
AR_EXT = lib
|
2013-11-28 18:22:50 +00:00
|
|
|
# Cygwin doesn't like -fPIC
|
|
|
|
CFLAGS := $(CFLAGS:-fPIC=)
|
|
|
|
# On Windows we need the shared library to be executable
|
|
|
|
else
|
|
|
|
# mingw?
|
2018-11-20 16:46:12 +00:00
|
|
|
IS_MINGW := $(shell $(CC) --version 2>/dev/null | grep -i "\(mingw\|MSYS\)" | wc -l)
|
2013-11-28 18:22:50 +00:00
|
|
|
ifeq ($(IS_MINGW),1)
|
|
|
|
EXT = dll
|
2014-05-14 06:53:51 +00:00
|
|
|
AR_EXT = lib
|
2013-11-28 18:22:50 +00:00
|
|
|
# mingw doesn't like -fPIC either
|
|
|
|
CFLAGS := $(CFLAGS:-fPIC=)
|
|
|
|
# On Windows we need the shared library to be executable
|
2013-12-25 15:54:45 +00:00
|
|
|
else
|
|
|
|
# Linux, *BSD
|
2014-03-17 09:31:33 +00:00
|
|
|
EXT = so
|
|
|
|
VERSION_EXT = $(EXT).$(API_MAJOR)
|
2014-03-17 02:37:08 +00:00
|
|
|
AR_EXT = a
|
2014-05-14 07:13:36 +00:00
|
|
|
$(LIBNAME)_LDFLAGS += -Wl,-soname,lib$(LIBNAME).$(VERSION_EXT)
|
2013-11-28 18:22:50 +00:00
|
|
|
endif
|
|
|
|
endif
|
2013-11-27 04:11:31 +00:00
|
|
|
endif
|
|
|
|
|
2014-05-01 14:00:52 +00:00
|
|
|
ifeq ($(CAPSTONE_SHARED),yes)
|
2014-06-03 16:26:33 +00:00
|
|
|
ifeq ($(IS_MINGW),1)
|
2016-04-30 16:32:59 +00:00
|
|
|
LIBRARY = $(BLDIR)/$(LIBNAME).$(VERSION_EXT)
|
2014-06-03 16:26:33 +00:00
|
|
|
else ifeq ($(IS_CYGWIN),1)
|
2016-04-30 16:32:59 +00:00
|
|
|
LIBRARY = $(BLDIR)/$(LIBNAME).$(VERSION_EXT)
|
2014-06-03 16:26:33 +00:00
|
|
|
else # *nix
|
2016-04-30 16:32:59 +00:00
|
|
|
LIBRARY = $(BLDIR)/lib$(LIBNAME).$(VERSION_EXT)
|
2015-02-26 17:37:32 +00:00
|
|
|
CFLAGS += -fvisibility=hidden
|
2014-05-01 14:00:52 +00:00
|
|
|
endif
|
2014-06-03 16:26:33 +00:00
|
|
|
endif
|
|
|
|
|
2014-05-01 14:00:52 +00:00
|
|
|
ifeq ($(CAPSTONE_STATIC),yes)
|
2014-06-03 16:26:33 +00:00
|
|
|
ifeq ($(IS_MINGW),1)
|
|
|
|
ARCHIVE = $(BLDIR)/$(LIBNAME).$(AR_EXT)
|
|
|
|
else ifeq ($(IS_CYGWIN),1)
|
|
|
|
ARCHIVE = $(BLDIR)/$(LIBNAME).$(AR_EXT)
|
|
|
|
else
|
2014-04-29 08:29:55 +00:00
|
|
|
ARCHIVE = $(BLDIR)/lib$(LIBNAME).$(AR_EXT)
|
2014-05-01 14:00:52 +00:00
|
|
|
endif
|
2014-06-03 16:26:33 +00:00
|
|
|
endif
|
|
|
|
|
2014-04-29 08:29:55 +00:00
|
|
|
PKGCFGF = $(BLDIR)/$(LIBNAME).pc
|
2013-12-06 16:03:41 +00:00
|
|
|
|
2014-02-28 02:49:46 +00:00
|
|
|
.PHONY: all clean install uninstall dist
|
2013-11-27 04:11:31 +00:00
|
|
|
|
2013-12-08 16:38:44 +00:00
|
|
|
all: $(LIBRARY) $(ARCHIVE) $(PKGCFGF)
|
2015-01-30 01:07:51 +00:00
|
|
|
ifeq (,$(findstring yes,$(CAPSTONE_BUILD_CORE_ONLY)))
|
2017-06-02 13:49:10 +00:00
|
|
|
@V=$(V) CC=$(CC) $(MAKE) -C cstool
|
2015-01-27 20:42:34 +00:00
|
|
|
ifndef BUILDDIR
|
2018-05-12 03:36:10 +00:00
|
|
|
$(MAKE) -C tests
|
2018-12-04 08:02:16 +00:00
|
|
|
$(MAKE) -C suite/fuzz
|
2015-01-27 20:42:34 +00:00
|
|
|
else
|
2018-05-12 03:36:10 +00:00
|
|
|
$(MAKE) -C tests BUILDDIR=$(BLDIR)
|
2018-12-04 08:02:16 +00:00
|
|
|
$(MAKE) -C suite/fuzz BUILDDIR=$(BLDIR)
|
2015-01-27 20:42:34 +00:00
|
|
|
endif
|
2016-09-03 01:54:56 +00:00
|
|
|
$(call install-library,$(BLDIR)/tests/)
|
2014-05-01 14:00:52 +00:00
|
|
|
endif
|
2013-11-27 04:11:31 +00:00
|
|
|
|
2014-05-01 14:00:52 +00:00
|
|
|
ifeq ($(CAPSTONE_SHARED),yes)
|
2014-02-28 01:44:07 +00:00
|
|
|
$(LIBRARY): $(LIBOBJ)
|
2014-05-01 13:22:25 +00:00
|
|
|
ifeq ($(V),0)
|
2014-06-03 16:43:53 +00:00
|
|
|
$(call log,LINK,$(@:$(BLDIR)/%=%))
|
2014-05-01 13:22:25 +00:00
|
|
|
@$(create-library)
|
|
|
|
else
|
|
|
|
$(create-library)
|
|
|
|
endif
|
2014-05-01 14:00:52 +00:00
|
|
|
endif
|
2013-11-27 14:31:26 +00:00
|
|
|
|
2019-07-29 06:15:05 +00:00
|
|
|
$(LIBOBJ): config.mk
|
2014-03-27 09:54:27 +00:00
|
|
|
|
2014-02-28 15:09:04 +00:00
|
|
|
$(LIBOBJ_ARM): $(DEP_ARM)
|
|
|
|
$(LIBOBJ_ARM64): $(DEP_ARM64)
|
2015-08-03 16:45:08 +00:00
|
|
|
$(LIBOBJ_M68K): $(DEP_M68K)
|
2014-02-28 15:09:04 +00:00
|
|
|
$(LIBOBJ_MIPS): $(DEP_MIPS)
|
|
|
|
$(LIBOBJ_PPC): $(DEP_PPC)
|
2014-03-10 03:58:57 +00:00
|
|
|
$(LIBOBJ_SPARC): $(DEP_SPARC)
|
2014-03-23 00:35:45 +00:00
|
|
|
$(LIBOBJ_SYSZ): $(DEP_SYSZ)
|
2014-02-28 15:09:04 +00:00
|
|
|
$(LIBOBJ_X86): $(DEP_X86)
|
2014-05-26 15:02:48 +00:00
|
|
|
$(LIBOBJ_XCORE): $(DEP_XCORE)
|
2016-05-03 12:52:11 +00:00
|
|
|
$(LIBOBJ_TMS320C64X): $(DEP_TMS320C64X)
|
M680X: Target ready for pull request (#1034)
* Added new M680X target. Supports M6800/1/2/3/9, HD6301
* M680X: Reformat for coding guide lines. Set alphabetical order in HACK.TXT
* M680X: Prepare for python binding. Move cs_m680x, m680x_insn to m680x_info. Chec
> k cpu type, no default.
* M680X: Add python bindings. Added python tests.
* M680X: Added cpu types to usage message.
* cstool: Avoid segfault for invalid <arch+mode>.
* Make test_m680x.c/test_m680x.py output comparable (diff params: -bu). Keep xprint.py untouched.
* M680X: Update CMake/make for m680x support. Update .gitignore.
* M680X: Reduce compiler warnings.
* M680X: Reduce compiler warnings.
* M680X: Reduce compiler warnings.
* M680X: Make test_m680x.c/test_m680x.py output comparable (diff params: -bu).
* M680X: Add ocaml bindings and tests.
* M680X: Add java bindings and tests.
* M680X: Added tests for all indexed addressing modes. C/Python/Ocaml
* M680X: Naming, use page1 for PAGE1 instructions (without prefix).
* M680X: Naming, use page1 for PAGE1 instructions (without prefix).
* M680X: Used M680X_FIRST_OP_IN_MNEM in tests C/python/java/ocaml.
* M680X: Added access property to cs_m680x_op.
* M680X: Added operand size.
* M680X: Remove compiler warnings.
* M680X: Added READ/WRITE access property per operator.
* M680X: Make reg_inherent_hdlr independent of CPU type.
* M680X: Add HD6309 support + bug fixes
* M680X: Remove errors and warning.
* M680X: Add Bcc/LBcc to group BRAREL (relative branch).
* M680X: Add group JUMP to BVS/BVC/LBVS/LBVC. Remove BRAREL from BRN/LBRN.
* M680X: Remove LBRN from group BRAREL.
* M680X: Refactored cpu_type initialization for better readability.
* M680X: Add two operands for insn having two reg. in mnemonic. e.g. ABX.
* M680X: Remove typo in cstool.c
* M680X: Some format improvements in changed_regs.
* M680X: Remove insn id string list from tests (C/python/java/ocaml).
* M680X: SEXW, set access of reg. D to WRITE.
* M680X: Sort changed_regs in increasing m680x_insn order.
* M680X: Add M68HC11 support + Reduced from two to one INDEXED operand.
* M680X: cstool, also write '(in mnemonic)' for second reg. operand.
* M680X: Add BRN/LBRN to group JUMP and BRAREL.
* M680X: For Bcc/LBcc/BRSET/BRCLR set reg. CC to read access.
* M680X: Correctly print negative immediate values with option CS_OPT_UNSIGNED.
* M680X: Rename some instruction handlers.
* M680X: Add M68HC05 support.
* M680X: Dont print prefix '<' for direct addr. mode.
* M680X: Add M68HC08 support + resorted tables + bug fixes.
* M680X: Add Freescale HCS08 support.
* M680X: Changed group names, avoid spaces.
* M680X: Refactoring, rename addessing mode handlers.
* M680X: indexed addr. mode, changed pre/post inc-/decrement representation.
* M680X: Rename some M6809/HD6309 specific functions.
* M680X: Add CPU12 (68HC12/HCS12) support.
* M680X: Correctly display illegal instruction as FCB .
* M680X: bugfix: BRA/BRN/BSR/LBRA/LBRN/LBSR does not read CC reg.
* M680X: bugfix: Correctly check for sufficient code size for M6809 indexed addressing.
* M680X: Better support for changing insn id within handler for addessing mode.
* M680X: Remove warnings.
* M680X: In set_changed_regs_read_write_counts use own access_mode.
* M680X: Split cpu specific tables into separate *.inc files.
* M680X: Remove warnings.
* M680X: Removed address_mode. Addressing mode is available in operand.type
* M680X: Bugfix: BSET/BCLR/BRSET/BRCLR correct read/modify CC reg.
* M680X: Remove register TMP1. It is first visible in CPU12X.
* M680X: Performance improvement + bug fixes.
* M680X: Performance improvement, make cpu_tables const static.
* M680X: Simplify operand decoding by using two handlers.
* M680X: Replace M680X_OP_INDEX by M680X_OP_CONSTANT + bugfix in java/python/ocaml bindings.
* M680X: Format with astyle.
* M680X: Update documentation.
* M680X: Corrected author for m680x specific files.
* M680X: Make max. number of architectures single source.
2017-10-21 13:44:36 +00:00
|
|
|
$(LIBOBJ_M680X): $(DEP_M680X)
|
2018-03-31 09:29:22 +00:00
|
|
|
$(LIBOBJ_EVM): $(DEP_EVM)
|
RISCV support ISRV32/ISRV64 (#1401)
* Added RISCV dir to contain the RISCV architecture engine code. Adding the TableGen files generated from llvm-tblgen. Add Disassembler.h
* Started working on RISCVDisassembler.c - RISCV_init(), RISCVDisassembler_getInstruction, and RISCV_getInstruction
* Added all functions to RISCVDisassembler.c and needed modifications to RISCVGenDisassemblerTables.inc. Add and modified RISCVGenSubtargetInfo.inc. Start creation of RISCVInstPrinter.h
* Finished RISCVGenAsmWriter.inc. Finished RISCVGenRegisterInfo.inc. Minor fixes to RISCVDisassembler.c. Working on RISCVInstPrinter
* Finished RISCVInstPrinter, RISCVMapping, RISCVBaseInfo, RISCVGenInstrInfo.inc, RISCVModule.c. Working on riscv.h
* Backport it from: https://github.com/porto703/capstone/commit/0db412ce3bed9d963caf598a2cb7dc76b41a5a2b
* All RISCV files added. Compiled correctly and initial test for ADD, ADDI, AND works properly.
* Add refactored cs.c for RISCV
* Testing all I instructions in test_riscv.c
* Modify the orignal backport for RISCVGenRegisterInfo.inc, capstone.h and test_iter to work w/ the current code strcuture
* Fix issue with RISCVGenRegisterInfo.inc - RISCVRegDesc[] (Excess elements in struct initializer). Added RISCV tests to test_iter.c
* fixed bug related to incorrect initialization of memory after malloc
* fix compile bug
* Fix compile errors.
* move riscv.h to include/capstone
* fix indentation issues
* fix coding style issues
* Fix indentation issues
* fix coding style
* Move variable declaration to the top of the block
* Fix coding indentation
* Move some stuff into RISCVMappingInsn.inc
* Fix code sytle
* remove cs_mode support for RISCV
* update asmwriter-inc to LLVM upstream
* update the .inc files to riscv upstream
* update riscv disassembler function for suport 16bit instructions
* update printer & tablegen inc files which have fixed arguments mismatch
* update headers and mapping source
* add riscv architecture specific test code
* fix all RISCV tons of compiler errors
* pass final tests
* add riscv tablegen patchs
* merge with upstream/next
* fix cstool missing riscv file
* fix root Makefile
* add new TableGen patchs for riscv
* fix cmakefile.txt of missing one riscv file
* fix declaration conflict
* fix incompatible declaration type
* change riscvc from arch to mode
* fix test_riscv warnning
* fix code style and add riscv part of test_basic
* add RISCV64 mode
* add suite for riscv
* crack fuzz test
* fix getfeaturebits test add riscvc
* fix test missing const qualifier warnning
* fix testcase type mismatch
* fix return value missing
* change getfeaturebits test
* add test cs files
* using a winder type contain the decode string
* fix a copy typo
* remove useless mode for riscv
* change cs file blank type
* add repo for update_riscv & fix cstool missing riscv mode
* fix typo
* add riscv for cstool useage
* add TableGen patch for riscv asmwriter
* clean ctags file
* remove black comment line
* fix fuzz related something
* fix missing RISCV string of fuzz
* update readme, etc..
* add riscv *.s.cs file
* add riscv *.s.cs file & clear ctags
* clear useless array declarations at capstone_test
* update to 5e4069f
* update readme change name more formal
* change position of riscv after bpf and modify copyright more uniform
* clear useless ctags file
* change blank with tab in riscv.h
* add riscv python bindings
* add riscv in __init__.py
* fix riscv define value for python binding
* fix test_riscv.py typo
* add missing riscvc in __init__.py of python bindings
* fix alias-insn printer bug, remove useless newline
* change inst print delimter from tab to bankspace for travis
* add riscv tablegen patch
* fix inst output more consistency
* add TableGen patch which fix inst output formal
* crack the effective address output for detail and change register print function
* fix not detail crash bug
* change item declaration position at cs_riscv
* update riscv.py
* change function name more meaningfull
* update python binding makefile
* fix register enum sequence according to riscvgenreginfo.inc
* test function name
* add enum s0/fp in riscv.h & update riscv_const.py
* add register name enum
2019-03-09 00:41:12 +00:00
|
|
|
$(LIBOBJ_RISCV): $(DEP_RISCV)
|
2019-02-01 15:03:47 +00:00
|
|
|
$(LIBOBJ_WASM): $(DEP_WASM)
|
2018-12-02 20:39:41 +00:00
|
|
|
$(LIBOBJ_MOS65XX): $(DEP_MOS65XX)
|
2019-02-18 09:39:51 +00:00
|
|
|
$(LIBOBJ_BPF): $(DEP_BPF)
|
2014-02-28 15:09:04 +00:00
|
|
|
|
2014-05-01 14:00:52 +00:00
|
|
|
ifeq ($(CAPSTONE_STATIC),yes)
|
2013-12-06 16:03:41 +00:00
|
|
|
$(ARCHIVE): $(LIBOBJ)
|
2014-05-01 13:22:25 +00:00
|
|
|
@rm -f $(ARCHIVE)
|
|
|
|
ifeq ($(V),0)
|
|
|
|
$(call log,AR,$(@:$(BLDIR)/%=%))
|
|
|
|
@$(create-archive)
|
|
|
|
else
|
|
|
|
$(create-archive)
|
|
|
|
endif
|
2014-05-01 14:00:52 +00:00
|
|
|
endif
|
2013-12-03 03:11:37 +00:00
|
|
|
|
2013-12-06 16:03:41 +00:00
|
|
|
$(PKGCFGF):
|
2014-05-01 13:22:25 +00:00
|
|
|
ifeq ($(V),0)
|
|
|
|
$(call log,GEN,$(@:$(BLDIR)/%=%))
|
|
|
|
@$(generate-pkgcfg)
|
2014-03-07 09:11:18 +00:00
|
|
|
else
|
2014-05-01 13:22:25 +00:00
|
|
|
$(generate-pkgcfg)
|
2014-03-07 09:11:18 +00:00
|
|
|
endif
|
2013-12-03 03:11:37 +00:00
|
|
|
|
2019-07-29 06:15:05 +00:00
|
|
|
# create a list of auto dependencies
|
|
|
|
AUTODEPS:= $(patsubst %.o,%.d, $(LIBOBJ))
|
|
|
|
|
|
|
|
# include by auto dependencies
|
|
|
|
-include $(AUTODEPS)
|
|
|
|
|
2013-12-06 16:03:41 +00:00
|
|
|
install: $(PKGCFGF) $(ARCHIVE) $(LIBRARY)
|
2018-12-19 01:41:34 +00:00
|
|
|
mkdir -p $(LIBDIR)
|
|
|
|
$(call install-library,$(LIBDIR))
|
2014-05-01 14:00:52 +00:00
|
|
|
ifeq ($(CAPSTONE_STATIC),yes)
|
2018-12-19 01:41:34 +00:00
|
|
|
$(INSTALL_DATA) $(ARCHIVE) $(LIBDIR)
|
2014-05-01 14:00:52 +00:00
|
|
|
endif
|
2016-10-13 12:45:24 +00:00
|
|
|
mkdir -p $(DESTDIR)$(INCDIR)/$(LIBNAME)
|
|
|
|
$(INSTALL_DATA) include/capstone/*.h $(DESTDIR)$(INCDIR)/$(LIBNAME)
|
2018-12-19 02:21:07 +00:00
|
|
|
mkdir -p $(PKGCFGDIR)
|
|
|
|
$(INSTALL_DATA) $(PKGCFGF) $(PKGCFGDIR)
|
|
|
|
mkdir -p $(BINDIR)
|
|
|
|
$(INSTALL_LIB) cstool/cstool $(BINDIR)
|
2013-11-27 04:11:31 +00:00
|
|
|
|
|
|
|
uninstall:
|
2016-10-13 12:45:24 +00:00
|
|
|
rm -rf $(DESTDIR)$(INCDIR)/$(LIBNAME)
|
2018-12-19 07:52:20 +00:00
|
|
|
rm -f $(LIBDIR)/lib$(LIBNAME).*
|
2018-12-19 02:21:07 +00:00
|
|
|
rm -f $(PKGCFGDIR)/$(LIBNAME).pc
|
2018-12-19 02:25:04 +00:00
|
|
|
rm -f $(BINDIR)/cstool
|
2013-11-27 04:11:31 +00:00
|
|
|
|
|
|
|
clean:
|
2014-04-29 08:24:30 +00:00
|
|
|
rm -f $(LIBOBJ)
|
2017-05-05 01:46:46 +00:00
|
|
|
rm -f $(BLDIR)/lib$(LIBNAME).* $(BLDIR)/$(LIBNAME).pc
|
2014-01-09 02:35:58 +00:00
|
|
|
rm -f $(PKGCFGF)
|
2019-07-29 06:15:05 +00:00
|
|
|
rm -f $(AUTODEPS)
|
2019-07-26 16:16:01 +00:00
|
|
|
[ ${ANDROID} -eq 1 ] && rm -rf android-ndk-*
|
2016-10-10 14:54:16 +00:00
|
|
|
$(MAKE) -C cstool clean
|
2015-01-27 17:35:44 +00:00
|
|
|
|
2015-01-30 01:07:51 +00:00
|
|
|
ifeq (,$(findstring yes,$(CAPSTONE_BUILD_CORE_ONLY)))
|
2018-05-12 03:36:10 +00:00
|
|
|
$(MAKE) -C tests clean
|
2018-12-04 08:02:16 +00:00
|
|
|
$(MAKE) -C suite/fuzz clean
|
2014-04-29 08:29:55 +00:00
|
|
|
rm -f $(BLDIR)/tests/lib$(LIBNAME).$(EXT)
|
2015-01-27 17:35:44 +00:00
|
|
|
endif
|
2014-04-29 08:29:55 +00:00
|
|
|
|
|
|
|
ifdef BUILDDIR
|
|
|
|
rm -rf $(BUILDDIR)
|
|
|
|
endif
|
2014-04-29 08:24:30 +00:00
|
|
|
|
2015-01-30 01:07:51 +00:00
|
|
|
ifeq (,$(findstring yes,$(CAPSTONE_BUILD_CORE_ONLY)))
|
2018-05-12 03:36:10 +00:00
|
|
|
$(MAKE) -C bindings/python clean
|
|
|
|
$(MAKE) -C bindings/java clean
|
|
|
|
$(MAKE) -C bindings/ocaml clean
|
2015-01-27 17:35:44 +00:00
|
|
|
endif
|
2013-11-27 04:11:31 +00:00
|
|
|
|
2014-01-18 04:47:15 +00:00
|
|
|
|
|
|
|
TAG ?= HEAD
|
|
|
|
ifeq ($(TAG), HEAD)
|
|
|
|
DIST_VERSION = latest
|
|
|
|
else
|
|
|
|
DIST_VERSION = $(TAG)
|
2014-01-18 02:42:15 +00:00
|
|
|
endif
|
2014-01-18 04:47:15 +00:00
|
|
|
|
|
|
|
dist:
|
2014-01-22 10:46:20 +00:00
|
|
|
git archive --format=tar.gz --prefix=capstone-$(DIST_VERSION)/ $(TAG) > capstone-$(DIST_VERSION).tgz
|
2014-03-11 04:29:16 +00:00
|
|
|
git archive --format=zip --prefix=capstone-$(DIST_VERSION)/ $(TAG) > capstone-$(DIST_VERSION).zip
|
2014-01-18 02:42:15 +00:00
|
|
|
|
RISCV support ISRV32/ISRV64 (#1401)
* Added RISCV dir to contain the RISCV architecture engine code. Adding the TableGen files generated from llvm-tblgen. Add Disassembler.h
* Started working on RISCVDisassembler.c - RISCV_init(), RISCVDisassembler_getInstruction, and RISCV_getInstruction
* Added all functions to RISCVDisassembler.c and needed modifications to RISCVGenDisassemblerTables.inc. Add and modified RISCVGenSubtargetInfo.inc. Start creation of RISCVInstPrinter.h
* Finished RISCVGenAsmWriter.inc. Finished RISCVGenRegisterInfo.inc. Minor fixes to RISCVDisassembler.c. Working on RISCVInstPrinter
* Finished RISCVInstPrinter, RISCVMapping, RISCVBaseInfo, RISCVGenInstrInfo.inc, RISCVModule.c. Working on riscv.h
* Backport it from: https://github.com/porto703/capstone/commit/0db412ce3bed9d963caf598a2cb7dc76b41a5a2b
* All RISCV files added. Compiled correctly and initial test for ADD, ADDI, AND works properly.
* Add refactored cs.c for RISCV
* Testing all I instructions in test_riscv.c
* Modify the orignal backport for RISCVGenRegisterInfo.inc, capstone.h and test_iter to work w/ the current code strcuture
* Fix issue with RISCVGenRegisterInfo.inc - RISCVRegDesc[] (Excess elements in struct initializer). Added RISCV tests to test_iter.c
* fixed bug related to incorrect initialization of memory after malloc
* fix compile bug
* Fix compile errors.
* move riscv.h to include/capstone
* fix indentation issues
* fix coding style issues
* Fix indentation issues
* fix coding style
* Move variable declaration to the top of the block
* Fix coding indentation
* Move some stuff into RISCVMappingInsn.inc
* Fix code sytle
* remove cs_mode support for RISCV
* update asmwriter-inc to LLVM upstream
* update the .inc files to riscv upstream
* update riscv disassembler function for suport 16bit instructions
* update printer & tablegen inc files which have fixed arguments mismatch
* update headers and mapping source
* add riscv architecture specific test code
* fix all RISCV tons of compiler errors
* pass final tests
* add riscv tablegen patchs
* merge with upstream/next
* fix cstool missing riscv file
* fix root Makefile
* add new TableGen patchs for riscv
* fix cmakefile.txt of missing one riscv file
* fix declaration conflict
* fix incompatible declaration type
* change riscvc from arch to mode
* fix test_riscv warnning
* fix code style and add riscv part of test_basic
* add RISCV64 mode
* add suite for riscv
* crack fuzz test
* fix getfeaturebits test add riscvc
* fix test missing const qualifier warnning
* fix testcase type mismatch
* fix return value missing
* change getfeaturebits test
* add test cs files
* using a winder type contain the decode string
* fix a copy typo
* remove useless mode for riscv
* change cs file blank type
* add repo for update_riscv & fix cstool missing riscv mode
* fix typo
* add riscv for cstool useage
* add TableGen patch for riscv asmwriter
* clean ctags file
* remove black comment line
* fix fuzz related something
* fix missing RISCV string of fuzz
* update readme, etc..
* add riscv *.s.cs file
* add riscv *.s.cs file & clear ctags
* clear useless array declarations at capstone_test
* update to 5e4069f
* update readme change name more formal
* change position of riscv after bpf and modify copyright more uniform
* clear useless ctags file
* change blank with tab in riscv.h
* add riscv python bindings
* add riscv in __init__.py
* fix riscv define value for python binding
* fix test_riscv.py typo
* add missing riscvc in __init__.py of python bindings
* fix alias-insn printer bug, remove useless newline
* change inst print delimter from tab to bankspace for travis
* add riscv tablegen patch
* fix inst output more consistency
* add TableGen patch which fix inst output formal
* crack the effective address output for detail and change register print function
* fix not detail crash bug
* change item declaration position at cs_riscv
* update riscv.py
* change function name more meaningfull
* update python binding makefile
* fix register enum sequence according to riscvgenreginfo.inc
* test function name
* add enum s0/fp in riscv.h & update riscv_const.py
* add register name enum
2019-03-09 00:41:12 +00:00
|
|
|
TESTS = test_basic test_detail test_arm test_arm64 test_m68k test_mips test_ppc test_sparc
|
|
|
|
TESTS += test_systemz test_x86 test_xcore test_iter test_evm test_riscv test_mos65xx test_wasm test_bpf
|
2017-05-11 15:58:12 +00:00
|
|
|
TESTS += test_basic.static test_detail.static test_arm.static test_arm64.static
|
2015-08-03 16:45:08 +00:00
|
|
|
TESTS += test_m68k.static test_mips.static test_ppc.static test_sparc.static
|
M680X: Target ready for pull request (#1034)
* Added new M680X target. Supports M6800/1/2/3/9, HD6301
* M680X: Reformat for coding guide lines. Set alphabetical order in HACK.TXT
* M680X: Prepare for python binding. Move cs_m680x, m680x_insn to m680x_info. Chec
> k cpu type, no default.
* M680X: Add python bindings. Added python tests.
* M680X: Added cpu types to usage message.
* cstool: Avoid segfault for invalid <arch+mode>.
* Make test_m680x.c/test_m680x.py output comparable (diff params: -bu). Keep xprint.py untouched.
* M680X: Update CMake/make for m680x support. Update .gitignore.
* M680X: Reduce compiler warnings.
* M680X: Reduce compiler warnings.
* M680X: Reduce compiler warnings.
* M680X: Make test_m680x.c/test_m680x.py output comparable (diff params: -bu).
* M680X: Add ocaml bindings and tests.
* M680X: Add java bindings and tests.
* M680X: Added tests for all indexed addressing modes. C/Python/Ocaml
* M680X: Naming, use page1 for PAGE1 instructions (without prefix).
* M680X: Naming, use page1 for PAGE1 instructions (without prefix).
* M680X: Used M680X_FIRST_OP_IN_MNEM in tests C/python/java/ocaml.
* M680X: Added access property to cs_m680x_op.
* M680X: Added operand size.
* M680X: Remove compiler warnings.
* M680X: Added READ/WRITE access property per operator.
* M680X: Make reg_inherent_hdlr independent of CPU type.
* M680X: Add HD6309 support + bug fixes
* M680X: Remove errors and warning.
* M680X: Add Bcc/LBcc to group BRAREL (relative branch).
* M680X: Add group JUMP to BVS/BVC/LBVS/LBVC. Remove BRAREL from BRN/LBRN.
* M680X: Remove LBRN from group BRAREL.
* M680X: Refactored cpu_type initialization for better readability.
* M680X: Add two operands for insn having two reg. in mnemonic. e.g. ABX.
* M680X: Remove typo in cstool.c
* M680X: Some format improvements in changed_regs.
* M680X: Remove insn id string list from tests (C/python/java/ocaml).
* M680X: SEXW, set access of reg. D to WRITE.
* M680X: Sort changed_regs in increasing m680x_insn order.
* M680X: Add M68HC11 support + Reduced from two to one INDEXED operand.
* M680X: cstool, also write '(in mnemonic)' for second reg. operand.
* M680X: Add BRN/LBRN to group JUMP and BRAREL.
* M680X: For Bcc/LBcc/BRSET/BRCLR set reg. CC to read access.
* M680X: Correctly print negative immediate values with option CS_OPT_UNSIGNED.
* M680X: Rename some instruction handlers.
* M680X: Add M68HC05 support.
* M680X: Dont print prefix '<' for direct addr. mode.
* M680X: Add M68HC08 support + resorted tables + bug fixes.
* M680X: Add Freescale HCS08 support.
* M680X: Changed group names, avoid spaces.
* M680X: Refactoring, rename addessing mode handlers.
* M680X: indexed addr. mode, changed pre/post inc-/decrement representation.
* M680X: Rename some M6809/HD6309 specific functions.
* M680X: Add CPU12 (68HC12/HCS12) support.
* M680X: Correctly display illegal instruction as FCB .
* M680X: bugfix: BRA/BRN/BSR/LBRA/LBRN/LBSR does not read CC reg.
* M680X: bugfix: Correctly check for sufficient code size for M6809 indexed addressing.
* M680X: Better support for changing insn id within handler for addessing mode.
* M680X: Remove warnings.
* M680X: In set_changed_regs_read_write_counts use own access_mode.
* M680X: Split cpu specific tables into separate *.inc files.
* M680X: Remove warnings.
* M680X: Removed address_mode. Addressing mode is available in operand.type
* M680X: Bugfix: BSET/BCLR/BRSET/BRCLR correct read/modify CC reg.
* M680X: Remove register TMP1. It is first visible in CPU12X.
* M680X: Performance improvement + bug fixes.
* M680X: Performance improvement, make cpu_tables const static.
* M680X: Simplify operand decoding by using two handlers.
* M680X: Replace M680X_OP_INDEX by M680X_OP_CONSTANT + bugfix in java/python/ocaml bindings.
* M680X: Format with astyle.
* M680X: Update documentation.
* M680X: Corrected author for m680x specific files.
* M680X: Make max. number of architectures single source.
2017-10-21 13:44:36 +00:00
|
|
|
TESTS += test_systemz.static test_x86.static test_xcore.static test_m680x.static
|
RISCV support ISRV32/ISRV64 (#1401)
* Added RISCV dir to contain the RISCV architecture engine code. Adding the TableGen files generated from llvm-tblgen. Add Disassembler.h
* Started working on RISCVDisassembler.c - RISCV_init(), RISCVDisassembler_getInstruction, and RISCV_getInstruction
* Added all functions to RISCVDisassembler.c and needed modifications to RISCVGenDisassemblerTables.inc. Add and modified RISCVGenSubtargetInfo.inc. Start creation of RISCVInstPrinter.h
* Finished RISCVGenAsmWriter.inc. Finished RISCVGenRegisterInfo.inc. Minor fixes to RISCVDisassembler.c. Working on RISCVInstPrinter
* Finished RISCVInstPrinter, RISCVMapping, RISCVBaseInfo, RISCVGenInstrInfo.inc, RISCVModule.c. Working on riscv.h
* Backport it from: https://github.com/porto703/capstone/commit/0db412ce3bed9d963caf598a2cb7dc76b41a5a2b
* All RISCV files added. Compiled correctly and initial test for ADD, ADDI, AND works properly.
* Add refactored cs.c for RISCV
* Testing all I instructions in test_riscv.c
* Modify the orignal backport for RISCVGenRegisterInfo.inc, capstone.h and test_iter to work w/ the current code strcuture
* Fix issue with RISCVGenRegisterInfo.inc - RISCVRegDesc[] (Excess elements in struct initializer). Added RISCV tests to test_iter.c
* fixed bug related to incorrect initialization of memory after malloc
* fix compile bug
* Fix compile errors.
* move riscv.h to include/capstone
* fix indentation issues
* fix coding style issues
* Fix indentation issues
* fix coding style
* Move variable declaration to the top of the block
* Fix coding indentation
* Move some stuff into RISCVMappingInsn.inc
* Fix code sytle
* remove cs_mode support for RISCV
* update asmwriter-inc to LLVM upstream
* update the .inc files to riscv upstream
* update riscv disassembler function for suport 16bit instructions
* update printer & tablegen inc files which have fixed arguments mismatch
* update headers and mapping source
* add riscv architecture specific test code
* fix all RISCV tons of compiler errors
* pass final tests
* add riscv tablegen patchs
* merge with upstream/next
* fix cstool missing riscv file
* fix root Makefile
* add new TableGen patchs for riscv
* fix cmakefile.txt of missing one riscv file
* fix declaration conflict
* fix incompatible declaration type
* change riscvc from arch to mode
* fix test_riscv warnning
* fix code style and add riscv part of test_basic
* add RISCV64 mode
* add suite for riscv
* crack fuzz test
* fix getfeaturebits test add riscvc
* fix test missing const qualifier warnning
* fix testcase type mismatch
* fix return value missing
* change getfeaturebits test
* add test cs files
* using a winder type contain the decode string
* fix a copy typo
* remove useless mode for riscv
* change cs file blank type
* add repo for update_riscv & fix cstool missing riscv mode
* fix typo
* add riscv for cstool useage
* add TableGen patch for riscv asmwriter
* clean ctags file
* remove black comment line
* fix fuzz related something
* fix missing RISCV string of fuzz
* update readme, etc..
* add riscv *.s.cs file
* add riscv *.s.cs file & clear ctags
* clear useless array declarations at capstone_test
* update to 5e4069f
* update readme change name more formal
* change position of riscv after bpf and modify copyright more uniform
* clear useless ctags file
* change blank with tab in riscv.h
* add riscv python bindings
* add riscv in __init__.py
* fix riscv define value for python binding
* fix test_riscv.py typo
* add missing riscvc in __init__.py of python bindings
* fix alias-insn printer bug, remove useless newline
* change inst print delimter from tab to bankspace for travis
* add riscv tablegen patch
* fix inst output more consistency
* add TableGen patch which fix inst output formal
* crack the effective address output for detail and change register print function
* fix not detail crash bug
* change item declaration position at cs_riscv
* update riscv.py
* change function name more meaningfull
* update python binding makefile
* fix register enum sequence according to riscvgenreginfo.inc
* test function name
* add enum s0/fp in riscv.h & update riscv_const.py
* add register name enum
2019-03-09 00:41:12 +00:00
|
|
|
TESTS += test_skipdata test_skipdata.static test_iter.static test_evm.static test_riscv.static
|
2019-02-18 09:39:51 +00:00
|
|
|
TESTS += test_mos65xx.static test_wasm.static test_bpf.static
|
2018-12-11 02:33:31 +00:00
|
|
|
check: $(TESTS) fuzztest fuzzallcorp
|
2018-05-25 12:59:30 +00:00
|
|
|
test_%:
|
|
|
|
./tests/$@ > /dev/null && echo OK || echo FAILED
|
2014-10-01 08:42:29 +00:00
|
|
|
|
2018-12-04 08:02:16 +00:00
|
|
|
FUZZ_INPUTS = $(shell find suite/MC -type f -name '*.cs')
|
|
|
|
|
|
|
|
fuzztest:
|
|
|
|
./suite/fuzz/fuzz_disasm $(FUZZ_INPUTS)
|
|
|
|
|
2018-12-11 02:33:31 +00:00
|
|
|
fuzzallcorp:
|
2018-12-19 07:43:31 +00:00
|
|
|
ifneq ($(wildcard suite/fuzz/corpus-libFuzzer-capstone_fuzz_disasmnext-latest),)
|
2019-02-04 09:07:03 +00:00
|
|
|
./suite/fuzz/fuzz_bindisasm suite/fuzz/corpus-libFuzzer-capstone_fuzz_disasmnext-latest/ > fuzz_bindisasm.log || (tail -1 fuzz_bindisasm.log; false)
|
2018-12-19 07:43:31 +00:00
|
|
|
else
|
|
|
|
@echo "Skipping tests on whole corpus"
|
|
|
|
endif
|
2018-12-11 02:33:31 +00:00
|
|
|
|
2014-04-29 07:00:34 +00:00
|
|
|
$(OBJDIR)/%.o: %.c
|
|
|
|
@mkdir -p $(@D)
|
2014-05-01 13:22:25 +00:00
|
|
|
ifeq ($(V),0)
|
|
|
|
$(call log,CC,$(@:$(OBJDIR)/%=%))
|
|
|
|
@$(compile)
|
|
|
|
else
|
|
|
|
$(compile)
|
|
|
|
endif
|
|
|
|
|
|
|
|
|
2016-09-03 01:54:56 +00:00
|
|
|
ifeq ($(CAPSTONE_SHARED),yes)
|
|
|
|
define install-library
|
|
|
|
$(INSTALL_LIB) $(LIBRARY) $1
|
|
|
|
$(if $(VERSION_EXT),
|
|
|
|
cd $1 && \
|
2016-09-11 00:00:32 +00:00
|
|
|
rm -f lib$(LIBNAME).$(EXT) && \
|
2016-09-03 01:54:56 +00:00
|
|
|
ln -s lib$(LIBNAME).$(VERSION_EXT) lib$(LIBNAME).$(EXT))
|
|
|
|
endef
|
|
|
|
else
|
|
|
|
define install-library
|
|
|
|
endef
|
|
|
|
endif
|
|
|
|
|
|
|
|
|
2014-05-01 13:22:25 +00:00
|
|
|
define create-archive
|
|
|
|
$(AR) q $(ARCHIVE) $(LIBOBJ)
|
|
|
|
$(RANLIB) $(ARCHIVE)
|
|
|
|
endef
|
|
|
|
|
2014-05-01 14:53:52 +00:00
|
|
|
|
2014-05-01 13:22:25 +00:00
|
|
|
define create-library
|
2014-05-14 07:13:36 +00:00
|
|
|
$(CC) $(LDFLAGS) $($(LIBNAME)_LDFLAGS) $(LIBOBJ) -o $(LIBRARY)
|
2014-05-01 13:22:25 +00:00
|
|
|
endef
|
|
|
|
|
2014-05-01 14:53:52 +00:00
|
|
|
|
2014-05-01 13:22:25 +00:00
|
|
|
define generate-pkgcfg
|
2015-04-23 15:55:06 +00:00
|
|
|
mkdir -p $(BLDIR)
|
2014-05-01 13:22:25 +00:00
|
|
|
echo 'Name: capstone' > $(PKGCFGF)
|
|
|
|
echo 'Description: Capstone disassembly engine' >> $(PKGCFGF)
|
|
|
|
echo 'Version: $(PKG_VERSION)' >> $(PKGCFGF)
|
|
|
|
echo 'libdir=$(LIBDIR)' >> $(PKGCFGF)
|
2019-01-12 06:07:02 +00:00
|
|
|
echo 'includedir=$(INCDIR)/capstone' >> $(PKGCFGF)
|
2014-05-01 13:22:25 +00:00
|
|
|
echo 'archive=$${libdir}/libcapstone.a' >> $(PKGCFGF)
|
|
|
|
echo 'Libs: -L$${libdir} -lcapstone' >> $(PKGCFGF)
|
|
|
|
echo 'Cflags: -I$${includedir}' >> $(PKGCFGF)
|
|
|
|
endef
|