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updated 6502 support. (#1498)

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* updated 6502 support. some improvements to the base 6502 support but also adds support for 65c02, w65c02, and 65816.

* add CS_OPT_SYNTAX_MOTOROLA.

This will use "$" as a hex prefix instead of "0x"

* remove excess blank lines
This commit is contained in:
ksherlock 2019-06-03 11:20:51 -04:00 committed by Nguyen Anh Quynh
parent 19e088393f
commit 05b3fbf2d7
18 changed files with 1965 additions and 576 deletions
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734
arch/MOS65XX/MOS65XXDisassembler.c
View File

@ -3,273 +3,25 @@
#include "capstone/mos65xx.h"
#include "MOS65XXDisassembler.h"
#include "MOS65XXDisassemblerInternals.h"
typedef struct OpInfo {
mos65xx_insn ins;
mos65xx_address_mode am;
int operand_bytes;
} OpInfo;
static const struct OpInfo OpInfoTable[]= {
{ MOS65XX_INS_BRK , MOS65XX_AM_IMP }, // 0x00
{ MOS65XX_INS_ORA , MOS65XX_AM_INDX }, // 0x01
{ MOS65XX_INS_INVALID, MOS65XX_AM_NONE }, // 0x02
{ MOS65XX_INS_INVALID, MOS65XX_AM_NONE }, // 0x03
{ MOS65XX_INS_NOP , MOS65XX_AM_ZP }, // 0x04
{ MOS65XX_INS_ORA , MOS65XX_AM_ZP }, // 0x05
{ MOS65XX_INS_ASL , MOS65XX_AM_ZP }, // 0x06
{ MOS65XX_INS_INVALID, MOS65XX_AM_NONE }, // 0x07
{ MOS65XX_INS_PHP , MOS65XX_AM_IMP }, // 0x08
{ MOS65XX_INS_ORA , MOS65XX_AM_IMM }, // 0x09
{ MOS65XX_INS_ASL , MOS65XX_AM_ACC }, // 0x0a
{ MOS65XX_INS_INVALID, MOS65XX_AM_NONE }, // 0x0b
{ MOS65XX_INS_NOP , MOS65XX_AM_ABS }, // 0x0c
{ MOS65XX_INS_ORA , MOS65XX_AM_ABS }, // 0x0d
{ MOS65XX_INS_ASL , MOS65XX_AM_ABS }, // 0x0e
{ MOS65XX_INS_INVALID, MOS65XX_AM_NONE }, // 0x0f
{ MOS65XX_INS_BPL , MOS65XX_AM_REL }, // 0x10
{ MOS65XX_INS_ORA , MOS65XX_AM_INDY }, // 0x11
{ MOS65XX_INS_INVALID, MOS65XX_AM_NONE }, // 0x12
{ MOS65XX_INS_INVALID, MOS65XX_AM_NONE }, // 0x13
{ MOS65XX_INS_NOP , MOS65XX_AM_ZPX }, // 0x14
{ MOS65XX_INS_ORA , MOS65XX_AM_ZPX }, // 0x15
{ MOS65XX_INS_ASL , MOS65XX_AM_ZPX }, // 0x16
{ MOS65XX_INS_INVALID, MOS65XX_AM_NONE }, // 0x17
{ MOS65XX_INS_CLC , MOS65XX_AM_IMP }, // 0x18
{ MOS65XX_INS_ORA , MOS65XX_AM_ABSY }, // 0x19
{ MOS65XX_INS_NOP , MOS65XX_AM_IMP }, // 0x1a
{ MOS65XX_INS_INVALID, MOS65XX_AM_NONE }, // 0x1b
{ MOS65XX_INS_NOP , MOS65XX_AM_ABS }, // 0x1c
{ MOS65XX_INS_ORA , MOS65XX_AM_ABSX }, // 0x1d
{ MOS65XX_INS_ASL , MOS65XX_AM_ABSX }, // 0x1e
{ MOS65XX_INS_INVALID, MOS65XX_AM_NONE }, // 0x1f
{ MOS65XX_INS_JSR , MOS65XX_AM_ABS }, // 0x20
{ MOS65XX_INS_AND , MOS65XX_AM_INDX }, // 0x21
{ MOS65XX_INS_INVALID, MOS65XX_AM_NONE }, // 0x22
{ MOS65XX_INS_INVALID, MOS65XX_AM_NONE }, // 0x23
{ MOS65XX_INS_BIT , MOS65XX_AM_ZP }, // 0x24
{ MOS65XX_INS_AND , MOS65XX_AM_ZP }, // 0x25
{ MOS65XX_INS_ROL , MOS65XX_AM_ZP }, // 0x26
{ MOS65XX_INS_INVALID, MOS65XX_AM_NONE }, // 0x27
{ MOS65XX_INS_PLP , MOS65XX_AM_IMP }, // 0x28
{ MOS65XX_INS_AND , MOS65XX_AM_IMM }, // 0x29
{ MOS65XX_INS_ROL , MOS65XX_AM_ACC }, // 0x2a
{ MOS65XX_INS_INVALID, MOS65XX_AM_NONE }, // 0x2b
{ MOS65XX_INS_BIT , MOS65XX_AM_ABS }, // 0x2c
{ MOS65XX_INS_AND , MOS65XX_AM_ABS }, // 0x2d
{ MOS65XX_INS_ROL , MOS65XX_AM_ABS }, // 0x2e
{ MOS65XX_INS_INVALID, MOS65XX_AM_NONE }, // 0x2f
{ MOS65XX_INS_BMI , MOS65XX_AM_REL }, // 0x30
{ MOS65XX_INS_AND , MOS65XX_AM_INDY }, // 0x31
{ MOS65XX_INS_INVALID, MOS65XX_AM_NONE }, // 0x32
{ MOS65XX_INS_INVALID, MOS65XX_AM_NONE }, // 0x33
{ MOS65XX_INS_NOP , MOS65XX_AM_ZPX }, // 0x34
{ MOS65XX_INS_AND , MOS65XX_AM_ZPX }, // 0x35
{ MOS65XX_INS_ROL , MOS65XX_AM_ZPX }, // 0x36
{ MOS65XX_INS_INVALID, MOS65XX_AM_NONE }, // 0x37
{ MOS65XX_INS_SEC , MOS65XX_AM_IMP }, // 0x38
{ MOS65XX_INS_AND , MOS65XX_AM_ABSY }, // 0x39
{ MOS65XX_INS_NOP , MOS65XX_AM_IMP }, // 0x3a
{ MOS65XX_INS_INVALID, MOS65XX_AM_NONE }, // 0x3b
{ MOS65XX_INS_NOP , MOS65XX_AM_ABSX }, // 0x3c
{ MOS65XX_INS_AND , MOS65XX_AM_ABSX }, // 0x3d
{ MOS65XX_INS_ROL , MOS65XX_AM_ABSX }, // 0x3e
{ MOS65XX_INS_INVALID, MOS65XX_AM_NONE }, // 0x3f
{ MOS65XX_INS_RTI , MOS65XX_AM_IMP }, // 0x40
{ MOS65XX_INS_EOR , MOS65XX_AM_INDX }, // 0x41
{ MOS65XX_INS_INVALID, MOS65XX_AM_NONE }, // 0x42
{ MOS65XX_INS_INVALID, MOS65XX_AM_NONE }, // 0x43
{ MOS65XX_INS_NOP , MOS65XX_AM_ZP }, // 0x44
{ MOS65XX_INS_EOR , MOS65XX_AM_ZP }, // 0x45
{ MOS65XX_INS_LSR , MOS65XX_AM_ZP }, // 0x46
{ MOS65XX_INS_INVALID, MOS65XX_AM_NONE }, // 0x47
{ MOS65XX_INS_PHA , MOS65XX_AM_IMP }, // 0x48
{ MOS65XX_INS_EOR , MOS65XX_AM_IMM }, // 0x49
{ MOS65XX_INS_LSR , MOS65XX_AM_ACC }, // 0x4a
{ MOS65XX_INS_INVALID, MOS65XX_AM_NONE }, // 0x4b
{ MOS65XX_INS_JMP , MOS65XX_AM_ABS }, // 0x4c
{ MOS65XX_INS_EOR , MOS65XX_AM_ABS }, // 0x4d
{ MOS65XX_INS_LSR , MOS65XX_AM_ABS }, // 0x4e
{ MOS65XX_INS_INVALID, MOS65XX_AM_NONE }, // 0x4f
{ MOS65XX_INS_BVC , MOS65XX_AM_REL }, // 0x50
{ MOS65XX_INS_EOR , MOS65XX_AM_INDY }, // 0x51
{ MOS65XX_INS_INVALID, MOS65XX_AM_NONE }, // 0x52
{ MOS65XX_INS_INVALID, MOS65XX_AM_NONE }, // 0x53
{ MOS65XX_INS_NOP , MOS65XX_AM_ZPX }, // 0x54
{ MOS65XX_INS_EOR , MOS65XX_AM_ZPX }, // 0x55
{ MOS65XX_INS_LSR , MOS65XX_AM_ZPX }, // 0x56
{ MOS65XX_INS_INVALID, MOS65XX_AM_NONE }, // 0x57
{ MOS65XX_INS_CLI , MOS65XX_AM_IMP }, // 0x58
{ MOS65XX_INS_EOR , MOS65XX_AM_ABSY }, // 0x59
{ MOS65XX_INS_NOP , MOS65XX_AM_IMP }, // 0x5a
{ MOS65XX_INS_INVALID, MOS65XX_AM_NONE }, // 0x5b
{ MOS65XX_INS_NOP , MOS65XX_AM_ABSX }, // 0x5c
{ MOS65XX_INS_EOR , MOS65XX_AM_ABSX }, // 0x5d
{ MOS65XX_INS_LSR , MOS65XX_AM_ABSX }, // 0x5e
{ MOS65XX_INS_INVALID, MOS65XX_AM_NONE }, // 0x5f
{ MOS65XX_INS_RTS , MOS65XX_AM_IMP }, // 0x60
{ MOS65XX_INS_ADC , MOS65XX_AM_INDX }, // 0x61
{ MOS65XX_INS_INVALID, MOS65XX_AM_NONE }, // 0x62
{ MOS65XX_INS_INVALID, MOS65XX_AM_NONE }, // 0x63
{ MOS65XX_INS_NOP , MOS65XX_AM_ZP }, // 0x64
{ MOS65XX_INS_ADC , MOS65XX_AM_ZP }, // 0x65
{ MOS65XX_INS_ROR , MOS65XX_AM_ZP }, // 0x66
{ MOS65XX_INS_INVALID, MOS65XX_AM_NONE }, // 0x67
{ MOS65XX_INS_PLA , MOS65XX_AM_IMP }, // 0x68
{ MOS65XX_INS_ADC , MOS65XX_AM_IMM }, // 0x69
{ MOS65XX_INS_ROR , MOS65XX_AM_ACC }, // 0x6a
{ MOS65XX_INS_INVALID, MOS65XX_AM_NONE }, // 0x6b
{ MOS65XX_INS_JMP , MOS65XX_AM_IND }, // 0x6c
{ MOS65XX_INS_ADC , MOS65XX_AM_ABS }, // 0x6d
{ MOS65XX_INS_ROR , MOS65XX_AM_ABS }, // 0x6e
{ MOS65XX_INS_INVALID, MOS65XX_AM_NONE }, // 0x6f
{ MOS65XX_INS_BVS , MOS65XX_AM_REL }, // 0x70
{ MOS65XX_INS_ADC , MOS65XX_AM_INDY }, // 0x71
{ MOS65XX_INS_INVALID, MOS65XX_AM_NONE }, // 0x72
{ MOS65XX_INS_INVALID, MOS65XX_AM_NONE }, // 0x73
{ MOS65XX_INS_NOP , MOS65XX_AM_ZPX }, // 0x74
{ MOS65XX_INS_ADC , MOS65XX_AM_ZPX }, // 0x75
{ MOS65XX_INS_ROR , MOS65XX_AM_ZPX }, // 0x76
{ MOS65XX_INS_INVALID, MOS65XX_AM_NONE }, // 0x77
{ MOS65XX_INS_SEI , MOS65XX_AM_IMP }, // 0x78
{ MOS65XX_INS_ADC , MOS65XX_AM_ABSY }, // 0x79
{ MOS65XX_INS_NOP , MOS65XX_AM_IMP }, // 0x7a
{ MOS65XX_INS_INVALID, MOS65XX_AM_NONE }, // 0x7b
{ MOS65XX_INS_NOP , MOS65XX_AM_ABSX }, // 0x7c
{ MOS65XX_INS_ADC , MOS65XX_AM_ABSX }, // 0x7d
{ MOS65XX_INS_ROR , MOS65XX_AM_ABSX }, // 0x7e
{ MOS65XX_INS_INVALID, MOS65XX_AM_NONE }, // 0x7f
{ MOS65XX_INS_NOP , MOS65XX_AM_IMP }, // 0x80
{ MOS65XX_INS_STA , MOS65XX_AM_INDX }, // 0x81
{ MOS65XX_INS_NOP , MOS65XX_AM_IMP }, // 0x82
{ MOS65XX_INS_INVALID, MOS65XX_AM_NONE }, // 0x83
{ MOS65XX_INS_STY , MOS65XX_AM_ZP }, // 0x84
{ MOS65XX_INS_STA , MOS65XX_AM_ZP }, // 0x85
{ MOS65XX_INS_STX , MOS65XX_AM_ZP }, // 0x86
{ MOS65XX_INS_INVALID, MOS65XX_AM_NONE }, // 0x87
{ MOS65XX_INS_DEY , MOS65XX_AM_IMP }, // 0x88
{ MOS65XX_INS_NOP , MOS65XX_AM_IMP }, // 0x89
{ MOS65XX_INS_TXA , MOS65XX_AM_IMP }, // 0x8a
{ MOS65XX_INS_INVALID, MOS65XX_AM_NONE }, // 0x8b
{ MOS65XX_INS_STY , MOS65XX_AM_ABS }, // 0x8c
{ MOS65XX_INS_STA , MOS65XX_AM_ABS }, // 0x8d
{ MOS65XX_INS_STX , MOS65XX_AM_ABS }, // 0x8e
{ MOS65XX_INS_INVALID, MOS65XX_AM_NONE }, // 0x8f
{ MOS65XX_INS_BCC , MOS65XX_AM_REL }, // 0x90
{ MOS65XX_INS_STA , MOS65XX_AM_INDY }, // 0x91
{ MOS65XX_INS_INVALID, MOS65XX_AM_NONE }, // 0x92
{ MOS65XX_INS_INVALID, MOS65XX_AM_NONE }, // 0x93
{ MOS65XX_INS_STY , MOS65XX_AM_ZPX }, // 0x94
{ MOS65XX_INS_STA , MOS65XX_AM_ZPX }, // 0x95
{ MOS65XX_INS_STX , MOS65XX_AM_ZPY }, // 0x96
{ MOS65XX_INS_INVALID, MOS65XX_AM_NONE }, // 0x97
{ MOS65XX_INS_TYA , MOS65XX_AM_IMP }, // 0x98
{ MOS65XX_INS_STA , MOS65XX_AM_ABSY }, // 0x99
{ MOS65XX_INS_TXS , MOS65XX_AM_IMP }, // 0x9a
{ MOS65XX_INS_INVALID, MOS65XX_AM_NONE }, // 0x9b
{ MOS65XX_INS_INVALID, MOS65XX_AM_NONE }, // 0x9c
{ MOS65XX_INS_STA , MOS65XX_AM_ABSX }, // 0x9d
{ MOS65XX_INS_INVALID, MOS65XX_AM_NONE }, // 0x9e
{ MOS65XX_INS_INVALID, MOS65XX_AM_NONE }, // 0x9f
{ MOS65XX_INS_LDY , MOS65XX_AM_IMM }, // 0xa0
{ MOS65XX_INS_LDA , MOS65XX_AM_INDX }, // 0xa1
{ MOS65XX_INS_LDX , MOS65XX_AM_IMM }, // 0xa2
{ MOS65XX_INS_INVALID, MOS65XX_AM_NONE }, // 0xa3
{ MOS65XX_INS_LDY , MOS65XX_AM_ZP }, // 0xa4
{ MOS65XX_INS_LDA , MOS65XX_AM_ZP }, // 0xa5
{ MOS65XX_INS_LDX , MOS65XX_AM_ZP }, // 0xa6
{ MOS65XX_INS_INVALID, MOS65XX_AM_NONE }, // 0xa7
{ MOS65XX_INS_TAY , MOS65XX_AM_IMP }, // 0xa8
{ MOS65XX_INS_LDA , MOS65XX_AM_IMM }, // 0xa9
{ MOS65XX_INS_TAX , MOS65XX_AM_IMP }, // 0xaa
{ MOS65XX_INS_INVALID, MOS65XX_AM_NONE }, // 0xab
{ MOS65XX_INS_LDY , MOS65XX_AM_ABS }, // 0xac
{ MOS65XX_INS_LDA , MOS65XX_AM_ABS }, // 0xad
{ MOS65XX_INS_LDX , MOS65XX_AM_ABS }, // 0xae
{ MOS65XX_INS_INVALID, MOS65XX_AM_NONE }, // 0xaf
{ MOS65XX_INS_BCS , MOS65XX_AM_REL }, // 0xb0
{ MOS65XX_INS_LDA , MOS65XX_AM_INDY }, // 0xb1
{ MOS65XX_INS_INVALID, MOS65XX_AM_NONE }, // 0xb2
{ MOS65XX_INS_INVALID, MOS65XX_AM_NONE }, // 0xb3
{ MOS65XX_INS_LDY , MOS65XX_AM_ZPX }, // 0xb4
{ MOS65XX_INS_LDA , MOS65XX_AM_ZPX }, // 0xb5
{ MOS65XX_INS_LDX , MOS65XX_AM_ZPY }, // 0xb6
{ MOS65XX_INS_INVALID, MOS65XX_AM_NONE }, // 0xb7
{ MOS65XX_INS_CLV , MOS65XX_AM_IMP }, // 0xb8
{ MOS65XX_INS_LDA , MOS65XX_AM_ABSY }, // 0xb9
{ MOS65XX_INS_TSX , MOS65XX_AM_IMP }, // 0xba
{ MOS65XX_INS_INVALID, MOS65XX_AM_NONE }, // 0xbb
{ MOS65XX_INS_LDY , MOS65XX_AM_ABSX }, // 0xbc
{ MOS65XX_INS_LDA , MOS65XX_AM_ABSX }, // 0xbd
{ MOS65XX_INS_LDX , MOS65XX_AM_ABSY }, // 0xbe
{ MOS65XX_INS_INVALID, MOS65XX_AM_NONE }, // 0xbf
{ MOS65XX_INS_CPY , MOS65XX_AM_IMM }, // 0xc0
{ MOS65XX_INS_CMP , MOS65XX_AM_INDX }, // 0xc1
{ MOS65XX_INS_NOP , MOS65XX_AM_IMP }, // 0xc2
{ MOS65XX_INS_INVALID, MOS65XX_AM_NONE }, // 0xc3
{ MOS65XX_INS_CPY , MOS65XX_AM_ZP }, // 0xc4
{ MOS65XX_INS_CMP , MOS65XX_AM_ZP }, // 0xc5
{ MOS65XX_INS_DEC , MOS65XX_AM_ZP }, // 0xc6
{ MOS65XX_INS_INVALID, MOS65XX_AM_NONE }, // 0xc7
{ MOS65XX_INS_INY , MOS65XX_AM_IMP }, // 0xc8
{ MOS65XX_INS_CMP , MOS65XX_AM_IMM }, // 0xc9
{ MOS65XX_INS_DEX , MOS65XX_AM_IMP }, // 0xca
{ MOS65XX_INS_INVALID, MOS65XX_AM_NONE }, // 0xcb
{ MOS65XX_INS_CPY , MOS65XX_AM_ABS }, // 0xcc
{ MOS65XX_INS_CMP , MOS65XX_AM_ABS }, // 0xcd
{ MOS65XX_INS_DEC , MOS65XX_AM_ABS }, // 0xce
{ MOS65XX_INS_INVALID, MOS65XX_AM_NONE }, // 0xcf
{ MOS65XX_INS_BNE , MOS65XX_AM_REL }, // 0xd0
{ MOS65XX_INS_CMP , MOS65XX_AM_INDY }, // 0xd1
{ MOS65XX_INS_INVALID, MOS65XX_AM_NONE }, // 0xd2
{ MOS65XX_INS_INVALID, MOS65XX_AM_NONE }, // 0xd3
{ MOS65XX_INS_NOP , MOS65XX_AM_ZPX }, // 0xd4
{ MOS65XX_INS_CMP , MOS65XX_AM_ZPX }, // 0xd5
{ MOS65XX_INS_DEC , MOS65XX_AM_ZPX }, // 0xd6
{ MOS65XX_INS_INVALID, MOS65XX_AM_NONE }, // 0xd7
{ MOS65XX_INS_CLD , MOS65XX_AM_IMP }, // 0xd8
{ MOS65XX_INS_CMP , MOS65XX_AM_ABSY }, // 0xd9
{ MOS65XX_INS_NOP , MOS65XX_AM_IMP }, // 0xda
{ MOS65XX_INS_INVALID, MOS65XX_AM_NONE }, // 0xdb
{ MOS65XX_INS_NOP , MOS65XX_AM_ABSX }, // 0xdc
{ MOS65XX_INS_CMP , MOS65XX_AM_ABSX }, // 0xdd
{ MOS65XX_INS_DEC , MOS65XX_AM_ABSX }, // 0xde
{ MOS65XX_INS_INVALID, MOS65XX_AM_NONE }, // 0xdf
{ MOS65XX_INS_CPX , MOS65XX_AM_IMM }, // 0xe0
{ MOS65XX_INS_SBC , MOS65XX_AM_INDX }, // 0xe1
{ MOS65XX_INS_NOP , MOS65XX_AM_IMP }, // 0xe2
{ MOS65XX_INS_INVALID, MOS65XX_AM_NONE }, // 0xe3
{ MOS65XX_INS_CPX , MOS65XX_AM_ZP }, // 0xe4
{ MOS65XX_INS_SBC , MOS65XX_AM_ZP }, // 0xe5
{ MOS65XX_INS_INC , MOS65XX_AM_ZP }, // 0xe6
{ MOS65XX_INS_INVALID, MOS65XX_AM_NONE }, // 0xe7
{ MOS65XX_INS_INX , MOS65XX_AM_IMP }, // 0xe8
{ MOS65XX_INS_SBC , MOS65XX_AM_IMM }, // 0xe9
{ MOS65XX_INS_NOP , MOS65XX_AM_IMP }, // 0xea
{ MOS65XX_INS_INVALID, MOS65XX_AM_NONE }, // 0xeb
{ MOS65XX_INS_CPX , MOS65XX_AM_ABS }, // 0xec
{ MOS65XX_INS_SBC , MOS65XX_AM_ABS }, // 0xed
{ MOS65XX_INS_INC , MOS65XX_AM_ABS }, // 0xee
{ MOS65XX_INS_INVALID, MOS65XX_AM_NONE }, // 0xef
{ MOS65XX_INS_BEQ , MOS65XX_AM_REL }, // 0xf0
{ MOS65XX_INS_SBC , MOS65XX_AM_INDY }, // 0xf1
{ MOS65XX_INS_INVALID, MOS65XX_AM_NONE }, // 0xf2
{ MOS65XX_INS_INVALID, MOS65XX_AM_NONE }, // 0xf3
{ MOS65XX_INS_NOP , MOS65XX_AM_ZPX }, // 0xf4
{ MOS65XX_INS_SBC , MOS65XX_AM_ZPX }, // 0xf5
{ MOS65XX_INS_INC , MOS65XX_AM_ZPX }, // 0xf6
{ MOS65XX_INS_INVALID, MOS65XX_AM_NONE }, // 0xf7
{ MOS65XX_INS_SED , MOS65XX_AM_IMP }, // 0xf8
{ MOS65XX_INS_SBC , MOS65XX_AM_ABSY }, // 0xf9
{ MOS65XX_INS_NOP , MOS65XX_AM_IMP }, // 0xfa
{ MOS65XX_INS_INVALID, MOS65XX_AM_NONE }, // 0xfb
{ MOS65XX_INS_NOP , MOS65XX_AM_ABSX }, // 0xfc
{ MOS65XX_INS_SBC , MOS65XX_AM_ABSX }, // 0xfd
{ MOS65XX_INS_INC , MOS65XX_AM_ABSX }, // 0xfe
{ MOS65XX_INS_INVALID, MOS65XX_AM_NONE }, // 0xff
#include "m6502.inc"
#include "m65c02.inc"
#include "mw65c02.inc"
#include "m65816.inc"
};
static const char* RegNames[] = {
"invalid", "A", "X", "Y", "P", "SP"
"invalid", "A", "X", "Y", "P", "SP", "DP", "B", "K"
};
#ifndef CAPSTONE_DIET
@ -278,7 +30,7 @@ static const char* GroupNames[] = {
"jump",
"call",
"ret",
NULL,
"int",
"iret",
"branch_relative"
};
@ -291,135 +43,163 @@ typedef struct InstructionInfo {
} InstructionInfo;
static const struct InstructionInfo InstructionInfoTable[]= {
{ "invalid", MOS65XX_GRP_INVALID, MOS65XX_REG_INVALID, MOS65XX_REG_INVALID, false },
{ "adc", MOS65XX_GRP_INVALID, MOS65XX_REG_ACC, MOS65XX_REG_INVALID, true },
{ "and", MOS65XX_GRP_INVALID, MOS65XX_REG_ACC, MOS65XX_REG_INVALID, true },
{ "asl", MOS65XX_GRP_INVALID, MOS65XX_REG_INVALID, MOS65XX_REG_INVALID, true },
{ "bcc", MOS65XX_GRP_BRANCH_RELATIVE, MOS65XX_REG_INVALID, MOS65XX_REG_P, false },
{ "bcs", MOS65XX_GRP_BRANCH_RELATIVE, MOS65XX_REG_INVALID, MOS65XX_REG_P, false },
{ "beq", MOS65XX_GRP_BRANCH_RELATIVE, MOS65XX_REG_INVALID, MOS65XX_REG_P, false },
{ "bit", MOS65XX_GRP_INVALID, MOS65XX_REG_INVALID, MOS65XX_REG_INVALID, true },
{ "bmi", MOS65XX_GRP_BRANCH_RELATIVE, MOS65XX_REG_INVALID, MOS65XX_REG_P, false },
{ "bne", MOS65XX_GRP_BRANCH_RELATIVE, MOS65XX_REG_INVALID, MOS65XX_REG_P, false },
{ "bpl", MOS65XX_GRP_BRANCH_RELATIVE, MOS65XX_REG_INVALID, MOS65XX_REG_P, false },
{ "brk", MOS65XX_GRP_INVALID, MOS65XX_REG_SP, MOS65XX_REG_INVALID, false },
{ "bvc", MOS65XX_GRP_BRANCH_RELATIVE, MOS65XX_REG_INVALID, MOS65XX_REG_P, false },
{ "bvs", MOS65XX_GRP_BRANCH_RELATIVE, MOS65XX_REG_INVALID, MOS65XX_REG_P, false },
{ "clc", MOS65XX_GRP_INVALID, MOS65XX_REG_INVALID, MOS65XX_REG_INVALID, true },
{ "cld", MOS65XX_GRP_INVALID, MOS65XX_REG_INVALID, MOS65XX_REG_INVALID, true },
{ "cli", MOS65XX_GRP_INVALID, MOS65XX_REG_INVALID, MOS65XX_REG_INVALID, true },
{ "clv", MOS65XX_GRP_INVALID, MOS65XX_REG_INVALID, MOS65XX_REG_INVALID, true },
{ "cmp", MOS65XX_GRP_INVALID, MOS65XX_REG_INVALID, MOS65XX_REG_ACC, true },
{ "cpx", MOS65XX_GRP_INVALID, MOS65XX_REG_INVALID, MOS65XX_REG_X, true },
{ "cpy", MOS65XX_GRP_INVALID, MOS65XX_REG_INVALID, MOS65XX_REG_Y, true },
{ "dec", MOS65XX_GRP_INVALID, MOS65XX_REG_INVALID, MOS65XX_REG_INVALID, true },
{ "dex", MOS65XX_GRP_INVALID, MOS65XX_REG_X, MOS65XX_REG_X, true },
{ "dey", MOS65XX_GRP_INVALID, MOS65XX_REG_Y, MOS65XX_REG_Y, true },
{ "eor", MOS65XX_GRP_INVALID, MOS65XX_REG_INVALID, MOS65XX_REG_INVALID, true },
{ "inc", MOS65XX_GRP_INVALID, MOS65XX_REG_INVALID, MOS65XX_REG_INVALID, true },
{ "inx", MOS65XX_GRP_INVALID, MOS65XX_REG_X, MOS65XX_REG_X, true },
{ "iny", MOS65XX_GRP_INVALID, MOS65XX_REG_Y, MOS65XX_REG_Y, true },
{ "jmp", MOS65XX_GRP_JUMP, MOS65XX_REG_INVALID, MOS65XX_REG_INVALID, false },
{ "jsr", MOS65XX_GRP_CALL, MOS65XX_REG_INVALID, MOS65XX_REG_INVALID, false },
{ "lda", MOS65XX_GRP_INVALID, MOS65XX_REG_ACC, MOS65XX_REG_INVALID, true },
{ "ldx", MOS65XX_GRP_INVALID, MOS65XX_REG_X, MOS65XX_REG_INVALID, true },
{ "ldy", MOS65XX_GRP_INVALID, MOS65XX_REG_Y, MOS65XX_REG_INVALID, true },
{ "lsr", MOS65XX_GRP_INVALID, MOS65XX_REG_INVALID, MOS65XX_REG_INVALID, true },
{ "nop", MOS65XX_GRP_INVALID, MOS65XX_REG_INVALID, MOS65XX_REG_INVALID, false },
{ "ora", MOS65XX_GRP_INVALID, MOS65XX_REG_ACC, MOS65XX_REG_INVALID, true },
{ "pha", MOS65XX_GRP_INVALID, MOS65XX_REG_SP, MOS65XX_REG_ACC, false },
{ "pla", MOS65XX_GRP_INVALID, MOS65XX_REG_ACC, MOS65XX_REG_SP, true },
{ "php", MOS65XX_GRP_INVALID, MOS65XX_REG_SP, MOS65XX_REG_P, false },
{ "plp", MOS65XX_GRP_INVALID, MOS65XX_REG_INVALID, MOS65XX_REG_SP, true },
{ "rol", MOS65XX_GRP_INVALID, MOS65XX_REG_INVALID, MOS65XX_REG_INVALID, true },
{ "ror", MOS65XX_GRP_INVALID, MOS65XX_REG_INVALID, MOS65XX_REG_INVALID, true },
{ "rti", MOS65XX_GRP_IRET, MOS65XX_REG_SP, MOS65XX_REG_INVALID, true },
{ "rts", MOS65XX_GRP_RET, MOS65XX_REG_SP, MOS65XX_REG_INVALID, false },
{ "sbc", MOS65XX_GRP_INVALID, MOS65XX_REG_ACC, MOS65XX_REG_INVALID, true },
{ "sec", MOS65XX_GRP_INVALID, MOS65XX_REG_INVALID, MOS65XX_REG_INVALID, true },
{ "sed", MOS65XX_GRP_INVALID, MOS65XX_REG_INVALID, MOS65XX_REG_INVALID, true },
{ "sei", MOS65XX_GRP_INVALID, MOS65XX_REG_INVALID, MOS65XX_REG_INVALID, true },
{ "sta", MOS65XX_GRP_INVALID, MOS65XX_REG_INVALID, MOS65XX_REG_ACC, false },
{ "stx", MOS65XX_GRP_INVALID, MOS65XX_REG_INVALID, MOS65XX_REG_X, false },
{ "sty", MOS65XX_GRP_INVALID, MOS65XX_REG_INVALID, MOS65XX_REG_Y, false },
{ "tax", MOS65XX_GRP_INVALID, MOS65XX_REG_X, MOS65XX_REG_ACC, true },
{ "tay", MOS65XX_GRP_INVALID, MOS65XX_REG_Y, MOS65XX_REG_ACC, true },
{ "tsx", MOS65XX_GRP_INVALID, MOS65XX_REG_X, MOS65XX_REG_SP, true },
{ "txa", MOS65XX_GRP_INVALID, MOS65XX_REG_ACC, MOS65XX_REG_X, true },
{ "txs", MOS65XX_GRP_INVALID, MOS65XX_REG_SP, MOS65XX_REG_X, true },
{ "tya", MOS65XX_GRP_INVALID, MOS65XX_REG_ACC, MOS65XX_REG_Y, true },
#include "instruction_info.inc"
};
#endif
static int getInstructionLength(mos65xx_address_mode am)
{
switch(am) {
case MOS65XX_AM_NONE:
case MOS65XX_AM_ACC:
case MOS65XX_AM_IMP:
return 1;
case MOS65XX_AM_IMM:
case MOS65XX_AM_ZPX:
case MOS65XX_AM_ZPY:
case MOS65XX_AM_ZP:
case MOS65XX_AM_REL:
case MOS65XX_AM_INDX:
case MOS65XX_AM_INDY:
return 2;
case MOS65XX_AM_ABS:
case MOS65XX_AM_ABSX:
case MOS65XX_AM_ABSY:
case MOS65XX_AM_IND:
return 3;
default:
return 1;
}
}
#ifndef CAPSTONE_DIET
static void fillDetails(MCInst *MI, unsigned char opcode)
static void fillDetails(MCInst *MI, struct OpInfo opinfo, int cpu_type)
{
int i;
cs_detail *detail = MI->flat_insn->detail;
mos65xx_insn ins = OpInfoTable[opcode].ins;
mos65xx_address_mode am = OpInfoTable[opcode].am;
detail->mos65xx.am = am;
detail->mos65xx.modifies_flags = InstructionInfoTable[ins].modifies_status;
InstructionInfo insinfo = InstructionInfoTable[opinfo.ins];
detail->mos65xx.am = opinfo.am;
detail->mos65xx.modifies_flags = insinfo.modifies_status;
detail->groups_count = 0;
detail->regs_read_count = 0;
detail->regs_write_count = 0;
detail->mos65xx.op_count = 0;
if (InstructionInfoTable[ins].group_type != MOS65XX_GRP_INVALID) {
detail->groups[0] = InstructionInfoTable[ins].group_type;
if (insinfo.group_type != MOS65XX_GRP_INVALID) {
detail->groups[0] = insinfo.group_type;
detail->groups_count++;
}
if (InstructionInfoTable[ins].read != MOS65XX_REG_INVALID) {
detail->regs_read[detail->regs_read_count++] = InstructionInfoTable[ins].read;
} else if (OpInfoTable[opcode].am == MOS65XX_AM_ACC) {
detail->regs_read[detail->regs_read_count++] = MOS65XX_REG_ACC;
} else if (OpInfoTable[opcode].am == MOS65XX_AM_INDY || OpInfoTable[opcode].am == MOS65XX_AM_ABSY || OpInfoTable[opcode].am == MOS65XX_AM_ZPY) {
detail->regs_read[detail->regs_read_count++] = MOS65XX_REG_Y;
} else if (OpInfoTable[opcode].am == MOS65XX_AM_INDX || OpInfoTable[opcode].am == MOS65XX_AM_ABSX || OpInfoTable[opcode].am == MOS65XX_AM_ZPX) {
detail->regs_read[detail->regs_read_count++] = MOS65XX_REG_X;
if (opinfo.am == MOS65XX_AM_REL || opinfo.am == MOS65XX_AM_ZP_REL) {
detail->groups[0] = MOS65XX_GRP_BRANCH_RELATIVE;
detail->groups_count++;
}
if (InstructionInfoTable[ins].write != MOS65XX_REG_INVALID) {
detail->regs_write[detail->regs_write_count++] = InstructionInfoTable[ins].write;
} else if (OpInfoTable[opcode].am == MOS65XX_AM_ACC) {
if (insinfo.read != MOS65XX_REG_INVALID) {
detail->regs_read[detail->regs_read_count++] = insinfo.read;
} else switch(opinfo.am) {
case MOS65XX_AM_ACC:
detail->regs_read[detail->regs_read_count++] = MOS65XX_REG_ACC;
break;
case MOS65XX_AM_ZP_Y:
case MOS65XX_AM_ZP_IND_Y:
case MOS65XX_AM_ABS_Y:
case MOS65XX_AM_ZP_IND_LONG_Y:
detail->regs_read[detail->regs_read_count++] = MOS65XX_REG_Y;
break;
case MOS65XX_AM_ZP_X:
case MOS65XX_AM_ZP_X_IND:
case MOS65XX_AM_ABS_X:
case MOS65XX_AM_ABS_X_IND:
case MOS65XX_AM_ABS_LONG_X:
detail->regs_read[detail->regs_read_count++] = MOS65XX_REG_X;
break;
case MOS65XX_AM_SR:
detail->regs_read[detail->regs_read_count++] = MOS65XX_REG_SP;
break;
case MOS65XX_AM_SR_IND_Y:
detail->regs_read[detail->regs_read_count++] = MOS65XX_REG_SP;
detail->regs_read[detail->regs_read_count++] = MOS65XX_REG_Y;
break;
default:
break;
}
if (insinfo.write != MOS65XX_REG_INVALID) {
detail->regs_write[detail->regs_write_count++] = insinfo.write;
} else if (opinfo.am == MOS65XX_AM_ACC) {
detail->regs_write[detail->regs_write_count++] = MOS65XX_REG_ACC;
}
if (InstructionInfoTable[ins].modifies_status) {
switch(opinfo.ins) {
case MOS65XX_INS_ADC:
case MOS65XX_INS_SBC:
case MOS65XX_INS_ROL:
case MOS65XX_INS_ROR:
/* these read carry flag (and decimal for ADC/SBC) */
detail->regs_read[detail->regs_read_count++] = MOS65XX_REG_P;
break;
/* stack operations */
case MOS65XX_INS_JSL:
case MOS65XX_INS_JSR:
case MOS65XX_INS_PEA:
case MOS65XX_INS_PEI:
case MOS65XX_INS_PER:
case MOS65XX_INS_PHA:
case MOS65XX_INS_PHB:
case MOS65XX_INS_PHD:
case MOS65XX_INS_PHK:
case MOS65XX_INS_PHP:
case MOS65XX_INS_PHX:
case MOS65XX_INS_PHY:
case MOS65XX_INS_PLA:
case MOS65XX_INS_PLB:
case MOS65XX_INS_PLD:
case MOS65XX_INS_PLP:
case MOS65XX_INS_PLX:
case MOS65XX_INS_PLY:
case MOS65XX_INS_RTI:
case MOS65XX_INS_RTL:
case MOS65XX_INS_RTS:
detail->regs_read[detail->regs_read_count++] = MOS65XX_REG_SP;
detail->regs_write[detail->regs_write_count++] = MOS65XX_REG_SP;
break;
default:
break;
}
if (cpu_type == MOS65XX_CPU_TYPE_65816) {
switch (opinfo.am) {
case MOS65XX_AM_ZP:
case MOS65XX_AM_ZP_X:
case MOS65XX_AM_ZP_Y:
case MOS65XX_AM_ZP_IND:
case MOS65XX_AM_ZP_X_IND:
case MOS65XX_AM_ZP_IND_Y:
case MOS65XX_AM_ZP_IND_LONG:
case MOS65XX_AM_ZP_IND_LONG_Y:
detail->regs_read[detail->regs_read_count++] = MOS65XX_REG_DP;
break;
case MOS65XX_AM_BLOCK:
detail->regs_read[detail->regs_read_count++] = MOS65XX_REG_ACC;
detail->regs_read[detail->regs_read_count++] = MOS65XX_REG_X;
detail->regs_read[detail->regs_read_count++] = MOS65XX_REG_Y;
detail->regs_write[detail->regs_write_count++] = MOS65XX_REG_ACC;
detail->regs_write[detail->regs_write_count++] = MOS65XX_REG_X;
detail->regs_write[detail->regs_write_count++] = MOS65XX_REG_Y;
detail->regs_write[detail->regs_write_count++] = MOS65XX_REG_B;
break;
default:
break;
}
switch (opinfo.am) {
case MOS65XX_AM_ZP_IND:
case MOS65XX_AM_ZP_X_IND:
case MOS65XX_AM_ZP_IND_Y:
case MOS65XX_AM_ABS:
case MOS65XX_AM_ABS_X:
case MOS65XX_AM_ABS_Y:
case MOS65XX_AM_ABS_X_IND:
/* these depend on the databank to generate a 24-bit address */
/* exceptions: PEA, PEI, and JMP (abs) */
if (opinfo.ins == MOS65XX_INS_PEI || opinfo.ins == MOS65XX_INS_PEA) break;
detail->regs_read[detail->regs_read_count++] = MOS65XX_REG_B;
break;
default:
break;
}
}
if (insinfo.modifies_status) {
detail->regs_write[detail->regs_write_count++] = MOS65XX_REG_P;
}
switch(am) {
switch(opinfo.am) {
case MOS65XX_AM_IMP:
case MOS65XX_AM_REL:
break;
case MOS65XX_AM_IMM:
detail->mos65xx.operands[detail->mos65xx.op_count].type = MOS65XX_OP_IMM;
@ -431,10 +211,13 @@ static void fillDetails(MCInst *MI, unsigned char opcode)
detail->mos65xx.operands[detail->mos65xx.op_count].reg = MOS65XX_REG_ACC;
detail->mos65xx.op_count++;
break;
default:
detail->mos65xx.operands[detail->mos65xx.op_count].type = MOS65XX_OP_MEM;
detail->mos65xx.operands[detail->mos65xx.op_count].mem = MI->Operands[0].ImmVal;
detail->mos65xx.op_count++;
for (i = 0; i < MI->size; ++i) {
detail->mos65xx.operands[detail->mos65xx.op_count].type = MOS65XX_OP_MEM;
detail->mos65xx.operands[detail->mos65xx.op_count].mem = MI->Operands[i].ImmVal;
detail->mos65xx.op_count++;
}
break;
}
}
@ -443,12 +226,28 @@ static void fillDetails(MCInst *MI, unsigned char opcode)
void MOS65XX_printInst(MCInst *MI, struct SStream *O, void *PrinterInfo)
{
#ifndef CAPSTONE_DIET
unsigned char opcode = MI->Opcode;
unsigned opcode = MCInst_getOpcode(MI);
mos65xx_info *info = (mos65xx_info *)PrinterInfo;
SStream_concat0(O, InstructionInfoTable[OpInfoTable[MI->Opcode].ins].name);
OpInfo opinfo = OpInfoTable[opcode];
const char *prefix = info->hex_prefix ? info->hex_prefix : "0x";
SStream_concat0(O, InstructionInfoTable[opinfo.ins].name);
switch (opinfo.ins) {
/* special case - bit included as part of the instruction name */
case MOS65XX_INS_BBR:
case MOS65XX_INS_BBS:
case MOS65XX_INS_RMB:
case MOS65XX_INS_SMB:
SStream_concat(O, "%d", (opcode >> 4) & 0x07);
break;
default:
break;
}
unsigned int value = MI->Operands[0].ImmVal;
switch (OpInfoTable[opcode].am) {
switch (opinfo.am) {
default:
break;
@ -459,49 +258,113 @@ void MOS65XX_printInst(MCInst *MI, struct SStream *O, void *PrinterInfo)
SStream_concat(O, " a");
break;
case MOS65XX_AM_ABS:
SStream_concat(O, " $%04X", value);
break;
case MOS65XX_AM_IMM:
SStream_concat(O, " #$%02X", value);
if (MI->imm_size == 1)
SStream_concat(O, " #%s%02x", prefix, value);
else
SStream_concat(O, " #%s%04x", prefix, value);
break;
case MOS65XX_AM_ZP:
SStream_concat(O, " $%02X", value);
SStream_concat(O, " %s%02x", prefix, value);
break;
case MOS65XX_AM_ABSX:
SStream_concat(O, " $%04X,x", value);
case MOS65XX_AM_ABS:
SStream_concat(O, " %s%04x", prefix, value);
break;
case MOS65XX_AM_ABSY:
SStream_concat(O, " $%04X,y", value);
case MOS65XX_AM_ABS_LONG_X:
SStream_concat(O, " %s%06x, x", prefix, value);
break;
case MOS65XX_AM_ZPX:
SStream_concat(O, " $%02X,x", value);
case MOS65XX_AM_INT:
SStream_concat(O, " %s%02x", prefix, value);
break;
case MOS65XX_AM_ZPY:
SStream_concat(O, " $%02X,y", value);
case MOS65XX_AM_ABS_X:
SStream_concat(O, " %s%04x, x", prefix, value);
break;
case MOS65XX_AM_ABS_Y:
SStream_concat(O, " %s%04x, y", prefix, value);
break;
case MOS65XX_AM_ABS_LONG:
SStream_concat(O, " %s%06x", prefix, value);
break;
case MOS65XX_AM_ZP_X:
SStream_concat(O, " %s%02x, x", prefix, value);
break;
case MOS65XX_AM_ZP_Y:
SStream_concat(O, " %s%02x, y", prefix, value);
break;
case MOS65XX_AM_REL:
SStream_concat(O, " $%04X", MI->address + (signed char) value + 2);
if (MI->op1_size == 1)
value = 2 + (signed char)value;
else
value = 3 + (signed short)value;
SStream_concat(O, " %s%04x", prefix,
(MI->address + value) & 0xffff);
break;
case MOS65XX_AM_IND:
SStream_concat(O, " ($%04X)", value);
case MOS65XX_AM_ABS_IND:
SStream_concat(O, " (%s%04x)", prefix, value);
break;
case MOS65XX_AM_INDX:
SStream_concat(O, " ($%02X,x)", value);
case MOS65XX_AM_ABS_X_IND:
SStream_concat(O, " (%s%04x, x)", prefix, value);
break;
case MOS65XX_AM_INDY:
SStream_concat(O, " ($%02X),y", value);
case MOS65XX_AM_ABS_IND_LONG:
SStream_concat(O, " [%s%04x]", prefix, value);
break;
case MOS65XX_AM_ZP_IND:
SStream_concat(O, " (%s%02x)", prefix, value);
break;
case MOS65XX_AM_ZP_X_IND:
SStream_concat(O, " (%s%02x, x)", prefix, value);
break;
case MOS65XX_AM_ZP_IND_Y:
SStream_concat(O, " (%s%02x), y", prefix, value);
break;
case MOS65XX_AM_ZP_IND_LONG:
SStream_concat(O, " [%s%02x]", prefix, value);
break;
case MOS65XX_AM_ZP_IND_LONG_Y:
SStream_concat(O, " [%s%02x], y", prefix, value);
break;
case MOS65XX_AM_SR:
SStream_concat(O, " %s%02x, s", prefix, value);
break;
case MOS65XX_AM_SR_IND_Y:
SStream_concat(O, " (%s%02x, s), y", prefix, value);
break;
case MOS65XX_AM_BLOCK:
SStream_concat(O, " %s%02x, %s%02x",
prefix, MI->Operands[0].ImmVal,
prefix, MI->Operands[1].ImmVal);
break;
case MOS65XX_AM_ZP_REL:
value = 3 + (signed char)MI->Operands[1].ImmVal;
/* BBR0, zp, rel and BBS0, zp, rel */
SStream_concat(O, " %s%02x, %s%04x",
prefix, MI->Operands[0].ImmVal,
prefix, (MI->address + value) & 0xffff);
break;
}
#endif
}
@ -509,43 +372,105 @@ void MOS65XX_printInst(MCInst *MI, struct SStream *O, void *PrinterInfo)
bool MOS65XX_getInstruction(csh ud, const uint8_t *code, size_t code_len,
MCInst *MI, uint16_t *size, uint64_t address, void *inst_info)
{
int i;
unsigned char opcode;
unsigned char len;
mos65xx_insn ins;
unsigned cpu_offset = 0;
int cpu_type = MOS65XX_CPU_TYPE_6502;
cs_struct* handle = MI->csh;
mos65xx_info *info = (mos65xx_info *)handle->printer_info;
OpInfo opinfo;
if (code_len == 0) {
*size = 1;
return false;
}
cpu_type = info->cpu_type;
cpu_offset = cpu_type * 256;
opcode = code[0];
ins = OpInfoTable[opcode].ins;
if (ins == MOS65XX_INS_INVALID) {
opinfo = OpInfoTable[cpu_offset + opcode];
if (opinfo.ins == MOS65XX_INS_INVALID) {
*size = 1;
return false;
}
len = getInstructionLength(OpInfoTable[opcode].am);
len = opinfo.operand_bytes + 1;
if (cpu_type == MOS65XX_CPU_TYPE_65816 && opinfo.am == MOS65XX_AM_IMM) {
switch(opinfo.ins) {
case MOS65XX_INS_CPX:
case MOS65XX_INS_CPY:
case MOS65XX_INS_LDX:
case MOS65XX_INS_LDY:
if (info->long_x) ++len;
break;
case MOS65XX_INS_ADC:
case MOS65XX_INS_AND:
case MOS65XX_INS_BIT:
case MOS65XX_INS_CMP:
case MOS65XX_INS_EOR:
case MOS65XX_INS_LDA:
case MOS65XX_INS_ORA:
case MOS65XX_INS_SBC:
if (info->long_m) ++len;
break;
default:
break;
}
}
if (code_len < len) {
*size = 1;
return false;
}
MI->address = address;
MI->Opcode = opcode;
MI->OpcodePub = ins;
MI->size = 0;
MCInst_setOpcode(MI, cpu_offset + opcode);
MCInst_setOpcodePub(MI, opinfo.ins);
*size = len;
if (len == 2) {
MCOperand_CreateImm0(MI, code[1]);
} else
if (len == 3) {
MCOperand_CreateImm0(MI, (code[2]<<8) | code[1]);
/* needed to differentiate relative vs relative long */
MI->op1_size = len - 1;
if (opinfo.ins == MOS65XX_INS_NOP) {
for (i = 1; i < len; ++i)
MCOperand_CreateImm0(MI, code[i]);
}
switch (opinfo.am) {
case MOS65XX_AM_ZP_REL:
MCOperand_CreateImm0(MI, code[1]);
MCOperand_CreateImm0(MI, code[2]);
break;
case MOS65XX_AM_BLOCK:
MCOperand_CreateImm0(MI, code[2]);
MCOperand_CreateImm0(MI, code[1]);
break;
case MOS65XX_AM_IMP:
case MOS65XX_AM_ACC:
break;
case MOS65XX_AM_IMM:
MI->has_imm = 1;
MI->imm_size = len - 1;
/* 65816 immediate is either 1 or 2 bytes */
/* drop through */
default:
if (len == 2)
MCOperand_CreateImm0(MI, code[1]);
else if (len == 3)
MCOperand_CreateImm0(MI, (code[2]<<8) | code[1]);
else if (len == 4)
MCOperand_CreateImm0(MI, (code[3]<<16) | (code[2]<<8) | code[1]);
break;
}
#ifndef CAPSTONE_DIET
if (MI->flat_insn->detail) {
fillDetails(MI, opcode);
fillDetails(MI, opinfo, cpu_type);
}
#endif
@ -578,7 +503,8 @@ const char* MOS65XX_reg_name(csh handle, unsigned int reg)
void MOS65XX_get_insn_id(cs_struct *h, cs_insn *insn, unsigned int id)
{
if (id < 256) {
/* id is cpu_offset + opcode */
if (id < ARR_SIZE(OpInfoTable)) {
insn->id = OpInfoTable[id].ins;
}
}

23
arch/MOS65XX/MOS65XXDisassemblerInternals.h Normal file
View File

@ -0,0 +1,23 @@
#ifndef CS_MOS65XXDISASSEMBLERINTERNALS_H
#define CS_MOS65XXDISASSEMBLERINTERNALS_H
#include "capstone/mos65xx.h"
enum {
MOS65XX_CPU_TYPE_6502,
MOS65XX_CPU_TYPE_65C02,
MOS65XX_CPU_TYPE_W65C02,
MOS65XX_CPU_TYPE_65816,
};
typedef struct mos65xx_info {
const char *hex_prefix;
unsigned cpu_type;
unsigned long_m;
unsigned long_x;
} mos65xx_info;
#endif

54
arch/MOS65XX/MOS65XXModule.c
View File

@ -6,27 +6,73 @@
#include "../../utils.h"
#include "../../MCRegisterInfo.h"
#include "MOS65XXDisassembler.h"
#include "MOS65XXDisassemblerInternals.h"
#include "MOS65XXModule.h"
cs_err MOS65XX_global_init(cs_struct *ud)
{
// verify if requested mode is valid
if (ud->mode)
return CS_ERR_MODE;
mos65xx_info *info;
info = cs_mem_malloc(sizeof(*info));
info->hex_prefix = NULL;
info->cpu_type = MOS65XX_CPU_TYPE_6502;
info->long_m = 0;
info->long_x = 0;
ud->printer = MOS65XX_printInst;
ud->printer_info = NULL;
ud->printer_info = info;
ud->insn_id = MOS65XX_get_insn_id;
ud->insn_name = MOS65XX_insn_name;
ud->group_name = MOS65XX_group_name;
ud->disasm = MOS65XX_getInstruction;
ud->reg_name = MOS65XX_reg_name;
if (ud->mode) {
MOS65XX_option(ud, CS_OPT_MODE, ud->mode);
}
return CS_ERR_OK;
}
cs_err MOS65XX_option(cs_struct *handle, cs_opt_type type, size_t value)
{
mos65xx_info *info = (mos65xx_info *)handle->printer_info;
switch(type) {
default:
break;
case CS_OPT_MODE:
if (value & CS_MODE_MOS65XX_6502)
info->cpu_type = MOS65XX_CPU_TYPE_6502;
if (value & CS_MODE_MOS65XX_65C02)
info->cpu_type = MOS65XX_CPU_TYPE_65C02;
if (value & CS_MODE_MOS65XX_W65C02)
info->cpu_type = MOS65XX_CPU_TYPE_W65C02;
if (value & (CS_MODE_MOS65XX_65816|CS_MODE_MOS65XX_65816_LONG_M|CS_MODE_MOS65XX_65816_LONG_X))
info->cpu_type = MOS65XX_CPU_TYPE_65816;
info->long_m = value & CS_MODE_MOS65XX_65816_LONG_M ? 1 : 0;
info->long_x = value & CS_MODE_MOS65XX_65816_LONG_X ? 1 : 0;
handle->mode = (cs_mode)value;
break;
case CS_OPT_SYNTAX:
switch(value) {
default:
// wrong syntax value
handle->errnum = CS_ERR_OPTION;
return CS_ERR_OPTION;
case CS_OPT_SYNTAX_DEFAULT:
info->hex_prefix = NULL;
break;
case CS_OPT_SYNTAX_MOTOROLA:
info->hex_prefix = "$";
break;
}
handle->syntax = (int)value;
break;
}
return CS_ERR_OK;
}

106
arch/MOS65XX/instruction_info.inc Normal file
View File

@ -0,0 +1,106 @@
/*
* MOS65XX_GRP_BRANCH_RELATIVE handled elsewhere based on address mode
* MOS65XX_REG_SP handled elsewhere for push/pop instructions
* BLOCK moves handled elsewhere.
* MOS65XX_REG_Y handled elsewhere for abs,y zp, y etc
* MOS65XX_REG_X handled elsewhere for abs,x zp, x etc
* MOS65XX_REG_DP handled elsewhere for zp zp,x zp,y etc
*/
{ "invalid", MOS65XX_GRP_INVALID, MOS65XX_REG_INVALID, MOS65XX_REG_INVALID, false },
{ "adc", MOS65XX_GRP_INVALID, MOS65XX_REG_ACC, MOS65XX_REG_ACC, true },
{ "and", MOS65XX_GRP_INVALID, MOS65XX_REG_ACC, MOS65XX_REG_ACC, true },
{ "asl", MOS65XX_GRP_INVALID, MOS65XX_REG_INVALID, MOS65XX_REG_INVALID, true },
{ "bbr", MOS65XX_GRP_JUMP, MOS65XX_REG_INVALID, MOS65XX_REG_P, false },
{ "bbs", MOS65XX_GRP_JUMP, MOS65XX_REG_INVALID, MOS65XX_REG_P, false },
{ "bcc", MOS65XX_GRP_JUMP, MOS65XX_REG_INVALID, MOS65XX_REG_P, false },
{ "bcs", MOS65XX_GRP_JUMP, MOS65XX_REG_INVALID, MOS65XX_REG_P, false },
{ "beq", MOS65XX_GRP_JUMP, MOS65XX_REG_INVALID, MOS65XX_REG_P, false },
{ "bit", MOS65XX_GRP_INVALID, MOS65XX_REG_INVALID, MOS65XX_REG_ACC, true },
{ "bmi", MOS65XX_GRP_JUMP, MOS65XX_REG_INVALID, MOS65XX_REG_P, false },
{ "bne", MOS65XX_GRP_JUMP, MOS65XX_REG_INVALID, MOS65XX_REG_P, false },
{ "bpl", MOS65XX_GRP_JUMP, MOS65XX_REG_INVALID, MOS65XX_REG_P, false },
{ "bra", MOS65XX_GRP_JUMP, MOS65XX_REG_INVALID, MOS65XX_REG_INVALID, false },
{ "brk", MOS65XX_GRP_INT, MOS65XX_REG_INVALID, MOS65XX_REG_INVALID, false },
{ "brl", MOS65XX_GRP_JUMP, MOS65XX_REG_INVALID, MOS65XX_REG_INVALID, false },
{ "bvc", MOS65XX_GRP_JUMP, MOS65XX_REG_INVALID, MOS65XX_REG_P, false },
{ "bvs", MOS65XX_GRP_JUMP, MOS65XX_REG_INVALID, MOS65XX_REG_P, false },
{ "clc", MOS65XX_GRP_INVALID, MOS65XX_REG_INVALID, MOS65XX_REG_INVALID, true },
{ "cld", MOS65XX_GRP_INVALID, MOS65XX_REG_INVALID, MOS65XX_REG_INVALID, true },
{ "cli", MOS65XX_GRP_INVALID, MOS65XX_REG_INVALID, MOS65XX_REG_INVALID, true },
{ "clv", MOS65XX_GRP_INVALID, MOS65XX_REG_INVALID, MOS65XX_REG_INVALID, true },
{ "cmp", MOS65XX_GRP_INVALID, MOS65XX_REG_INVALID, MOS65XX_REG_ACC, true },
{ "cop", MOS65XX_GRP_INT, MOS65XX_REG_INVALID, MOS65XX_REG_INVALID, false },
{ "cpx", MOS65XX_GRP_INVALID, MOS65XX_REG_INVALID, MOS65XX_REG_X, true },
{ "cpy", MOS65XX_GRP_INVALID, MOS65XX_REG_INVALID, MOS65XX_REG_Y, true },
{ "dec", MOS65XX_GRP_INVALID, MOS65XX_REG_INVALID, MOS65XX_REG_INVALID, true },
{ "dex", MOS65XX_GRP_INVALID, MOS65XX_REG_X, MOS65XX_REG_X, true },
{ "dey", MOS65XX_GRP_INVALID, MOS65XX_REG_Y, MOS65XX_REG_Y, true },
{ "eor", MOS65XX_GRP_INVALID, MOS65XX_REG_ACC, MOS65XX_REG_ACC, true },
{ "inc", MOS65XX_GRP_INVALID, MOS65XX_REG_INVALID, MOS65XX_REG_INVALID, true },
{ "inx", MOS65XX_GRP_INVALID, MOS65XX_REG_X, MOS65XX_REG_X, true },
{ "iny", MOS65XX_GRP_INVALID, MOS65XX_REG_Y, MOS65XX_REG_Y, true },
{ "jml", MOS65XX_GRP_JUMP, MOS65XX_REG_INVALID, MOS65XX_REG_INVALID, false },
{ "jmp", MOS65XX_GRP_JUMP, MOS65XX_REG_INVALID, MOS65XX_REG_INVALID, false },
{ "jsl", MOS65XX_GRP_CALL, MOS65XX_REG_INVALID, MOS65XX_REG_INVALID, false },
{ "jsr", MOS65XX_GRP_CALL, MOS65XX_REG_INVALID, MOS65XX_REG_INVALID, false },
{ "lda", MOS65XX_GRP_INVALID, MOS65XX_REG_ACC, MOS65XX_REG_INVALID, true },
{ "ldx", MOS65XX_GRP_INVALID, MOS65XX_REG_X, MOS65XX_REG_INVALID, true },
{ "ldy", MOS65XX_GRP_INVALID, MOS65XX_REG_Y, MOS65XX_REG_INVALID, true },
{ "lsr", MOS65XX_GRP_INVALID, MOS65XX_REG_INVALID, MOS65XX_REG_INVALID, true },
{ "mvn", MOS65XX_GRP_INVALID, MOS65XX_REG_INVALID, MOS65XX_REG_INVALID, false },
{ "mvp", MOS65XX_GRP_INVALID, MOS65XX_REG_INVALID, MOS65XX_REG_INVALID, false },
{ "nop", MOS65XX_GRP_INVALID, MOS65XX_REG_INVALID, MOS65XX_REG_INVALID, false },
{ "ora", MOS65XX_GRP_INVALID, MOS65XX_REG_ACC, MOS65XX_REG_ACC, true },
{ "pea", MOS65XX_GRP_INVALID, MOS65XX_REG_INVALID, MOS65XX_REG_INVALID, false },
{ "pei", MOS65XX_GRP_INVALID, MOS65XX_REG_INVALID, MOS65XX_REG_INVALID, false },
{ "per", MOS65XX_GRP_INVALID, MOS65XX_REG_INVALID, MOS65XX_REG_INVALID, false },
{ "pha", MOS65XX_GRP_INVALID, MOS65XX_REG_INVALID, MOS65XX_REG_ACC, false },
{ "phb", MOS65XX_GRP_INVALID, MOS65XX_REG_INVALID, MOS65XX_REG_B, false },
{ "phd", MOS65XX_GRP_INVALID, MOS65XX_REG_INVALID, MOS65XX_REG_DP, false },
{ "phk", MOS65XX_GRP_INVALID, MOS65XX_REG_INVALID, MOS65XX_REG_K, false },
{ "php", MOS65XX_GRP_INVALID, MOS65XX_REG_INVALID, MOS65XX_REG_P, false },
{ "phx", MOS65XX_GRP_INVALID, MOS65XX_REG_INVALID, MOS65XX_REG_X, false },
{ "phy", MOS65XX_GRP_INVALID, MOS65XX_REG_INVALID, MOS65XX_REG_Y, false },
{ "pla", MOS65XX_GRP_INVALID, MOS65XX_REG_ACC, MOS65XX_REG_INVALID, true },
{ "plb", MOS65XX_GRP_INVALID, MOS65XX_REG_B, MOS65XX_REG_INVALID, true },
{ "pld", MOS65XX_GRP_INVALID, MOS65XX_REG_DP, MOS65XX_REG_INVALID, true },
{ "plp", MOS65XX_GRP_INVALID, MOS65XX_REG_INVALID, MOS65XX_REG_INVALID, true },
{ "plx", MOS65XX_GRP_INVALID, MOS65XX_REG_X, MOS65XX_REG_INVALID, true },
{ "ply", MOS65XX_GRP_INVALID, MOS65XX_REG_Y, MOS65XX_REG_INVALID, true },
{ "rep", MOS65XX_GRP_INVALID, MOS65XX_REG_INVALID, MOS65XX_REG_INVALID, true },
{ "rmb", MOS65XX_GRP_INVALID, MOS65XX_REG_INVALID, MOS65XX_REG_INVALID, false },
{ "rol", MOS65XX_GRP_INVALID, MOS65XX_REG_INVALID, MOS65XX_REG_INVALID, true },
{ "ror", MOS65XX_GRP_INVALID, MOS65XX_REG_INVALID, MOS65XX_REG_INVALID, true },
{ "rti", MOS65XX_GRP_IRET, MOS65XX_REG_INVALID, MOS65XX_REG_INVALID, true },
{ "rtl", MOS65XX_GRP_RET, MOS65XX_REG_INVALID, MOS65XX_REG_INVALID, false },
{ "rts", MOS65XX_GRP_RET, MOS65XX_REG_INVALID, MOS65XX_REG_INVALID, false },
{ "sbc", MOS65XX_GRP_INVALID, MOS65XX_REG_ACC, MOS65XX_REG_ACC, true },
{ "sec", MOS65XX_GRP_INVALID, MOS65XX_REG_INVALID, MOS65XX_REG_INVALID, true },
{ "sed", MOS65XX_GRP_INVALID, MOS65XX_REG_INVALID, MOS65XX_REG_INVALID, true },
{ "sei", MOS65XX_GRP_INVALID, MOS65XX_REG_INVALID, MOS65XX_REG_INVALID, true },
{ "sep", MOS65XX_GRP_INVALID, MOS65XX_REG_INVALID, MOS65XX_REG_INVALID, true },
{ "smb", MOS65XX_GRP_INVALID, MOS65XX_REG_INVALID, MOS65XX_REG_INVALID, false },
{ "sta", MOS65XX_GRP_INVALID, MOS65XX_REG_INVALID, MOS65XX_REG_ACC, false },
{ "stp", MOS65XX_GRP_INVALID, MOS65XX_REG_INVALID, MOS65XX_REG_INVALID, false },
{ "stx", MOS65XX_GRP_INVALID, MOS65XX_REG_INVALID, MOS65XX_REG_X, false },
{ "sty", MOS65XX_GRP_INVALID, MOS65XX_REG_INVALID, MOS65XX_REG_Y, false },
{ "stz", MOS65XX_GRP_INVALID, MOS65XX_REG_INVALID, MOS65XX_REG_INVALID, false },
{ "tax", MOS65XX_GRP_INVALID, MOS65XX_REG_X, MOS65XX_REG_ACC, true },
{ "tay", MOS65XX_GRP_INVALID, MOS65XX_REG_Y, MOS65XX_REG_ACC, true },
{ "tcd", MOS65XX_GRP_INVALID, MOS65XX_REG_DP, MOS65XX_REG_ACC, true },
{ "tcs", MOS65XX_GRP_INVALID, MOS65XX_REG_SP, MOS65XX_REG_ACC, false },
{ "tdc", MOS65XX_GRP_INVALID, MOS65XX_REG_ACC, MOS65XX_REG_DP, true },
{ "trb", MOS65XX_GRP_INVALID, MOS65XX_REG_INVALID, MOS65XX_REG_ACC, true },
{ "tsb", MOS65XX_GRP_INVALID, MOS65XX_REG_INVALID, MOS65XX_REG_ACC, true },
{ "tsc", MOS65XX_GRP_INVALID, MOS65XX_REG_ACC, MOS65XX_REG_SP, true },
{ "tsx", MOS65XX_GRP_INVALID, MOS65XX_REG_X, MOS65XX_REG_SP, true },
{ "txa", MOS65XX_GRP_INVALID, MOS65XX_REG_ACC, MOS65XX_REG_X, true },
{ "txs", MOS65XX_GRP_INVALID, MOS65XX_REG_SP, MOS65XX_REG_X, false },
{ "txy", MOS65XX_GRP_INVALID, MOS65XX_REG_Y, MOS65XX_REG_X, true },
{ "tya", MOS65XX_GRP_INVALID, MOS65XX_REG_ACC, MOS65XX_REG_Y, true },
{ "tyx", MOS65XX_GRP_INVALID, MOS65XX_REG_X, MOS65XX_REG_Y, true },
{ "wai", MOS65XX_GRP_INVALID, MOS65XX_REG_INVALID, MOS65XX_REG_INVALID, false },
{ "wdm", MOS65XX_GRP_INVALID, MOS65XX_REG_INVALID, MOS65XX_REG_INVALID, false },
{ "xba", MOS65XX_GRP_INVALID, MOS65XX_REG_ACC, MOS65XX_REG_ACC, true },
{ "xce", MOS65XX_GRP_INVALID, MOS65XX_REG_INVALID, MOS65XX_REG_INVALID, true },

256
arch/MOS65XX/m6502.inc Normal file
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@ -0,0 +1,256 @@
{ MOS65XX_INS_BRK , MOS65XX_AM_INT , 1 }, // 0x00
{ MOS65XX_INS_ORA , MOS65XX_AM_ZP_X_IND , 1 }, // 0x01
{ MOS65XX_INS_INVALID, MOS65XX_AM_NONE , 0 }, // 0x02
{ MOS65XX_INS_INVALID, MOS65XX_AM_NONE , 0 }, // 0x03
{ MOS65XX_INS_INVALID, MOS65XX_AM_NONE , 0 }, // 0x04
{ MOS65XX_INS_ORA , MOS65XX_AM_ZP , 1 }, // 0x05
{ MOS65XX_INS_ASL , MOS65XX_AM_ZP , 1 }, // 0x06
{ MOS65XX_INS_INVALID, MOS65XX_AM_NONE , 0 }, // 0x07
{ MOS65XX_INS_PHP , MOS65XX_AM_IMP , 0 }, // 0x08
{ MOS65XX_INS_ORA , MOS65XX_AM_IMM , 1 }, // 0x09
{ MOS65XX_INS_ASL , MOS65XX_AM_ACC , 0 }, // 0x0a
{ MOS65XX_INS_INVALID, MOS65XX_AM_NONE , 0 }, // 0x0b
{ MOS65XX_INS_INVALID, MOS65XX_AM_NONE , 0 }, // 0x0c
{ MOS65XX_INS_ORA , MOS65XX_AM_ABS , 2 }, // 0x0d
{ MOS65XX_INS_ASL , MOS65XX_AM_ABS , 2 }, // 0x0e
{ MOS65XX_INS_INVALID, MOS65XX_AM_NONE , 0 }, // 0x0f
{ MOS65XX_INS_BPL , MOS65XX_AM_REL , 1 }, // 0x10
{ MOS65XX_INS_ORA , MOS65XX_AM_ZP_IND_Y , 1 }, // 0x11
{ MOS65XX_INS_INVALID, MOS65XX_AM_NONE , 0 }, // 0x12
{ MOS65XX_INS_INVALID, MOS65XX_AM_NONE , 0 }, // 0x13
{ MOS65XX_INS_INVALID, MOS65XX_AM_NONE , 0 }, // 0x14
{ MOS65XX_INS_ORA , MOS65XX_AM_ZP_X , 1 }, // 0x15
{ MOS65XX_INS_ASL , MOS65XX_AM_ZP_X , 1 }, // 0x16
{ MOS65XX_INS_INVALID, MOS65XX_AM_NONE , 0 }, // 0x17
{ MOS65XX_INS_CLC , MOS65XX_AM_IMP , 0 }, // 0x18
{ MOS65XX_INS_ORA , MOS65XX_AM_ABS_Y , 2 }, // 0x19
{ MOS65XX_INS_INVALID, MOS65XX_AM_NONE , 0 }, // 0x1a
{ MOS65XX_INS_INVALID, MOS65XX_AM_NONE , 0 }, // 0x1b
{ MOS65XX_INS_INVALID, MOS65XX_AM_NONE , 0 }, // 0x1c
{ MOS65XX_INS_ORA , MOS65XX_AM_ABS_X , 2 }, // 0x1d
{ MOS65XX_INS_ASL , MOS65XX_AM_ABS_X , 2 }, // 0x1e
{ MOS65XX_INS_INVALID, MOS65XX_AM_NONE , 0 }, // 0x1f
{ MOS65XX_INS_JSR , MOS65XX_AM_ABS , 2 }, // 0x20
{ MOS65XX_INS_AND , MOS65XX_AM_ZP_X_IND , 1 }, // 0x21
{ MOS65XX_INS_INVALID, MOS65XX_AM_NONE , 0 }, // 0x22
{ MOS65XX_INS_INVALID, MOS65XX_AM_NONE , 0 }, // 0x23
{ MOS65XX_INS_BIT , MOS65XX_AM_ZP , 1 }, // 0x24
{ MOS65XX_INS_AND , MOS65XX_AM_ZP , 1 }, // 0x25
{ MOS65XX_INS_ROL , MOS65XX_AM_ZP , 1 }, // 0x26
{ MOS65XX_INS_INVALID, MOS65XX_AM_NONE , 0 }, // 0x27
{ MOS65XX_INS_PLP , MOS65XX_AM_IMP , 0 }, // 0x28
{ MOS65XX_INS_AND , MOS65XX_AM_IMM , 1 }, // 0x29
{ MOS65XX_INS_ROL , MOS65XX_AM_ACC , 0 }, // 0x2a
{ MOS65XX_INS_INVALID, MOS65XX_AM_NONE , 0 }, // 0x2b
{ MOS65XX_INS_BIT , MOS65XX_AM_ABS , 2 }, // 0x2c
{ MOS65XX_INS_AND , MOS65XX_AM_ABS , 2 }, // 0x2d
{ MOS65XX_INS_ROL , MOS65XX_AM_ABS , 2 }, // 0x2e
{ MOS65XX_INS_INVALID, MOS65XX_AM_NONE , 0 }, // 0x2f
{ MOS65XX_INS_BMI , MOS65XX_AM_REL , 1 }, // 0x30
{ MOS65XX_INS_AND , MOS65XX_AM_ZP_IND_Y , 1 }, // 0x31
{ MOS65XX_INS_INVALID, MOS65XX_AM_NONE , 0 }, // 0x32
{ MOS65XX_INS_INVALID, MOS65XX_AM_NONE , 0 }, // 0x33
{ MOS65XX_INS_INVALID, MOS65XX_AM_NONE , 0 }, // 0x34
{ MOS65XX_INS_AND , MOS65XX_AM_ZP_X , 1 }, // 0x35
{ MOS65XX_INS_ROL , MOS65XX_AM_ZP_X , 1 }, // 0x36
{ MOS65XX_INS_INVALID, MOS65XX_AM_NONE , 0 }, // 0x37
{ MOS65XX_INS_SEC , MOS65XX_AM_IMP , 0 }, // 0x38
{ MOS65XX_INS_AND , MOS65XX_AM_ABS_Y , 2 }, // 0x39
{ MOS65XX_INS_INVALID, MOS65XX_AM_NONE , 0 }, // 0x3a
{ MOS65XX_INS_INVALID, MOS65XX_AM_NONE , 0 }, // 0x3b
{ MOS65XX_INS_INVALID, MOS65XX_AM_NONE , 0 }, // 0x3c
{ MOS65XX_INS_AND , MOS65XX_AM_ABS_X , 2 }, // 0x3d
{ MOS65XX_INS_ROL , MOS65XX_AM_ABS_X , 2 }, // 0x3e
{ MOS65XX_INS_INVALID, MOS65XX_AM_NONE , 0 }, // 0x3f
{ MOS65XX_INS_RTI , MOS65XX_AM_IMP , 0 }, // 0x40
{ MOS65XX_INS_EOR , MOS65XX_AM_ZP_X_IND , 1 }, // 0x41
{ MOS65XX_INS_INVALID, MOS65XX_AM_NONE , 0 }, // 0x42
{ MOS65XX_INS_INVALID, MOS65XX_AM_NONE , 0 }, // 0x43
{ MOS65XX_INS_INVALID, MOS65XX_AM_NONE , 0 }, // 0x44
{ MOS65XX_INS_EOR , MOS65XX_AM_ZP , 1 }, // 0x45
{ MOS65XX_INS_LSR , MOS65XX_AM_ZP , 1 }, // 0x46
{ MOS65XX_INS_INVALID, MOS65XX_AM_NONE , 0 }, // 0x47
{ MOS65XX_INS_PHA , MOS65XX_AM_IMP , 0 }, // 0x48
{ MOS65XX_INS_EOR , MOS65XX_AM_IMM , 1 }, // 0x49
{ MOS65XX_INS_LSR , MOS65XX_AM_ACC , 0 }, // 0x4a
{ MOS65XX_INS_INVALID, MOS65XX_AM_NONE , 0 }, // 0x4b
{ MOS65XX_INS_JMP , MOS65XX_AM_ABS , 2 }, // 0x4c
{ MOS65XX_INS_EOR , MOS65XX_AM_ABS , 2 }, // 0x4d
{ MOS65XX_INS_LSR , MOS65XX_AM_ABS , 2 }, // 0x4e
{ MOS65XX_INS_INVALID, MOS65XX_AM_NONE , 0 }, // 0x4f
{ MOS65XX_INS_BVC , MOS65XX_AM_REL , 1 }, // 0x50
{ MOS65XX_INS_EOR , MOS65XX_AM_ZP_IND_Y , 1 }, // 0x51
{ MOS65XX_INS_INVALID, MOS65XX_AM_NONE , 0 }, // 0x52
{ MOS65XX_INS_INVALID, MOS65XX_AM_NONE , 0 }, // 0x53
{ MOS65XX_INS_INVALID, MOS65XX_AM_NONE , 0 }, // 0x54
{ MOS65XX_INS_EOR , MOS65XX_AM_ZP_X , 1 }, // 0x55
{ MOS65XX_INS_LSR , MOS65XX_AM_ZP_X , 1 }, // 0x56
{ MOS65XX_INS_INVALID, MOS65XX_AM_NONE , 0 }, // 0x57
{ MOS65XX_INS_CLI , MOS65XX_AM_IMP , 0 }, // 0x58
{ MOS65XX_INS_EOR , MOS65XX_AM_ABS_Y , 2 }, // 0x59
{ MOS65XX_INS_INVALID, MOS65XX_AM_NONE , 0 }, // 0x5a
{ MOS65XX_INS_INVALID, MOS65XX_AM_NONE , 0 }, // 0x5b
{ MOS65XX_INS_INVALID, MOS65XX_AM_NONE , 0 }, // 0x5c
{ MOS65XX_INS_EOR , MOS65XX_AM_ABS_X , 2 }, // 0x5d
{ MOS65XX_INS_LSR , MOS65XX_AM_ABS_X , 2 }, // 0x5e
{ MOS65XX_INS_INVALID, MOS65XX_AM_NONE , 0 }, // 0x5f
{ MOS65XX_INS_RTS , MOS65XX_AM_IMP , 0 }, // 0x60
{ MOS65XX_INS_ADC , MOS65XX_AM_ZP_X_IND , 1 }, // 0x61
{ MOS65XX_INS_INVALID, MOS65XX_AM_NONE , 0 }, // 0x62
{ MOS65XX_INS_INVALID, MOS65XX_AM_NONE , 0 }, // 0x63
{ MOS65XX_INS_INVALID, MOS65XX_AM_NONE , 0 }, // 0x64
{ MOS65XX_INS_ADC , MOS65XX_AM_ZP , 1 }, // 0x65
{ MOS65XX_INS_ROR , MOS65XX_AM_ZP , 1 }, // 0x66
{ MOS65XX_INS_INVALID, MOS65XX_AM_NONE , 0 }, // 0x67
{ MOS65XX_INS_PLA , MOS65XX_AM_IMP , 0 }, // 0x68
{ MOS65XX_INS_ADC , MOS65XX_AM_IMM , 1 }, // 0x69
{ MOS65XX_INS_ROR , MOS65XX_AM_ACC , 0 }, // 0x6a
{ MOS65XX_INS_INVALID, MOS65XX_AM_NONE , 0 }, // 0x6b
{ MOS65XX_INS_JMP , MOS65XX_AM_ABS_IND , 2 }, // 0x6c
{ MOS65XX_INS_ADC , MOS65XX_AM_ABS , 2 }, // 0x6d
{ MOS65XX_INS_ROR , MOS65XX_AM_ABS , 2 }, // 0x6e
{ MOS65XX_INS_INVALID, MOS65XX_AM_NONE , 0 }, // 0x6f
{ MOS65XX_INS_BVS , MOS65XX_AM_REL , 1 }, // 0x70
{ MOS65XX_INS_ADC , MOS65XX_AM_ZP_IND_Y , 1 }, // 0x71
{ MOS65XX_INS_INVALID, MOS65XX_AM_NONE , 0 }, // 0x72
{ MOS65XX_INS_INVALID, MOS65XX_AM_NONE , 0 }, // 0x73
{ MOS65XX_INS_INVALID, MOS65XX_AM_NONE , 0 }, // 0x74
{ MOS65XX_INS_ADC , MOS65XX_AM_ZP_X , 1 }, // 0x75
{ MOS65XX_INS_ROR , MOS65XX_AM_ZP_X , 1 }, // 0x76
{ MOS65XX_INS_INVALID, MOS65XX_AM_NONE , 0 }, // 0x77
{ MOS65XX_INS_SEI , MOS65XX_AM_IMP , 0 }, // 0x78
{ MOS65XX_INS_ADC , MOS65XX_AM_ABS_Y , 2 }, // 0x79
{ MOS65XX_INS_INVALID, MOS65XX_AM_NONE , 0 }, // 0x7a
{ MOS65XX_INS_INVALID, MOS65XX_AM_NONE , 0 }, // 0x7b
{ MOS65XX_INS_INVALID, MOS65XX_AM_NONE , 0 }, // 0x7c
{ MOS65XX_INS_ADC , MOS65XX_AM_ABS_X , 2 }, // 0x7d
{ MOS65XX_INS_ROR , MOS65XX_AM_ABS_X , 2 }, // 0x7e
{ MOS65XX_INS_INVALID, MOS65XX_AM_NONE , 0 }, // 0x7f
{ MOS65XX_INS_INVALID, MOS65XX_AM_NONE , 0 }, // 0x80
{ MOS65XX_INS_STA , MOS65XX_AM_ZP_X_IND , 1 }, // 0x81
{ MOS65XX_INS_INVALID, MOS65XX_AM_NONE , 0 }, // 0x82
{ MOS65XX_INS_INVALID, MOS65XX_AM_NONE , 0 }, // 0x83
{ MOS65XX_INS_STY , MOS65XX_AM_ZP , 1 }, // 0x84
{ MOS65XX_INS_STA , MOS65XX_AM_ZP , 1 }, // 0x85
{ MOS65XX_INS_STX , MOS65XX_AM_ZP , 1 }, // 0x86
{ MOS65XX_INS_INVALID, MOS65XX_AM_NONE , 0 }, // 0x87
{ MOS65XX_INS_DEY , MOS65XX_AM_IMP , 0 }, // 0x88
{ MOS65XX_INS_INVALID, MOS65XX_AM_NONE , 0 }, // 0x89
{ MOS65XX_INS_TXA , MOS65XX_AM_IMP , 0 }, // 0x8a
{ MOS65XX_INS_INVALID, MOS65XX_AM_NONE , 0 }, // 0x8b
{ MOS65XX_INS_STY , MOS65XX_AM_ABS , 2 }, // 0x8c
{ MOS65XX_INS_STA , MOS65XX_AM_ABS , 2 }, // 0x8d
{ MOS65XX_INS_STX , MOS65XX_AM_ABS , 2 }, // 0x8e
{ MOS65XX_INS_INVALID, MOS65XX_AM_NONE , 0 }, // 0x8f
{ MOS65XX_INS_BCC , MOS65XX_AM_REL , 1 }, // 0x90
{ MOS65XX_INS_STA , MOS65XX_AM_ZP_IND_Y , 1 }, // 0x91
{ MOS65XX_INS_INVALID, MOS65XX_AM_NONE , 0 }, // 0x92
{ MOS65XX_INS_INVALID, MOS65XX_AM_NONE , 0 }, // 0x93
{ MOS65XX_INS_STY , MOS65XX_AM_ZP_X , 1 }, // 0x94
{ MOS65XX_INS_STA , MOS65XX_AM_ZP_X , 1 }, // 0x95
{ MOS65XX_INS_STX , MOS65XX_AM_ZP_Y , 1 }, // 0x96
{ MOS65XX_INS_INVALID, MOS65XX_AM_NONE , 0 }, // 0x97
{ MOS65XX_INS_TYA , MOS65XX_AM_IMP , 0 }, // 0x98
{ MOS65XX_INS_STA , MOS65XX_AM_ABS_Y , 2 }, // 0x99
{ MOS65XX_INS_TXS , MOS65XX_AM_IMP , 0 }, // 0x9a
{ MOS65XX_INS_INVALID, MOS65XX_AM_NONE , 0 }, // 0x9b
{ MOS65XX_INS_INVALID, MOS65XX_AM_NONE , 0 }, // 0x9c
{ MOS65XX_INS_STA , MOS65XX_AM_ABS_X , 2 }, // 0x9d
{ MOS65XX_INS_INVALID, MOS65XX_AM_NONE , 0 }, // 0x9e
{ MOS65XX_INS_INVALID, MOS65XX_AM_NONE , 0 }, // 0x9f
{ MOS65XX_INS_LDY , MOS65XX_AM_IMM , 1 }, // 0xa0
{ MOS65XX_INS_LDA , MOS65XX_AM_ZP_X_IND , 1 }, // 0xa1
{ MOS65XX_INS_LDX , MOS65XX_AM_IMM , 1 }, // 0xa2
{ MOS65XX_INS_INVALID, MOS65XX_AM_NONE , 0 }, // 0xa3
{ MOS65XX_INS_LDY , MOS65XX_AM_ZP , 1 }, // 0xa4
{ MOS65XX_INS_LDA , MOS65XX_AM_ZP , 1 }, // 0xa5
{ MOS65XX_INS_LDX , MOS65XX_AM_ZP , 1 }, // 0xa6
{ MOS65XX_INS_INVALID, MOS65XX_AM_NONE , 0 }, // 0xa7
{ MOS65XX_INS_TAY , MOS65XX_AM_IMP , 0 }, // 0xa8
{ MOS65XX_INS_LDA , MOS65XX_AM_IMM , 1 }, // 0xa9
{ MOS65XX_INS_TAX , MOS65XX_AM_IMP , 0 }, // 0xaa
{ MOS65XX_INS_INVALID, MOS65XX_AM_NONE , 0 }, // 0xab
{ MOS65XX_INS_LDY , MOS65XX_AM_ABS , 2 }, // 0xac
{ MOS65XX_INS_LDA , MOS65XX_AM_ABS , 2 }, // 0xad
{ MOS65XX_INS_LDX , MOS65XX_AM_ABS , 2 }, // 0xae
{ MOS65XX_INS_INVALID, MOS65XX_AM_NONE , 0 }, // 0xaf
{ MOS65XX_INS_BCS , MOS65XX_AM_REL , 1 }, // 0xb0
{ MOS65XX_INS_LDA , MOS65XX_AM_ZP_IND_Y , 1 }, // 0xb1
{ MOS65XX_INS_INVALID, MOS65XX_AM_NONE , 0 }, // 0xb2
{ MOS65XX_INS_INVALID, MOS65XX_AM_NONE , 0 }, // 0xb3
{ MOS65XX_INS_LDY , MOS65XX_AM_ZP_X , 1 }, // 0xb4
{ MOS65XX_INS_LDA , MOS65XX_AM_ZP_X , 1 }, // 0xb5
{ MOS65XX_INS_LDX , MOS65XX_AM_ZP_Y , 1 }, // 0xb6
{ MOS65XX_INS_INVALID, MOS65XX_AM_NONE , 0 }, // 0xb7
{ MOS65XX_INS_CLV , MOS65XX_AM_IMP , 0 }, // 0xb8
{ MOS65XX_INS_LDA , MOS65XX_AM_ABS_Y , 2 }, // 0xb9
{ MOS65XX_INS_TSX , MOS65XX_AM_IMP , 0 }, // 0xba
{ MOS65XX_INS_INVALID, MOS65XX_AM_NONE , 0 }, // 0xbb
{ MOS65XX_INS_LDY , MOS65XX_AM_ABS_X , 2 }, // 0xbc
{ MOS65XX_INS_LDA , MOS65XX_AM_ABS_X , 2 }, // 0xbd
{ MOS65XX_INS_LDX , MOS65XX_AM_ABS_Y , 2 }, // 0xbe
{ MOS65XX_INS_INVALID, MOS65XX_AM_NONE , 0 }, // 0xbf
{ MOS65XX_INS_CPY , MOS65XX_AM_IMM , 1 }, // 0xc0
{ MOS65XX_INS_CMP , MOS65XX_AM_ZP_X_IND , 1 }, // 0xc1
{ MOS65XX_INS_INVALID, MOS65XX_AM_NONE , 0 }, // 0xc2
{ MOS65XX_INS_INVALID, MOS65XX_AM_NONE , 0 }, // 0xc3
{ MOS65XX_INS_CPY , MOS65XX_AM_ZP , 1 }, // 0xc4
{ MOS65XX_INS_CMP , MOS65XX_AM_ZP , 1 }, // 0xc5
{ MOS65XX_INS_DEC , MOS65XX_AM_ZP , 1 }, // 0xc6
{ MOS65XX_INS_INVALID, MOS65XX_AM_NONE , 0 }, // 0xc7
{ MOS65XX_INS_INY , MOS65XX_AM_IMP , 0 }, // 0xc8
{ MOS65XX_INS_CMP , MOS65XX_AM_IMM , 1 }, // 0xc9
{ MOS65XX_INS_DEX , MOS65XX_AM_IMP , 0 }, // 0xca
{ MOS65XX_INS_INVALID, MOS65XX_AM_NONE , 0 }, // 0xcb
{ MOS65XX_INS_CPY , MOS65XX_AM_ABS , 2 }, // 0xcc
{ MOS65XX_INS_CMP , MOS65XX_AM_ABS , 2 }, // 0xcd
{ MOS65XX_INS_DEC , MOS65XX_AM_ABS , 2 }, // 0xce
{ MOS65XX_INS_INVALID, MOS65XX_AM_NONE , 0 }, // 0xcf
{ MOS65XX_INS_BNE , MOS65XX_AM_REL , 1 }, // 0xd0
{ MOS65XX_INS_CMP , MOS65XX_AM_ZP_IND_Y , 1 }, // 0xd1
{ MOS65XX_INS_INVALID, MOS65XX_AM_NONE , 0 }, // 0xd2
{ MOS65XX_INS_INVALID, MOS65XX_AM_NONE , 0 }, // 0xd3
{ MOS65XX_INS_INVALID, MOS65XX_AM_NONE , 0 }, // 0xd4
{ MOS65XX_INS_CMP , MOS65XX_AM_ZP_X , 1 }, // 0xd5
{ MOS65XX_INS_DEC , MOS65XX_AM_ZP_X , 1 }, // 0xd6
{ MOS65XX_INS_INVALID, MOS65XX_AM_NONE , 0 }, // 0xd7
{ MOS65XX_INS_CLD , MOS65XX_AM_IMP , 0 }, // 0xd8
{ MOS65XX_INS_CMP , MOS65XX_AM_ABS_Y , 2 }, // 0xd9
{ MOS65XX_INS_INVALID, MOS65XX_AM_NONE , 0 }, // 0xda
{ MOS65XX_INS_INVALID, MOS65XX_AM_NONE , 0 }, // 0xdb
{ MOS65XX_INS_INVALID, MOS65XX_AM_NONE , 0 }, // 0xdc
{ MOS65XX_INS_CMP , MOS65XX_AM_ABS_X , 2 }, // 0xdd
{ MOS65XX_INS_DEC , MOS65XX_AM_ABS_X , 2 }, // 0xde
{ MOS65XX_INS_INVALID, MOS65XX_AM_NONE , 0 }, // 0xdf
{ MOS65XX_INS_CPX , MOS65XX_AM_IMM , 1 }, // 0xe0
{ MOS65XX_INS_SBC , MOS65XX_AM_ZP_X_IND , 1 }, // 0xe1
{ MOS65XX_INS_INVALID, MOS65XX_AM_NONE , 0 }, // 0xe2
{ MOS65XX_INS_INVALID, MOS65XX_AM_NONE , 0 }, // 0xe3
{ MOS65XX_INS_CPX , MOS65XX_AM_ZP , 1 }, // 0xe4
{ MOS65XX_INS_SBC , MOS65XX_AM_ZP , 1 }, // 0xe5
{ MOS65XX_INS_INC , MOS65XX_AM_ZP , 1 }, // 0xe6
{ MOS65XX_INS_INVALID, MOS65XX_AM_NONE , 0 }, // 0xe7
{ MOS65XX_INS_INX , MOS65XX_AM_IMP , 0 }, // 0xe8
{ MOS65XX_INS_SBC , MOS65XX_AM_IMM , 1 }, // 0xe9
{ MOS65XX_INS_NOP , MOS65XX_AM_IMP , 0 }, // 0xea
{ MOS65XX_INS_INVALID, MOS65XX_AM_NONE , 0 }, // 0xeb
{ MOS65XX_INS_CPX , MOS65XX_AM_ABS , 2 }, // 0xec
{ MOS65XX_INS_SBC , MOS65XX_AM_ABS , 2 }, // 0xed
{ MOS65XX_INS_INC , MOS65XX_AM_ABS , 2 }, // 0xee
{ MOS65XX_INS_INVALID, MOS65XX_AM_NONE , 0 }, // 0xef
{ MOS65XX_INS_BEQ , MOS65XX_AM_REL , 1 }, // 0xf0
{ MOS65XX_INS_SBC , MOS65XX_AM_ZP_IND_Y , 1 }, // 0xf1
{ MOS65XX_INS_INVALID, MOS65XX_AM_NONE , 0 }, // 0xf2
{ MOS65XX_INS_INVALID, MOS65XX_AM_NONE , 0 }, // 0xf3
{ MOS65XX_INS_INVALID, MOS65XX_AM_NONE , 0 }, // 0xf4
{ MOS65XX_INS_SBC , MOS65XX_AM_ZP_X , 1 }, // 0xf5
{ MOS65XX_INS_INC , MOS65XX_AM_ZP_X , 1 }, // 0xf6
{ MOS65XX_INS_INVALID, MOS65XX_AM_NONE , 0 }, // 0xf7
{ MOS65XX_INS_SED , MOS65XX_AM_IMP , 0 }, // 0xf8
{ MOS65XX_INS_SBC , MOS65XX_AM_ABS_Y , 2 }, // 0xf9
{ MOS65XX_INS_INVALID, MOS65XX_AM_NONE , 0 }, // 0xfa
{ MOS65XX_INS_INVALID, MOS65XX_AM_NONE , 0 }, // 0xfb
{ MOS65XX_INS_INVALID, MOS65XX_AM_NONE , 0 }, // 0xfc
{ MOS65XX_INS_SBC , MOS65XX_AM_ABS_X , 2 }, // 0xfd
{ MOS65XX_INS_INC , MOS65XX_AM_ABS_X , 2 }, // 0xfe
{ MOS65XX_INS_INVALID, MOS65XX_AM_NONE , 0 }, // 0xff

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arch/MOS65XX/m65816.inc Normal file
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{ MOS65XX_INS_BRK , MOS65XX_AM_INT , 1 }, // 0x00
{ MOS65XX_INS_ORA , MOS65XX_AM_ZP_X_IND , 1 }, // 0x01
{ MOS65XX_INS_COP , MOS65XX_AM_INT , 1 }, // 0x02
{ MOS65XX_INS_ORA , MOS65XX_AM_SR , 1 }, // 0x03
{ MOS65XX_INS_TSB , MOS65XX_AM_ZP , 1 }, // 0x04
{ MOS65XX_INS_ORA , MOS65XX_AM_ZP , 1 }, // 0x05
{ MOS65XX_INS_ASL , MOS65XX_AM_ZP , 1 }, // 0x06
{ MOS65XX_INS_ORA , MOS65XX_AM_ZP_IND_LONG , 1 }, // 0x07
{ MOS65XX_INS_PHP , MOS65XX_AM_IMP , 0 }, // 0x08
{ MOS65XX_INS_ORA , MOS65XX_AM_IMM , 1 }, // 0x09
{ MOS65XX_INS_ASL , MOS65XX_AM_ACC , 0 }, // 0x0a
{ MOS65XX_INS_PHD , MOS65XX_AM_IMP , 0 }, // 0x0b
{ MOS65XX_INS_TSB , MOS65XX_AM_ABS , 2 }, // 0x0c
{ MOS65XX_INS_ORA , MOS65XX_AM_ABS , 2 }, // 0x0d
{ MOS65XX_INS_ASL , MOS65XX_AM_ABS , 2 }, // 0x0e
{ MOS65XX_INS_ORA , MOS65XX_AM_ABS_LONG , 3 }, // 0x0f
{ MOS65XX_INS_BPL , MOS65XX_AM_REL , 1 }, // 0x10
{ MOS65XX_INS_ORA , MOS65XX_AM_ZP_IND_Y , 1 }, // 0x11
{ MOS65XX_INS_ORA , MOS65XX_AM_ZP_IND , 1 }, // 0x12
{ MOS65XX_INS_ORA , MOS65XX_AM_SR_IND_Y , 1 }, // 0x13
{ MOS65XX_INS_TRB , MOS65XX_AM_ZP , 1 }, // 0x14
{ MOS65XX_INS_ORA , MOS65XX_AM_ZP_X , 1 }, // 0x15
{ MOS65XX_INS_ASL , MOS65XX_AM_ZP_X , 1 }, // 0x16
{ MOS65XX_INS_ORA , MOS65XX_AM_ZP_IND_LONG_Y, 1 }, // 0x17
{ MOS65XX_INS_CLC , MOS65XX_AM_IMP , 0 }, // 0x18
{ MOS65XX_INS_ORA , MOS65XX_AM_ABS_Y , 2 }, // 0x19
{ MOS65XX_INS_INC , MOS65XX_AM_ACC , 0 }, // 0x1a
{ MOS65XX_INS_TCS , MOS65XX_AM_IMP , 0 }, // 0x1b
{ MOS65XX_INS_TRB , MOS65XX_AM_ABS , 2 }, // 0x1c
{ MOS65XX_INS_ORA , MOS65XX_AM_ABS_X , 2 }, // 0x1d
{ MOS65XX_INS_ASL , MOS65XX_AM_ABS_X , 2 }, // 0x1e
{ MOS65XX_INS_ORA , MOS65XX_AM_ABS_LONG_X , 3 }, // 0x1f
{ MOS65XX_INS_JSR , MOS65XX_AM_ABS , 2 }, // 0x20
{ MOS65XX_INS_AND , MOS65XX_AM_ZP_X_IND , 1 }, // 0x21
{ MOS65XX_INS_JSL , MOS65XX_AM_ABS_LONG , 3 }, // 0x22
{ MOS65XX_INS_AND , MOS65XX_AM_SR , 1 }, // 0x23
{ MOS65XX_INS_BIT , MOS65XX_AM_ZP , 1 }, // 0x24
{ MOS65XX_INS_AND , MOS65XX_AM_ZP , 1 }, // 0x25
{ MOS65XX_INS_ROL , MOS65XX_AM_ZP , 1 }, // 0x26
{ MOS65XX_INS_AND , MOS65XX_AM_ZP_IND_LONG , 1 }, // 0x27
{ MOS65XX_INS_PLP , MOS65XX_AM_IMP , 0 }, // 0x28
{ MOS65XX_INS_AND , MOS65XX_AM_IMM , 1 }, // 0x29
{ MOS65XX_INS_ROL , MOS65XX_AM_ACC , 0 }, // 0x2a
{ MOS65XX_INS_PLD , MOS65XX_AM_IMP , 0 }, // 0x2b
{ MOS65XX_INS_BIT , MOS65XX_AM_ABS , 2 }, // 0x2c
{ MOS65XX_INS_AND , MOS65XX_AM_ABS , 2 }, // 0x2d
{ MOS65XX_INS_ROL , MOS65XX_AM_ABS , 2 }, // 0x2e
{ MOS65XX_INS_AND , MOS65XX_AM_ABS_LONG , 3 }, // 0x2f
{ MOS65XX_INS_BMI , MOS65XX_AM_REL , 1 }, // 0x30
{ MOS65XX_INS_AND , MOS65XX_AM_ZP_IND_Y , 1 }, // 0x31
{ MOS65XX_INS_AND , MOS65XX_AM_ZP_IND , 1 }, // 0x32
{ MOS65XX_INS_AND , MOS65XX_AM_SR_IND_Y , 1 }, // 0x33
{ MOS65XX_INS_BIT , MOS65XX_AM_ZP_X , 1 }, // 0x34
{ MOS65XX_INS_AND , MOS65XX_AM_ZP_X , 1 }, // 0x35
{ MOS65XX_INS_ROL , MOS65XX_AM_ZP_X , 1 }, // 0x36
{ MOS65XX_INS_AND , MOS65XX_AM_ZP_IND_LONG_Y, 1 }, // 0x37
{ MOS65XX_INS_SEC , MOS65XX_AM_IMP , 0 }, // 0x38
{ MOS65XX_INS_AND , MOS65XX_AM_ABS_Y , 2 }, // 0x39
{ MOS65XX_INS_DEC , MOS65XX_AM_ACC , 0 }, // 0x3a
{ MOS65XX_INS_TSC , MOS65XX_AM_IMP , 0 }, // 0x3b
{ MOS65XX_INS_BIT , MOS65XX_AM_ABS_X , 2 }, // 0x3c
{ MOS65XX_INS_AND , MOS65XX_AM_ABS_X , 2 }, // 0x3d
{ MOS65XX_INS_ROL , MOS65XX_AM_ABS_X , 2 }, // 0x3e
{ MOS65XX_INS_AND , MOS65XX_AM_ABS_LONG_X , 3 }, // 0x3f
{ MOS65XX_INS_RTI , MOS65XX_AM_IMP , 0 }, // 0x40
{ MOS65XX_INS_EOR , MOS65XX_AM_ZP_X_IND , 1 }, // 0x41
{ MOS65XX_INS_WDM , MOS65XX_AM_INT , 1 }, // 0x42
{ MOS65XX_INS_EOR , MOS65XX_AM_SR , 1 }, // 0x43
{ MOS65XX_INS_MVP , MOS65XX_AM_BLOCK , 2 }, // 0x44
{ MOS65XX_INS_EOR , MOS65XX_AM_ZP , 1 }, // 0x45
{ MOS65XX_INS_LSR , MOS65XX_AM_ZP , 1 }, // 0x46
{ MOS65XX_INS_EOR , MOS65XX_AM_ZP_IND_LONG , 1 }, // 0x47
{ MOS65XX_INS_PHA , MOS65XX_AM_IMP , 0 }, // 0x48
{ MOS65XX_INS_EOR , MOS65XX_AM_IMM , 1 }, // 0x49
{ MOS65XX_INS_LSR , MOS65XX_AM_ACC , 0 }, // 0x4a
{ MOS65XX_INS_PHK , MOS65XX_AM_IMP , 0 }, // 0x4b
{ MOS65XX_INS_JMP , MOS65XX_AM_ABS , 2 }, // 0x4c
{ MOS65XX_INS_EOR , MOS65XX_AM_ABS , 2 }, // 0x4d
{ MOS65XX_INS_LSR , MOS65XX_AM_ABS , 2 }, // 0x4e
{ MOS65XX_INS_EOR , MOS65XX_AM_ABS_LONG , 3 }, // 0x4f
{ MOS65XX_INS_BVC , MOS65XX_AM_REL , 1 }, // 0x50
{ MOS65XX_INS_EOR , MOS65XX_AM_ZP_IND_Y , 1 }, // 0x51
{ MOS65XX_INS_EOR , MOS65XX_AM_ZP_IND , 1 }, // 0x52
{ MOS65XX_INS_EOR , MOS65XX_AM_SR_IND_Y , 1 }, // 0x53
{ MOS65XX_INS_MVN , MOS65XX_AM_BLOCK , 2 }, // 0x54
{ MOS65XX_INS_EOR , MOS65XX_AM_ZP_X , 1 }, // 0x55
{ MOS65XX_INS_LSR , MOS65XX_AM_ZP_X , 1 }, // 0x56
{ MOS65XX_INS_EOR , MOS65XX_AM_ZP_IND_LONG_Y, 1 }, // 0x57
{ MOS65XX_INS_CLI , MOS65XX_AM_IMP , 0 }, // 0x58
{ MOS65XX_INS_EOR , MOS65XX_AM_ABS_Y , 2 }, // 0x59
{ MOS65XX_INS_PHY , MOS65XX_AM_IMP , 0 }, // 0x5a
{ MOS65XX_INS_TCD , MOS65XX_AM_IMP , 0 }, // 0x5b
{ MOS65XX_INS_JML , MOS65XX_AM_ABS_LONG , 3 }, // 0x5c
{ MOS65XX_INS_EOR , MOS65XX_AM_ABS_X , 2 }, // 0x5d
{ MOS65XX_INS_LSR , MOS65XX_AM_ABS_X , 2 }, // 0x5e
{ MOS65XX_INS_EOR , MOS65XX_AM_ABS_LONG_X , 3 }, // 0x5f
{ MOS65XX_INS_RTS , MOS65XX_AM_IMP , 0 }, // 0x60
{ MOS65XX_INS_ADC , MOS65XX_AM_ZP_X_IND , 1 }, // 0x61
{ MOS65XX_INS_PER , MOS65XX_AM_REL , 2 }, // 0x62
{ MOS65XX_INS_ADC , MOS65XX_AM_SR , 1 }, // 0x63
{ MOS65XX_INS_STZ , MOS65XX_AM_ZP , 1 }, // 0x64
{ MOS65XX_INS_ADC , MOS65XX_AM_ZP , 1 }, // 0x65
{ MOS65XX_INS_ROR , MOS65XX_AM_ZP , 1 }, // 0x66
{ MOS65XX_INS_ADC , MOS65XX_AM_ZP_IND_LONG , 1 }, // 0x67
{ MOS65XX_INS_PLA , MOS65XX_AM_IMP , 0 }, // 0x68
{ MOS65XX_INS_ADC , MOS65XX_AM_IMM , 1 }, // 0x69
{ MOS65XX_INS_ROR , MOS65XX_AM_ACC , 0 }, // 0x6a
{ MOS65XX_INS_RTL , MOS65XX_AM_IMP , 0 }, // 0x6b
{ MOS65XX_INS_JMP , MOS65XX_AM_ABS_IND , 2 }, // 0x6c
{ MOS65XX_INS_ADC , MOS65XX_AM_ABS , 2 }, // 0x6d
{ MOS65XX_INS_ROR , MOS65XX_AM_ABS , 2 }, // 0x6e
{ MOS65XX_INS_ADC , MOS65XX_AM_ABS_LONG , 3 }, // 0x6f
{ MOS65XX_INS_BVS , MOS65XX_AM_REL , 1 }, // 0x70
{ MOS65XX_INS_ADC , MOS65XX_AM_ZP_IND_Y , 1 }, // 0x71
{ MOS65XX_INS_ADC , MOS65XX_AM_ZP_IND , 1 }, // 0x72
{ MOS65XX_INS_ADC , MOS65XX_AM_SR_IND_Y , 1 }, // 0x73
{ MOS65XX_INS_STZ , MOS65XX_AM_ZP_X , 1 }, // 0x74
{ MOS65XX_INS_ADC , MOS65XX_AM_ZP_X , 1 }, // 0x75
{ MOS65XX_INS_ROR , MOS65XX_AM_ZP_X , 1 }, // 0x76
{ MOS65XX_INS_ADC , MOS65XX_AM_ZP_IND_LONG_Y, 1 }, // 0x77
{ MOS65XX_INS_SEI , MOS65XX_AM_IMP , 0 }, // 0x78
{ MOS65XX_INS_ADC , MOS65XX_AM_ABS_Y , 2 }, // 0x79
{ MOS65XX_INS_PLY , MOS65XX_AM_IMP , 0 }, // 0x7a
{ MOS65XX_INS_TDC , MOS65XX_AM_IMP , 0 }, // 0x7b
{ MOS65XX_INS_JMP , MOS65XX_AM_ABS_X_IND , 2 }, // 0x7c
{ MOS65XX_INS_ADC , MOS65XX_AM_ABS_X , 2 }, // 0x7d
{ MOS65XX_INS_ROR , MOS65XX_AM_ABS_X , 2 }, // 0x7e
{ MOS65XX_INS_ADC , MOS65XX_AM_ABS_LONG_X , 3 }, // 0x7f
{ MOS65XX_INS_BRA , MOS65XX_AM_REL , 1 }, // 0x80
{ MOS65XX_INS_STA , MOS65XX_AM_ZP_X_IND , 1 }, // 0x81
{ MOS65XX_INS_BRL , MOS65XX_AM_REL , 2 }, // 0x82
{ MOS65XX_INS_STA , MOS65XX_AM_SR , 1 }, // 0x83
{ MOS65XX_INS_STY , MOS65XX_AM_ZP , 1 }, // 0x84
{ MOS65XX_INS_STA , MOS65XX_AM_ZP , 1 }, // 0x85
{ MOS65XX_INS_STX , MOS65XX_AM_ZP , 1 }, // 0x86
{ MOS65XX_INS_STA , MOS65XX_AM_ZP_IND_LONG , 1 }, // 0x87
{ MOS65XX_INS_DEY , MOS65XX_AM_IMP , 0 }, // 0x88
{ MOS65XX_INS_BIT , MOS65XX_AM_IMM , 1 }, // 0x89
{ MOS65XX_INS_TXA , MOS65XX_AM_IMP , 0 }, // 0x8a
{ MOS65XX_INS_PHB , MOS65XX_AM_IMP , 0 }, // 0x8b
{ MOS65XX_INS_STY , MOS65XX_AM_ABS , 2 }, // 0x8c
{ MOS65XX_INS_STA , MOS65XX_AM_ABS , 2 }, // 0x8d
{ MOS65XX_INS_STX , MOS65XX_AM_ABS , 2 }, // 0x8e
{ MOS65XX_INS_STA , MOS65XX_AM_ABS_LONG , 3 }, // 0x8f
{ MOS65XX_INS_BCC , MOS65XX_AM_REL , 1 }, // 0x90
{ MOS65XX_INS_STA , MOS65XX_AM_ZP_IND_Y , 1 }, // 0x91
{ MOS65XX_INS_STA , MOS65XX_AM_ZP_IND , 1 }, // 0x92
{ MOS65XX_INS_STA , MOS65XX_AM_SR_IND_Y , 1 }, // 0x93
{ MOS65XX_INS_STY , MOS65XX_AM_ZP_X , 1 }, // 0x94
{ MOS65XX_INS_STA , MOS65XX_AM_ZP_X , 1 }, // 0x95
{ MOS65XX_INS_STX , MOS65XX_AM_ZP_Y , 1 }, // 0x96
{ MOS65XX_INS_STA , MOS65XX_AM_ZP_IND_LONG_Y, 1 }, // 0x97
{ MOS65XX_INS_TYA , MOS65XX_AM_IMP , 0 }, // 0x98
{ MOS65XX_INS_STA , MOS65XX_AM_ABS_Y , 2 }, // 0x99
{ MOS65XX_INS_TXS , MOS65XX_AM_IMP , 0 }, // 0x9a
{ MOS65XX_INS_TXY , MOS65XX_AM_IMP , 0 }, // 0x9b
{ MOS65XX_INS_STZ , MOS65XX_AM_ABS , 2 }, // 0x9c
{ MOS65XX_INS_STA , MOS65XX_AM_ABS_X , 2 }, // 0x9d
{ MOS65XX_INS_STZ , MOS65XX_AM_ABS_X , 2 }, // 0x9e
{ MOS65XX_INS_STA , MOS65XX_AM_ABS_LONG_X , 3 }, // 0x9f
{ MOS65XX_INS_LDY , MOS65XX_AM_IMM , 1 }, // 0xa0
{ MOS65XX_INS_LDA , MOS65XX_AM_ZP_X_IND , 1 }, // 0xa1
{ MOS65XX_INS_LDX , MOS65XX_AM_IMM , 1 }, // 0xa2
{ MOS65XX_INS_LDA , MOS65XX_AM_SR , 1 }, // 0xa3
{ MOS65XX_INS_LDY , MOS65XX_AM_ZP , 1 }, // 0xa4
{ MOS65XX_INS_LDA , MOS65XX_AM_ZP , 1 }, // 0xa5
{ MOS65XX_INS_LDX , MOS65XX_AM_ZP , 1 }, // 0xa6
{ MOS65XX_INS_LDA , MOS65XX_AM_ZP_IND_LONG , 1 }, // 0xa7
{ MOS65XX_INS_TAY , MOS65XX_AM_IMP , 0 }, // 0xa8
{ MOS65XX_INS_LDA , MOS65XX_AM_IMM , 1 }, // 0xa9
{ MOS65XX_INS_TAX , MOS65XX_AM_IMP , 0 }, // 0xaa
{ MOS65XX_INS_PLB , MOS65XX_AM_IMP , 0 }, // 0xab
{ MOS65XX_INS_LDY , MOS65XX_AM_ABS , 2 }, // 0xac
{ MOS65XX_INS_LDA , MOS65XX_AM_ABS , 2 }, // 0xad
{ MOS65XX_INS_LDX , MOS65XX_AM_ABS , 2 }, // 0xae
{ MOS65XX_INS_LDA , MOS65XX_AM_ABS_LONG , 3 }, // 0xaf
{ MOS65XX_INS_BCS , MOS65XX_AM_REL , 1 }, // 0xb0
{ MOS65XX_INS_LDA , MOS65XX_AM_ZP_IND_Y , 1 }, // 0xb1
{ MOS65XX_INS_LDA , MOS65XX_AM_ZP_IND , 1 }, // 0xb2
{ MOS65XX_INS_LDA , MOS65XX_AM_SR_IND_Y , 1 }, // 0xb3
{ MOS65XX_INS_LDY , MOS65XX_AM_ZP_X , 1 }, // 0xb4
{ MOS65XX_INS_LDA , MOS65XX_AM_ZP_X , 1 }, // 0xb5
{ MOS65XX_INS_LDX , MOS65XX_AM_ZP_Y , 1 }, // 0xb6
{ MOS65XX_INS_LDA , MOS65XX_AM_ZP_IND_LONG_Y, 1 }, // 0xb7
{ MOS65XX_INS_CLV , MOS65XX_AM_IMP , 0 }, // 0xb8
{ MOS65XX_INS_LDA , MOS65XX_AM_ABS_Y , 2 }, // 0xb9
{ MOS65XX_INS_TSX , MOS65XX_AM_IMP , 0 }, // 0xba
{ MOS65XX_INS_TYX , MOS65XX_AM_IMP , 0 }, // 0xbb
{ MOS65XX_INS_LDY , MOS65XX_AM_ABS_X , 2 }, // 0xbc
{ MOS65XX_INS_LDA , MOS65XX_AM_ABS_X , 2 }, // 0xbd
{ MOS65XX_INS_LDX , MOS65XX_AM_ABS_Y , 2 }, // 0xbe
{ MOS65XX_INS_LDA , MOS65XX_AM_ABS_LONG_X , 3 }, // 0xbf
{ MOS65XX_INS_CPY , MOS65XX_AM_IMM , 1 }, // 0xc0
{ MOS65XX_INS_CMP , MOS65XX_AM_ZP_X_IND , 1 }, // 0xc1
{ MOS65XX_INS_REP , MOS65XX_AM_IMM , 1 }, // 0xc2
{ MOS65XX_INS_CMP , MOS65XX_AM_SR , 1 }, // 0xc3
{ MOS65XX_INS_CPY , MOS65XX_AM_ZP , 1 }, // 0xc4
{ MOS65XX_INS_CMP , MOS65XX_AM_ZP , 1 }, // 0xc5
{ MOS65XX_INS_DEC , MOS65XX_AM_ZP , 1 }, // 0xc6
{ MOS65XX_INS_CMP , MOS65XX_AM_ZP_IND_LONG , 1 }, // 0xc7
{ MOS65XX_INS_INY , MOS65XX_AM_IMP , 0 }, // 0xc8
{ MOS65XX_INS_CMP , MOS65XX_AM_IMM , 1 }, // 0xc9
{ MOS65XX_INS_DEX , MOS65XX_AM_IMP , 0 }, // 0xca
{ MOS65XX_INS_WAI , MOS65XX_AM_IMP , 0 }, // 0xcb
{ MOS65XX_INS_CPY , MOS65XX_AM_ABS , 2 }, // 0xcc
{ MOS65XX_INS_CMP , MOS65XX_AM_ABS , 2 }, // 0xcd
{ MOS65XX_INS_DEC , MOS65XX_AM_ABS , 2 }, // 0xce
{ MOS65XX_INS_CMP , MOS65XX_AM_ABS_LONG , 3 }, // 0xcf
{ MOS65XX_INS_BNE , MOS65XX_AM_REL , 1 }, // 0xd0
{ MOS65XX_INS_CMP , MOS65XX_AM_ZP_IND_Y , 1 }, // 0xd1
{ MOS65XX_INS_CMP , MOS65XX_AM_ZP_IND , 1 }, // 0xd2
{ MOS65XX_INS_CMP , MOS65XX_AM_SR_IND_Y , 1 }, // 0xd3
{ MOS65XX_INS_PEI , MOS65XX_AM_ZP_IND , 1 }, // 0xd4
{ MOS65XX_INS_CMP , MOS65XX_AM_ZP_X , 1 }, // 0xd5
{ MOS65XX_INS_DEC , MOS65XX_AM_ZP_X , 1 }, // 0xd6
{ MOS65XX_INS_CMP , MOS65XX_AM_ZP_IND_LONG_Y, 1 }, // 0xd7
{ MOS65XX_INS_CLD , MOS65XX_AM_IMP , 0 }, // 0xd8
{ MOS65XX_INS_CMP , MOS65XX_AM_ABS_Y , 2 }, // 0xd9
{ MOS65XX_INS_PHX , MOS65XX_AM_IMP , 0 }, // 0xda
{ MOS65XX_INS_STP , MOS65XX_AM_IMP , 0 }, // 0xdb
{ MOS65XX_INS_JML , MOS65XX_AM_ABS_IND_LONG , 2 }, // 0xdc
{ MOS65XX_INS_CMP , MOS65XX_AM_ABS_X , 2 }, // 0xdd
{ MOS65XX_INS_DEC , MOS65XX_AM_ABS_X , 2 }, // 0xde
{ MOS65XX_INS_CMP , MOS65XX_AM_ABS_LONG_X , 3 }, // 0xdf
{ MOS65XX_INS_CPX , MOS65XX_AM_IMM , 1 }, // 0xe0
{ MOS65XX_INS_SBC , MOS65XX_AM_ZP_X_IND , 1 }, // 0xe1
{ MOS65XX_INS_SEP , MOS65XX_AM_IMM , 1 }, // 0xe2
{ MOS65XX_INS_SBC , MOS65XX_AM_SR , 1 }, // 0xe3
{ MOS65XX_INS_CPX , MOS65XX_AM_ZP , 1 }, // 0xe4
{ MOS65XX_INS_SBC , MOS65XX_AM_ZP , 1 }, // 0xe5
{ MOS65XX_INS_INC , MOS65XX_AM_ZP , 1 }, // 0xe6
{ MOS65XX_INS_SBC , MOS65XX_AM_ZP_IND_LONG , 1 }, // 0xe7
{ MOS65XX_INS_INX , MOS65XX_AM_IMP , 0 }, // 0xe8
{ MOS65XX_INS_SBC , MOS65XX_AM_IMM , 1 }, // 0xe9
{ MOS65XX_INS_NOP , MOS65XX_AM_IMP , 0 }, // 0xea
{ MOS65XX_INS_XBA , MOS65XX_AM_IMP , 0 }, // 0xeb
{ MOS65XX_INS_CPX , MOS65XX_AM_ABS , 2 }, // 0xec
{ MOS65XX_INS_SBC , MOS65XX_AM_ABS , 2 }, // 0xed
{ MOS65XX_INS_INC , MOS65XX_AM_ABS , 2 }, // 0xee
{ MOS65XX_INS_SBC , MOS65XX_AM_ABS_LONG , 3 }, // 0xef
{ MOS65XX_INS_BEQ , MOS65XX_AM_REL , 1 }, // 0xf0
{ MOS65XX_INS_SBC , MOS65XX_AM_ZP_IND_Y , 1 }, // 0xf1
{ MOS65XX_INS_SBC , MOS65XX_AM_ZP_IND , 1 }, // 0xf2
{ MOS65XX_INS_SBC , MOS65XX_AM_SR_IND_Y , 1 }, // 0xf3
{ MOS65XX_INS_PEA , MOS65XX_AM_ABS , 2 }, // 0xf4
{ MOS65XX_INS_SBC , MOS65XX_AM_ZP_X , 1 }, // 0xf5
{ MOS65XX_INS_INC , MOS65XX_AM_ZP_X , 1 }, // 0xf6
{ MOS65XX_INS_SBC , MOS65XX_AM_ZP_IND_LONG_Y, 1 }, // 0xf7
{ MOS65XX_INS_SED , MOS65XX_AM_IMP , 0 }, // 0xf8
{ MOS65XX_INS_SBC , MOS65XX_AM_ABS_Y , 2 }, // 0xf9
{ MOS65XX_INS_PLX , MOS65XX_AM_IMP , 0 }, // 0xfa
{ MOS65XX_INS_XCE , MOS65XX_AM_IMP , 0 }, // 0xfb
{ MOS65XX_INS_JSR , MOS65XX_AM_ABS_X_IND , 2 }, // 0xfc
{ MOS65XX_INS_SBC , MOS65XX_AM_ABS_X , 2 }, // 0xfd
{ MOS65XX_INS_INC , MOS65XX_AM_ABS_X , 2 }, // 0xfe
{ MOS65XX_INS_SBC , MOS65XX_AM_ABS_LONG_X , 3 }, // 0xff

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{ MOS65XX_INS_BRK , MOS65XX_AM_INT , 1 }, // 0x00
{ MOS65XX_INS_ORA , MOS65XX_AM_ZP_X_IND , 1 }, // 0x01
{ MOS65XX_INS_NOP , MOS65XX_AM_IMP , 1 }, // 0x02
{ MOS65XX_INS_NOP , MOS65XX_AM_IMP , 0 }, // 0x03
{ MOS65XX_INS_TSB , MOS65XX_AM_ZP , 1 }, // 0x04
{ MOS65XX_INS_ORA , MOS65XX_AM_ZP , 1 }, // 0x05
{ MOS65XX_INS_ASL , MOS65XX_AM_ZP , 1 }, // 0x06
{ MOS65XX_INS_NOP , MOS65XX_AM_IMP , 0 }, // 0x07
{ MOS65XX_INS_PHP , MOS65XX_AM_IMP , 0 }, // 0x08
{ MOS65XX_INS_ORA , MOS65XX_AM_IMM , 1 }, // 0x09
{ MOS65XX_INS_ASL , MOS65XX_AM_ACC , 0 }, // 0x0a
{ MOS65XX_INS_NOP , MOS65XX_AM_IMP , 0 }, // 0x0b
{ MOS65XX_INS_TSB , MOS65XX_AM_ABS , 2 }, // 0x0c
{ MOS65XX_INS_ORA , MOS65XX_AM_ABS , 2 }, // 0x0d
{ MOS65XX_INS_ASL , MOS65XX_AM_ABS , 2 }, // 0x0e
{ MOS65XX_INS_NOP , MOS65XX_AM_IMP , 0 }, // 0x0f
{ MOS65XX_INS_BPL , MOS65XX_AM_REL , 1 }, // 0x10
{ MOS65XX_INS_ORA , MOS65XX_AM_ZP_IND_Y , 1 }, // 0x11
{ MOS65XX_INS_ORA , MOS65XX_AM_ZP_IND , 1 }, // 0x12
{ MOS65XX_INS_NOP , MOS65XX_AM_IMP , 0 }, // 0x13
{ MOS65XX_INS_TRB , MOS65XX_AM_ZP , 1 }, // 0x14
{ MOS65XX_INS_ORA , MOS65XX_AM_ZP_X , 1 }, // 0x15
{ MOS65XX_INS_ASL , MOS65XX_AM_ZP_X , 1 }, // 0x16
{ MOS65XX_INS_NOP , MOS65XX_AM_IMP , 0 }, // 0x17
{ MOS65XX_INS_CLC , MOS65XX_AM_IMP , 0 }, // 0x18
{ MOS65XX_INS_ORA , MOS65XX_AM_ABS_Y , 2 }, // 0x19
{ MOS65XX_INS_INC , MOS65XX_AM_ACC , 0 }, // 0x1a
{ MOS65XX_INS_NOP , MOS65XX_AM_IMP , 0 }, // 0x1b
{ MOS65XX_INS_TRB , MOS65XX_AM_ABS , 2 }, // 0x1c
{ MOS65XX_INS_ORA , MOS65XX_AM_ABS_X , 2 }, // 0x1d
{ MOS65XX_INS_ASL , MOS65XX_AM_ABS_X , 2 }, // 0x1e
{ MOS65XX_INS_NOP , MOS65XX_AM_IMP , 0 }, // 0x1f
{ MOS65XX_INS_JSR , MOS65XX_AM_ABS , 2 }, // 0x20
{ MOS65XX_INS_AND , MOS65XX_AM_ZP_X_IND , 1 }, // 0x21
{ MOS65XX_INS_NOP , MOS65XX_AM_IMP , 1 }, // 0x22
{ MOS65XX_INS_NOP , MOS65XX_AM_IMP , 0 }, // 0x23
{ MOS65XX_INS_BIT , MOS65XX_AM_ZP , 1 }, // 0x24
{ MOS65XX_INS_AND , MOS65XX_AM_ZP , 1 }, // 0x25
{ MOS65XX_INS_ROL , MOS65XX_AM_ZP , 1 }, // 0x26
{ MOS65XX_INS_NOP , MOS65XX_AM_IMP , 0 }, // 0x27
{ MOS65XX_INS_PLP , MOS65XX_AM_IMP , 0 }, // 0x28
{ MOS65XX_INS_AND , MOS65XX_AM_IMM , 1 }, // 0x29
{ MOS65XX_INS_ROL , MOS65XX_AM_ACC , 0 }, // 0x2a
{ MOS65XX_INS_NOP , MOS65XX_AM_IMP , 0 }, // 0x2b
{ MOS65XX_INS_BIT , MOS65XX_AM_ABS , 2 }, // 0x2c
{ MOS65XX_INS_AND , MOS65XX_AM_ABS , 2 }, // 0x2d
{ MOS65XX_INS_ROL , MOS65XX_AM_ABS , 2 }, // 0x2e
{ MOS65XX_INS_NOP , MOS65XX_AM_IMP , 0 }, // 0x2f
{ MOS65XX_INS_BMI , MOS65XX_AM_REL , 1 }, // 0x30
{ MOS65XX_INS_AND , MOS65XX_AM_ZP_IND_Y , 1 }, // 0x31
{ MOS65XX_INS_AND , MOS65XX_AM_ZP_IND , 1 }, // 0x32
{ MOS65XX_INS_NOP , MOS65XX_AM_IMP , 0 }, // 0x33
{ MOS65XX_INS_BIT , MOS65XX_AM_ZP_X , 1 }, // 0x34
{ MOS65XX_INS_AND , MOS65XX_AM_ZP_X , 1 }, // 0x35
{ MOS65XX_INS_ROL , MOS65XX_AM_ZP_X , 1 }, // 0x36
{ MOS65XX_INS_NOP , MOS65XX_AM_IMP , 0 }, // 0x37
{ MOS65XX_INS_SEC , MOS65XX_AM_IMP , 0 }, // 0x38
{ MOS65XX_INS_AND , MOS65XX_AM_ABS_Y , 2 }, // 0x39
{ MOS65XX_INS_DEC , MOS65XX_AM_ACC , 0 }, // 0x3a
{ MOS65XX_INS_NOP , MOS65XX_AM_IMP , 0 }, // 0x3b
{ MOS65XX_INS_BIT , MOS65XX_AM_ABS_X , 2 }, // 0x3c
{ MOS65XX_INS_AND , MOS65XX_AM_ABS_X , 2 }, // 0x3d
{ MOS65XX_INS_ROL , MOS65XX_AM_ABS_X , 2 }, // 0x3e
{ MOS65XX_INS_NOP , MOS65XX_AM_IMP , 0 }, // 0x3f
{ MOS65XX_INS_RTI , MOS65XX_AM_IMP , 0 }, // 0x40
{ MOS65XX_INS_EOR , MOS65XX_AM_ZP_X_IND , 1 }, // 0x41
{ MOS65XX_INS_NOP , MOS65XX_AM_IMP , 1 }, // 0x42
{ MOS65XX_INS_NOP , MOS65XX_AM_IMP , 0 }, // 0x43
{ MOS65XX_INS_NOP , MOS65XX_AM_IMP , 1 }, // 0x44
{ MOS65XX_INS_EOR , MOS65XX_AM_ZP , 1 }, // 0x45
{ MOS65XX_INS_LSR , MOS65XX_AM_ZP , 1 }, // 0x46
{ MOS65XX_INS_NOP , MOS65XX_AM_IMP , 0 }, // 0x47
{ MOS65XX_INS_PHA , MOS65XX_AM_IMP , 0 }, // 0x48
{ MOS65XX_INS_EOR , MOS65XX_AM_IMM , 1 }, // 0x49
{ MOS65XX_INS_LSR , MOS65XX_AM_ACC , 0 }, // 0x4a
{ MOS65XX_INS_NOP , MOS65XX_AM_IMP , 0 }, // 0x4b
{ MOS65XX_INS_JMP , MOS65XX_AM_ABS , 2 }, // 0x4c
{ MOS65XX_INS_EOR , MOS65XX_AM_ABS , 2 }, // 0x4d
{ MOS65XX_INS_LSR , MOS65XX_AM_ABS , 2 }, // 0x4e
{ MOS65XX_INS_NOP , MOS65XX_AM_IMP , 0 }, // 0x4f
{ MOS65XX_INS_BVC , MOS65XX_AM_REL , 1 }, // 0x50
{ MOS65XX_INS_EOR , MOS65XX_AM_ZP_IND_Y , 1 }, // 0x51
{ MOS65XX_INS_EOR , MOS65XX_AM_ZP_IND , 1 }, // 0x52
{ MOS65XX_INS_NOP , MOS65XX_AM_IMP , 0 }, // 0x53
{ MOS65XX_INS_NOP , MOS65XX_AM_IMP , 1 }, // 0x54
{ MOS65XX_INS_EOR , MOS65XX_AM_ZP_X , 1 }, // 0x55
{ MOS65XX_INS_LSR , MOS65XX_AM_ZP_X , 1 }, // 0x56
{ MOS65XX_INS_NOP , MOS65XX_AM_IMP , 0 }, // 0x57
{ MOS65XX_INS_CLI , MOS65XX_AM_IMP , 0 }, // 0x58
{ MOS65XX_INS_EOR , MOS65XX_AM_ABS_Y , 2 }, // 0x59
{ MOS65XX_INS_PHY , MOS65XX_AM_IMP , 0 }, // 0x5a
{ MOS65XX_INS_NOP , MOS65XX_AM_IMP , 0 }, // 0x5b
{ MOS65XX_INS_NOP , MOS65XX_AM_IMP , 2 }, // 0x5c
{ MOS65XX_INS_EOR , MOS65XX_AM_ABS_X , 2 }, // 0x5d
{ MOS65XX_INS_LSR , MOS65XX_AM_ABS_X , 2 }, // 0x5e
{ MOS65XX_INS_NOP , MOS65XX_AM_IMP , 0 }, // 0x5f
{ MOS65XX_INS_RTS , MOS65XX_AM_IMP , 0 }, // 0x60
{ MOS65XX_INS_ADC , MOS65XX_AM_ZP_X_IND , 1 }, // 0x61
{ MOS65XX_INS_NOP , MOS65XX_AM_IMP , 1 }, // 0x62
{ MOS65XX_INS_NOP , MOS65XX_AM_IMP , 0 }, // 0x63
{ MOS65XX_INS_STZ , MOS65XX_AM_ZP , 1 }, // 0x64
{ MOS65XX_INS_ADC , MOS65XX_AM_ZP , 1 }, // 0x65
{ MOS65XX_INS_ROR , MOS65XX_AM_ZP , 1 }, // 0x66
{ MOS65XX_INS_NOP , MOS65XX_AM_IMP , 0 }, // 0x67
{ MOS65XX_INS_PLA , MOS65XX_AM_IMP , 0 }, // 0x68
{ MOS65XX_INS_ADC , MOS65XX_AM_IMM , 1 }, // 0x69
{ MOS65XX_INS_ROR , MOS65XX_AM_ACC , 0 }, // 0x6a
{ MOS65XX_INS_NOP , MOS65XX_AM_IMP , 0 }, // 0x6b
{ MOS65XX_INS_JMP , MOS65XX_AM_ABS_IND , 2 }, // 0x6c
{ MOS65XX_INS_ADC , MOS65XX_AM_ABS , 2 }, // 0x6d
{ MOS65XX_INS_ROR , MOS65XX_AM_ABS , 2 }, // 0x6e
{ MOS65XX_INS_NOP , MOS65XX_AM_IMP , 0 }, // 0x6f
{ MOS65XX_INS_BVS , MOS65XX_AM_REL , 1 }, // 0x70
{ MOS65XX_INS_ADC , MOS65XX_AM_ZP_IND_Y , 1 }, // 0x71
{ MOS65XX_INS_ADC , MOS65XX_AM_ZP_IND , 1 }, // 0x72
{ MOS65XX_INS_NOP , MOS65XX_AM_IMP , 0 }, // 0x73
{ MOS65XX_INS_STZ , MOS65XX_AM_ZP_X , 1 }, // 0x74
{ MOS65XX_INS_ADC , MOS65XX_AM_ZP_X , 1 }, // 0x75
{ MOS65XX_INS_ROR , MOS65XX_AM_ZP_X , 1 }, // 0x76
{ MOS65XX_INS_NOP , MOS65XX_AM_IMP , 0 }, // 0x77
{ MOS65XX_INS_SEI , MOS65XX_AM_IMP , 0 }, // 0x78
{ MOS65XX_INS_ADC , MOS65XX_AM_ABS_Y , 2 }, // 0x79
{ MOS65XX_INS_PLY , MOS65XX_AM_IMP , 0 }, // 0x7a
{ MOS65XX_INS_NOP , MOS65XX_AM_IMP , 0 }, // 0x7b
{ MOS65XX_INS_JMP , MOS65XX_AM_ABS_X_IND , 2 }, // 0x7c
{ MOS65XX_INS_ADC , MOS65XX_AM_ABS_X , 2 }, // 0x7d
{ MOS65XX_INS_ROR , MOS65XX_AM_ABS_X , 2 }, // 0x7e
{ MOS65XX_INS_NOP , MOS65XX_AM_IMP , 0 }, // 0x7f
{ MOS65XX_INS_BRA , MOS65XX_AM_REL , 1 }, // 0x80
{ MOS65XX_INS_STA , MOS65XX_AM_ZP_X_IND , 1 }, // 0x81
{ MOS65XX_INS_NOP , MOS65XX_AM_IMP , 1 }, // 0x82
{ MOS65XX_INS_NOP , MOS65XX_AM_IMP , 0 }, // 0x83
{ MOS65XX_INS_STY , MOS65XX_AM_ZP , 1 }, // 0x84
{ MOS65XX_INS_STA , MOS65XX_AM_ZP , 1 }, // 0x85
{ MOS65XX_INS_STX , MOS65XX_AM_ZP , 1 }, // 0x86
{ MOS65XX_INS_NOP , MOS65XX_AM_IMP , 0 }, // 0x87
{ MOS65XX_INS_DEY , MOS65XX_AM_IMP , 0 }, // 0x88
{ MOS65XX_INS_BIT , MOS65XX_AM_IMM , 1 }, // 0x89
{ MOS65XX_INS_TXA , MOS65XX_AM_IMP , 0 }, // 0x8a
{ MOS65XX_INS_NOP , MOS65XX_AM_IMP , 0 }, // 0x8b
{ MOS65XX_INS_STY , MOS65XX_AM_ABS , 2 }, // 0x8c
{ MOS65XX_INS_STA , MOS65XX_AM_ABS , 2 }, // 0x8d
{ MOS65XX_INS_STX , MOS65XX_AM_ABS , 2 }, // 0x8e
{ MOS65XX_INS_NOP , MOS65XX_AM_IMP , 0 }, // 0x8f
{ MOS65XX_INS_BCC , MOS65XX_AM_REL , 1 }, // 0x90
{ MOS65XX_INS_STA , MOS65XX_AM_ZP_IND_Y , 1 }, // 0x91
{ MOS65XX_INS_STA , MOS65XX_AM_ZP_IND , 1 }, // 0x92
{ MOS65XX_INS_NOP , MOS65XX_AM_IMP , 0 }, // 0x93
{ MOS65XX_INS_STY , MOS65XX_AM_ZP_X , 1 }, // 0x94
{ MOS65XX_INS_STA , MOS65XX_AM_ZP_X , 1 }, // 0x95
{ MOS65XX_INS_STX , MOS65XX_AM_ZP_Y , 1 }, // 0x96
{ MOS65XX_INS_NOP , MOS65XX_AM_IMP , 0 }, // 0x97
{ MOS65XX_INS_TYA , MOS65XX_AM_IMP , 0 }, // 0x98
{ MOS65XX_INS_STA , MOS65XX_AM_ABS_Y , 2 }, // 0x99
{ MOS65XX_INS_TXS , MOS65XX_AM_IMP , 0 }, // 0x9a
{ MOS65XX_INS_NOP , MOS65XX_AM_IMP , 0 }, // 0x9b
{ MOS65XX_INS_STZ , MOS65XX_AM_ABS , 2 }, // 0x9c
{ MOS65XX_INS_STA , MOS65XX_AM_ABS_X , 2 }, // 0x9d
{ MOS65XX_INS_STZ , MOS65XX_AM_ABS_X , 2 }, // 0x9e
{ MOS65XX_INS_NOP , MOS65XX_AM_IMP , 0 }, // 0x9f
{ MOS65XX_INS_LDY , MOS65XX_AM_IMM , 1 }, // 0xa0
{ MOS65XX_INS_LDA , MOS65XX_AM_ZP_X_IND , 1 }, // 0xa1
{ MOS65XX_INS_LDX , MOS65XX_AM_IMM , 1 }, // 0xa2
{ MOS65XX_INS_NOP , MOS65XX_AM_IMP , 0 }, // 0xa3
{ MOS65XX_INS_LDY , MOS65XX_AM_ZP , 1 }, // 0xa4
{ MOS65XX_INS_LDA , MOS65XX_AM_ZP , 1 }, // 0xa5
{ MOS65XX_INS_LDX , MOS65XX_AM_ZP , 1 }, // 0xa6
{ MOS65XX_INS_NOP , MOS65XX_AM_IMP , 0 }, // 0xa7
{ MOS65XX_INS_TAY , MOS65XX_AM_IMP , 0 }, // 0xa8
{ MOS65XX_INS_LDA , MOS65XX_AM_IMM , 1 }, // 0xa9
{ MOS65XX_INS_TAX , MOS65XX_AM_IMP , 0 }, // 0xaa
{ MOS65XX_INS_NOP , MOS65XX_AM_IMP , 0 }, // 0xab
{ MOS65XX_INS_LDY , MOS65XX_AM_ABS , 2 }, // 0xac
{ MOS65XX_INS_LDA , MOS65XX_AM_ABS , 2 }, // 0xad
{ MOS65XX_INS_LDX , MOS65XX_AM_ABS , 2 }, // 0xae
{ MOS65XX_INS_NOP , MOS65XX_AM_IMP , 0 }, // 0xaf
{ MOS65XX_INS_BCS , MOS65XX_AM_REL , 1 }, // 0xb0
{ MOS65XX_INS_LDA , MOS65XX_AM_ZP_IND_Y , 1 }, // 0xb1
{ MOS65XX_INS_LDA , MOS65XX_AM_ZP_IND , 1 }, // 0xb2
{ MOS65XX_INS_NOP , MOS65XX_AM_IMP , 0 }, // 0xb3
{ MOS65XX_INS_LDY , MOS65XX_AM_ZP_X , 1 }, // 0xb4
{ MOS65XX_INS_LDA , MOS65XX_AM_ZP_X , 1 }, // 0xb5
{ MOS65XX_INS_LDX , MOS65XX_AM_ZP_Y , 1 }, // 0xb6
{ MOS65XX_INS_NOP , MOS65XX_AM_IMP , 0 }, // 0xb7
{ MOS65XX_INS_CLV , MOS65XX_AM_IMP , 0 }, // 0xb8
{ MOS65XX_INS_LDA , MOS65XX_AM_ABS_Y , 2 }, // 0xb9
{ MOS65XX_INS_TSX , MOS65XX_AM_IMP , 0 }, // 0xba
{ MOS65XX_INS_NOP , MOS65XX_AM_IMP , 0 }, // 0xbb
{ MOS65XX_INS_LDY , MOS65XX_AM_ABS_X , 2 }, // 0xbc
{ MOS65XX_INS_LDA , MOS65XX_AM_ABS_X , 2 }, // 0xbd
{ MOS65XX_INS_LDX , MOS65XX_AM_ABS_Y , 2 }, // 0xbe
{ MOS65XX_INS_NOP , MOS65XX_AM_IMP , 0 }, // 0xbf
{ MOS65XX_INS_CPY , MOS65XX_AM_IMM , 1 }, // 0xc0
{ MOS65XX_INS_CMP , MOS65XX_AM_ZP_X_IND , 1 }, // 0xc1
{ MOS65XX_INS_NOP , MOS65XX_AM_IMP , 1 }, // 0xc2
{ MOS65XX_INS_NOP , MOS65XX_AM_IMP , 0 }, // 0xc3
{ MOS65XX_INS_CPY , MOS65XX_AM_ZP , 1 }, // 0xc4
{ MOS65XX_INS_CMP , MOS65XX_AM_ZP , 1 }, // 0xc5
{ MOS65XX_INS_DEC , MOS65XX_AM_ZP , 1 }, // 0xc6
{ MOS65XX_INS_NOP , MOS65XX_AM_IMP , 0 }, // 0xc7
{ MOS65XX_INS_INY , MOS65XX_AM_IMP , 0 }, // 0xc8
{ MOS65XX_INS_CMP , MOS65XX_AM_IMM , 1 }, // 0xc9
{ MOS65XX_INS_DEX , MOS65XX_AM_IMP , 0 }, // 0xca
{ MOS65XX_INS_WAI , MOS65XX_AM_IMP , 0 }, // 0xcb
{ MOS65XX_INS_CPY , MOS65XX_AM_ABS , 2 }, // 0xcc
{ MOS65XX_INS_CMP , MOS65XX_AM_ABS , 2 }, // 0xcd
{ MOS65XX_INS_DEC , MOS65XX_AM_ABS , 2 }, // 0xce
{ MOS65XX_INS_NOP , MOS65XX_AM_IMP , 0 }, // 0xcf
{ MOS65XX_INS_BNE , MOS65XX_AM_REL , 1 }, // 0xd0
{ MOS65XX_INS_CMP , MOS65XX_AM_ZP_IND_Y , 1 }, // 0xd1
{ MOS65XX_INS_CMP , MOS65XX_AM_ZP_IND , 1 }, // 0xd2
{ MOS65XX_INS_NOP , MOS65XX_AM_IMP , 0 }, // 0xd3
{ MOS65XX_INS_NOP , MOS65XX_AM_IMP , 1 }, // 0xd4
{ MOS65XX_INS_CMP , MOS65XX_AM_ZP_X , 1 }, // 0xd5
{ MOS65XX_INS_DEC , MOS65XX_AM_ZP_X , 1 }, // 0xd6
{ MOS65XX_INS_NOP , MOS65XX_AM_IMP , 0 }, // 0xd7
{ MOS65XX_INS_CLD , MOS65XX_AM_IMP , 0 }, // 0xd8
{ MOS65XX_INS_CMP , MOS65XX_AM_ABS_Y , 2 }, // 0xd9
{ MOS65XX_INS_PHX , MOS65XX_AM_IMP , 0 }, // 0xda
{ MOS65XX_INS_STP , MOS65XX_AM_IMP , 0 }, // 0xdb
{ MOS65XX_INS_NOP , MOS65XX_AM_IMP , 2 }, // 0xdc
{ MOS65XX_INS_CMP , MOS65XX_AM_ABS_X , 2 }, // 0xdd
{ MOS65XX_INS_DEC , MOS65XX_AM_ABS_X , 2 }, // 0xde
{ MOS65XX_INS_NOP , MOS65XX_AM_IMP , 0 }, // 0xdf
{ MOS65XX_INS_CPX , MOS65XX_AM_IMM , 1 }, // 0xe0
{ MOS65XX_INS_SBC , MOS65XX_AM_ZP_X_IND , 1 }, // 0xe1
{ MOS65XX_INS_NOP , MOS65XX_AM_IMP , 1 }, // 0xe2
{ MOS65XX_INS_NOP , MOS65XX_AM_IMP , 0 }, // 0xe3
{ MOS65XX_INS_CPX , MOS65XX_AM_ZP , 1 }, // 0xe4
{ MOS65XX_INS_SBC , MOS65XX_AM_ZP , 1 }, // 0xe5
{ MOS65XX_INS_INC , MOS65XX_AM_ZP , 1 }, // 0xe6
{ MOS65XX_INS_NOP , MOS65XX_AM_IMP , 0 }, // 0xe7
{ MOS65XX_INS_INX , MOS65XX_AM_IMP , 0 }, // 0xe8
{ MOS65XX_INS_SBC , MOS65XX_AM_IMM , 1 }, // 0xe9
{ MOS65XX_INS_NOP , MOS65XX_AM_IMP , 0 }, // 0xea
{ MOS65XX_INS_NOP , MOS65XX_AM_IMP , 0 }, // 0xeb
{ MOS65XX_INS_CPX , MOS65XX_AM_ABS , 2 }, // 0xec
{ MOS65XX_INS_SBC , MOS65XX_AM_ABS , 2 }, // 0xed
{ MOS65XX_INS_INC , MOS65XX_AM_ABS , 2 }, // 0xee
{ MOS65XX_INS_NOP , MOS65XX_AM_IMP , 0 }, // 0xef
{ MOS65XX_INS_BEQ , MOS65XX_AM_REL , 1 }, // 0xf0
{ MOS65XX_INS_SBC , MOS65XX_AM_ZP_IND_Y , 1 }, // 0xf1
{ MOS65XX_INS_SBC , MOS65XX_AM_ZP_IND , 1 }, // 0xf2
{ MOS65XX_INS_NOP , MOS65XX_AM_IMP , 0 }, // 0xf3
{ MOS65XX_INS_NOP , MOS65XX_AM_IMP , 1 }, // 0xf4
{ MOS65XX_INS_SBC , MOS65XX_AM_ZP_X , 1 }, // 0xf5
{ MOS65XX_INS_INC , MOS65XX_AM_ZP_X , 1 }, // 0xf6
{ MOS65XX_INS_NOP , MOS65XX_AM_IMP , 0 }, // 0xf7
{ MOS65XX_INS_SED , MOS65XX_AM_IMP , 0 }, // 0xf8
{ MOS65XX_INS_SBC , MOS65XX_AM_ABS_Y , 2 }, // 0xf9
{ MOS65XX_INS_PLX , MOS65XX_AM_IMP , 0 }, // 0xfa
{ MOS65XX_INS_NOP , MOS65XX_AM_IMP , 0 }, // 0xfb
{ MOS65XX_INS_NOP , MOS65XX_AM_IMP , 2 }, // 0xfc
{ MOS65XX_INS_SBC , MOS65XX_AM_ABS_X , 2 }, // 0xfd
{ MOS65XX_INS_INC , MOS65XX_AM_ABS_X , 2 }, // 0xfe
{ MOS65XX_INS_NOP , MOS65XX_AM_IMP , 0 }, // 0xff

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{ MOS65XX_INS_BRK , MOS65XX_AM_INT , 1 }, // 0x00
{ MOS65XX_INS_ORA , MOS65XX_AM_ZP_X_IND , 1 }, // 0x01
{ MOS65XX_INS_NOP , MOS65XX_AM_IMP , 1 }, // 0x02
{ MOS65XX_INS_NOP , MOS65XX_AM_IMP , 0 }, // 0x03
{ MOS65XX_INS_TSB , MOS65XX_AM_ZP , 1 }, // 0x04
{ MOS65XX_INS_ORA , MOS65XX_AM_ZP , 1 }, // 0x05
{ MOS65XX_INS_ASL , MOS65XX_AM_ZP , 1 }, // 0x06
{ MOS65XX_INS_RMB , MOS65XX_AM_ZP , 1 }, // 0x07
{ MOS65XX_INS_PHP , MOS65XX_AM_IMP , 0 }, // 0x08
{ MOS65XX_INS_ORA , MOS65XX_AM_IMM , 1 }, // 0x09
{ MOS65XX_INS_ASL , MOS65XX_AM_ACC , 0 }, // 0x0a
{ MOS65XX_INS_NOP , MOS65XX_AM_IMP , 0 }, // 0x0b
{ MOS65XX_INS_TSB , MOS65XX_AM_ABS , 2 }, // 0x0c
{ MOS65XX_INS_ORA , MOS65XX_AM_ABS , 2 }, // 0x0d
{ MOS65XX_INS_ASL , MOS65XX_AM_ABS , 2 }, // 0x0e
{ MOS65XX_INS_BBR , MOS65XX_AM_ZP_REL , 2 }, // 0x0f
{ MOS65XX_INS_BPL , MOS65XX_AM_REL , 1 }, // 0x10
{ MOS65XX_INS_ORA , MOS65XX_AM_ZP_IND_Y , 1 }, // 0x11
{ MOS65XX_INS_ORA , MOS65XX_AM_ZP_IND , 1 }, // 0x12
{ MOS65XX_INS_NOP , MOS65XX_AM_IMP , 0 }, // 0x13
{ MOS65XX_INS_TRB , MOS65XX_AM_ZP , 1 }, // 0x14
{ MOS65XX_INS_ORA , MOS65XX_AM_ZP_X , 1 }, // 0x15
{ MOS65XX_INS_ASL , MOS65XX_AM_ZP_X , 1 }, // 0x16
{ MOS65XX_INS_RMB , MOS65XX_AM_ZP , 1 }, // 0x17
{ MOS65XX_INS_CLC , MOS65XX_AM_IMP , 0 }, // 0x18
{ MOS65XX_INS_ORA , MOS65XX_AM_ABS_Y , 2 }, // 0x19
{ MOS65XX_INS_INC , MOS65XX_AM_ACC , 0 }, // 0x1a
{ MOS65XX_INS_NOP , MOS65XX_AM_IMP , 0 }, // 0x1b
{ MOS65XX_INS_TRB , MOS65XX_AM_ABS , 2 }, // 0x1c
{ MOS65XX_INS_ORA , MOS65XX_AM_ABS_X , 2 }, // 0x1d
{ MOS65XX_INS_ASL , MOS65XX_AM_ABS_X , 2 }, // 0x1e
{ MOS65XX_INS_BBR , MOS65XX_AM_ZP_REL , 2 }, // 0x1f
{ MOS65XX_INS_JSR , MOS65XX_AM_ABS , 2 }, // 0x20
{ MOS65XX_INS_AND , MOS65XX_AM_ZP_X_IND , 1 }, // 0x21
{ MOS65XX_INS_NOP , MOS65XX_AM_IMP , 1 }, // 0x22
{ MOS65XX_INS_NOP , MOS65XX_AM_IMP , 0 }, // 0x23
{ MOS65XX_INS_BIT , MOS65XX_AM_ZP , 1 }, // 0x24
{ MOS65XX_INS_AND , MOS65XX_AM_ZP , 1 }, // 0x25
{ MOS65XX_INS_ROL , MOS65XX_AM_ZP , 1 }, // 0x26
{ MOS65XX_INS_RMB , MOS65XX_AM_ZP , 1 }, // 0x27
{ MOS65XX_INS_PLP , MOS65XX_AM_IMP , 0 }, // 0x28
{ MOS65XX_INS_AND , MOS65XX_AM_IMM , 1 }, // 0x29
{ MOS65XX_INS_ROL , MOS65XX_AM_ACC , 0 }, // 0x2a
{ MOS65XX_INS_NOP , MOS65XX_AM_IMP , 0 }, // 0x2b
{ MOS65XX_INS_BIT , MOS65XX_AM_ABS , 2 }, // 0x2c
{ MOS65XX_INS_AND , MOS65XX_AM_ABS , 2 }, // 0x2d
{ MOS65XX_INS_ROL , MOS65XX_AM_ABS , 2 }, // 0x2e
{ MOS65XX_INS_BBR , MOS65XX_AM_ZP_REL , 2 }, // 0x2f
{ MOS65XX_INS_BMI , MOS65XX_AM_REL , 1 }, // 0x30
{ MOS65XX_INS_AND , MOS65XX_AM_ZP_IND_Y , 1 }, // 0x31
{ MOS65XX_INS_AND , MOS65XX_AM_ZP_IND , 1 }, // 0x32
{ MOS65XX_INS_NOP , MOS65XX_AM_IMP , 0 }, // 0x33
{ MOS65XX_INS_BIT , MOS65XX_AM_ZP_X , 1 }, // 0x34
{ MOS65XX_INS_AND , MOS65XX_AM_ZP_X , 1 }, // 0x35
{ MOS65XX_INS_ROL , MOS65XX_AM_ZP_X , 1 }, // 0x36
{ MOS65XX_INS_RMB , MOS65XX_AM_ZP , 1 }, // 0x37
{ MOS65XX_INS_SEC , MOS65XX_AM_IMP , 0 }, // 0x38
{ MOS65XX_INS_AND , MOS65XX_AM_ABS_Y , 2 }, // 0x39
{ MOS65XX_INS_DEC , MOS65XX_AM_ACC , 0 }, // 0x3a
{ MOS65XX_INS_NOP , MOS65XX_AM_IMP , 0 }, // 0x3b
{ MOS65XX_INS_BIT , MOS65XX_AM_ABS_X , 2 }, // 0x3c
{ MOS65XX_INS_AND , MOS65XX_AM_ABS_X , 2 }, // 0x3d
{ MOS65XX_INS_ROL , MOS65XX_AM_ABS_X , 2 }, // 0x3e
{ MOS65XX_INS_BBR , MOS65XX_AM_ZP_REL , 2 }, // 0x3f
{ MOS65XX_INS_RTI , MOS65XX_AM_IMP , 0 }, // 0x40
{ MOS65XX_INS_EOR , MOS65XX_AM_ZP_X_IND , 1 }, // 0x41
{ MOS65XX_INS_NOP , MOS65XX_AM_IMP , 1 }, // 0x42
{ MOS65XX_INS_NOP , MOS65XX_AM_IMP , 0 }, // 0x43
{ MOS65XX_INS_NOP , MOS65XX_AM_IMP , 1 }, // 0x44
{ MOS65XX_INS_EOR , MOS65XX_AM_ZP , 1 }, // 0x45
{ MOS65XX_INS_LSR , MOS65XX_AM_ZP , 1 }, // 0x46
{ MOS65XX_INS_RMB , MOS65XX_AM_ZP , 1 }, // 0x47
{ MOS65XX_INS_PHA , MOS65XX_AM_IMP , 0 }, // 0x48
{ MOS65XX_INS_EOR , MOS65XX_AM_IMM , 1 }, // 0x49
{ MOS65XX_INS_LSR , MOS65XX_AM_ACC , 0 }, // 0x4a
{ MOS65XX_INS_NOP , MOS65XX_AM_IMP , 0 }, // 0x4b
{ MOS65XX_INS_JMP , MOS65XX_AM_ABS , 2 }, // 0x4c
{ MOS65XX_INS_EOR , MOS65XX_AM_ABS , 2 }, // 0x4d
{ MOS65XX_INS_LSR , MOS65XX_AM_ABS , 2 }, // 0x4e
{ MOS65XX_INS_BBR , MOS65XX_AM_ZP_REL , 2 }, // 0x4f
{ MOS65XX_INS_BVC , MOS65XX_AM_REL , 1 }, // 0x50
{ MOS65XX_INS_EOR , MOS65XX_AM_ZP_IND_Y , 1 }, // 0x51
{ MOS65XX_INS_EOR , MOS65XX_AM_ZP_IND , 1 }, // 0x52
{ MOS65XX_INS_NOP , MOS65XX_AM_IMP , 0 }, // 0x53
{ MOS65XX_INS_NOP , MOS65XX_AM_IMP , 1 }, // 0x54
{ MOS65XX_INS_EOR , MOS65XX_AM_ZP_X , 1 }, // 0x55
{ MOS65XX_INS_LSR , MOS65XX_AM_ZP_X , 1 }, // 0x56
{ MOS65XX_INS_RMB , MOS65XX_AM_ZP , 1 }, // 0x57
{ MOS65XX_INS_CLI , MOS65XX_AM_IMP , 0 }, // 0x58
{ MOS65XX_INS_EOR , MOS65XX_AM_ABS_Y , 2 }, // 0x59
{ MOS65XX_INS_PHY , MOS65XX_AM_IMP , 0 }, // 0x5a
{ MOS65XX_INS_NOP , MOS65XX_AM_IMP , 0 }, // 0x5b
{ MOS65XX_INS_NOP , MOS65XX_AM_IMP , 2 }, // 0x5c
{ MOS65XX_INS_EOR , MOS65XX_AM_ABS_X , 2 }, // 0x5d
{ MOS65XX_INS_LSR , MOS65XX_AM_ABS_X , 2 }, // 0x5e
{ MOS65XX_INS_BBR , MOS65XX_AM_ZP_REL , 2 }, // 0x5f
{ MOS65XX_INS_RTS , MOS65XX_AM_IMP , 0 }, // 0x60
{ MOS65XX_INS_ADC , MOS65XX_AM_ZP_X_IND , 1 }, // 0x61
{ MOS65XX_INS_NOP , MOS65XX_AM_IMP , 1 }, // 0x62
{ MOS65XX_INS_NOP , MOS65XX_AM_IMP , 0 }, // 0x63
{ MOS65XX_INS_STZ , MOS65XX_AM_ZP , 1 }, // 0x64
{ MOS65XX_INS_ADC , MOS65XX_AM_ZP , 1 }, // 0x65
{ MOS65XX_INS_ROR , MOS65XX_AM_ZP , 1 }, // 0x66
{ MOS65XX_INS_RMB , MOS65XX_AM_ZP , 1 }, // 0x67
{ MOS65XX_INS_PLA , MOS65XX_AM_IMP , 0 }, // 0x68
{ MOS65XX_INS_ADC , MOS65XX_AM_IMM , 1 }, // 0x69
{ MOS65XX_INS_ROR , MOS65XX_AM_ACC , 0 }, // 0x6a
{ MOS65XX_INS_NOP , MOS65XX_AM_IMP , 0 }, // 0x6b
{ MOS65XX_INS_JMP , MOS65XX_AM_ABS_IND , 2 }, // 0x6c
{ MOS65XX_INS_ADC , MOS65XX_AM_ABS , 2 }, // 0x6d
{ MOS65XX_INS_ROR , MOS65XX_AM_ABS , 2 }, // 0x6e
{ MOS65XX_INS_BBR , MOS65XX_AM_ZP_REL , 2 }, // 0x6f
{ MOS65XX_INS_BVS , MOS65XX_AM_REL , 1 }, // 0x70
{ MOS65XX_INS_ADC , MOS65XX_AM_ZP_IND_Y , 1 }, // 0x71
{ MOS65XX_INS_ADC , MOS65XX_AM_ZP_IND , 1 }, // 0x72
{ MOS65XX_INS_NOP , MOS65XX_AM_IMP , 0 }, // 0x73
{ MOS65XX_INS_STZ , MOS65XX_AM_ZP_X , 1 }, // 0x74
{ MOS65XX_INS_ADC , MOS65XX_AM_ZP_X , 1 }, // 0x75
{ MOS65XX_INS_ROR , MOS65XX_AM_ZP_X , 1 }, // 0x76
{ MOS65XX_INS_RMB , MOS65XX_AM_ZP , 1 }, // 0x77
{ MOS65XX_INS_SEI , MOS65XX_AM_IMP , 0 }, // 0x78
{ MOS65XX_INS_ADC , MOS65XX_AM_ABS_Y , 2 }, // 0x79
{ MOS65XX_INS_PLY , MOS65XX_AM_IMP , 0 }, // 0x7a
{ MOS65XX_INS_NOP , MOS65XX_AM_IMP , 0 }, // 0x7b
{ MOS65XX_INS_JMP , MOS65XX_AM_ABS_X_IND , 2 }, // 0x7c
{ MOS65XX_INS_ADC , MOS65XX_AM_ABS_X , 2 }, // 0x7d
{ MOS65XX_INS_ROR , MOS65XX_AM_ABS_X , 2 }, // 0x7e
{ MOS65XX_INS_BBR , MOS65XX_AM_ZP_REL , 2 }, // 0x7f
{ MOS65XX_INS_BRA , MOS65XX_AM_REL , 1 }, // 0x80
{ MOS65XX_INS_STA , MOS65XX_AM_ZP_X_IND , 1 }, // 0x81
{ MOS65XX_INS_NOP , MOS65XX_AM_IMP , 1 }, // 0x82
{ MOS65XX_INS_NOP , MOS65XX_AM_IMP , 0 }, // 0x83
{ MOS65XX_INS_STY , MOS65XX_AM_ZP , 1 }, // 0x84
{ MOS65XX_INS_STA , MOS65XX_AM_ZP , 1 }, // 0x85
{ MOS65XX_INS_STX , MOS65XX_AM_ZP , 1 }, // 0x86
{ MOS65XX_INS_SMB , MOS65XX_AM_ZP , 1 }, // 0x87
{ MOS65XX_INS_DEY , MOS65XX_AM_IMP , 0 }, // 0x88
{ MOS65XX_INS_BIT , MOS65XX_AM_IMM , 1 }, // 0x89
{ MOS65XX_INS_TXA , MOS65XX_AM_IMP , 0 }, // 0x8a
{ MOS65XX_INS_NOP , MOS65XX_AM_IMP , 0 }, // 0x8b
{ MOS65XX_INS_STY , MOS65XX_AM_ABS , 2 }, // 0x8c
{ MOS65XX_INS_STA , MOS65XX_AM_ABS , 2 }, // 0x8d
{ MOS65XX_INS_STX , MOS65XX_AM_ABS , 2 }, // 0x8e
{ MOS65XX_INS_BBS , MOS65XX_AM_ZP_REL , 2 }, // 0x8f
{ MOS65XX_INS_BCC , MOS65XX_AM_REL , 1 }, // 0x90
{ MOS65XX_INS_STA , MOS65XX_AM_ZP_IND_Y , 1 }, // 0x91
{ MOS65XX_INS_STA , MOS65XX_AM_ZP_IND , 1 }, // 0x92
{ MOS65XX_INS_NOP , MOS65XX_AM_IMP , 0 }, // 0x93
{ MOS65XX_INS_STY , MOS65XX_AM_ZP_X , 1 }, // 0x94
{ MOS65XX_INS_STA , MOS65XX_AM_ZP_X , 1 }, // 0x95
{ MOS65XX_INS_STX , MOS65XX_AM_ZP_Y , 1 }, // 0x96
{ MOS65XX_INS_SMB , MOS65XX_AM_ZP , 1 }, // 0x97
{ MOS65XX_INS_TYA , MOS65XX_AM_IMP , 0 }, // 0x98
{ MOS65XX_INS_STA , MOS65XX_AM_ABS_Y , 2 }, // 0x99
{ MOS65XX_INS_TXS , MOS65XX_AM_IMP , 0 }, // 0x9a
{ MOS65XX_INS_NOP , MOS65XX_AM_IMP , 0 }, // 0x9b
{ MOS65XX_INS_STZ , MOS65XX_AM_ABS , 2 }, // 0x9c
{ MOS65XX_INS_STA , MOS65XX_AM_ABS_X , 2 }, // 0x9d
{ MOS65XX_INS_STZ , MOS65XX_AM_ABS_X , 2 }, // 0x9e
{ MOS65XX_INS_BBS , MOS65XX_AM_ZP_REL , 2 }, // 0x9f
{ MOS65XX_INS_LDY , MOS65XX_AM_IMM , 1 }, // 0xa0
{ MOS65XX_INS_LDA , MOS65XX_AM_ZP_X_IND , 1 }, // 0xa1
{ MOS65XX_INS_LDX , MOS65XX_AM_IMM , 1 }, // 0xa2
{ MOS65XX_INS_NOP , MOS65XX_AM_IMP , 0 }, // 0xa3
{ MOS65XX_INS_LDY , MOS65XX_AM_ZP , 1 }, // 0xa4
{ MOS65XX_INS_LDA , MOS65XX_AM_ZP , 1 }, // 0xa5
{ MOS65XX_INS_LDX , MOS65XX_AM_ZP , 1 }, // 0xa6
{ MOS65XX_INS_SMB , MOS65XX_AM_ZP , 1 }, // 0xa7
{ MOS65XX_INS_TAY , MOS65XX_AM_IMP , 0 }, // 0xa8
{ MOS65XX_INS_LDA , MOS65XX_AM_IMM , 1 }, // 0xa9
{ MOS65XX_INS_TAX , MOS65XX_AM_IMP , 0 }, // 0xaa
{ MOS65XX_INS_NOP , MOS65XX_AM_IMP , 0 }, // 0xab
{ MOS65XX_INS_LDY , MOS65XX_AM_ABS , 2 }, // 0xac
{ MOS65XX_INS_LDA , MOS65XX_AM_ABS , 2 }, // 0xad
{ MOS65XX_INS_LDX , MOS65XX_AM_ABS , 2 }, // 0xae
{ MOS65XX_INS_BBS , MOS65XX_AM_ZP_REL , 2 }, // 0xaf
{ MOS65XX_INS_BCS , MOS65XX_AM_REL , 1 }, // 0xb0
{ MOS65XX_INS_LDA , MOS65XX_AM_ZP_IND_Y , 1 }, // 0xb1
{ MOS65XX_INS_LDA , MOS65XX_AM_ZP_IND , 1 }, // 0xb2
{ MOS65XX_INS_NOP , MOS65XX_AM_IMP , 0 }, // 0xb3
{ MOS65XX_INS_LDY , MOS65XX_AM_ZP_X , 1 }, // 0xb4
{ MOS65XX_INS_LDA , MOS65XX_AM_ZP_X , 1 }, // 0xb5
{ MOS65XX_INS_LDX , MOS65XX_AM_ZP_Y , 1 }, // 0xb6
{ MOS65XX_INS_SMB , MOS65XX_AM_ZP , 1 }, // 0xb7
{ MOS65XX_INS_CLV , MOS65XX_AM_IMP , 0 }, // 0xb8
{ MOS65XX_INS_LDA , MOS65XX_AM_ABS_Y , 2 }, // 0xb9
{ MOS65XX_INS_TSX , MOS65XX_AM_IMP , 0 }, // 0xba
{ MOS65XX_INS_NOP , MOS65XX_AM_IMP , 0 }, // 0xbb
{ MOS65XX_INS_LDY , MOS65XX_AM_ABS_X , 2 }, // 0xbc
{ MOS65XX_INS_LDA , MOS65XX_AM_ABS_X , 2 }, // 0xbd
{ MOS65XX_INS_LDX , MOS65XX_AM_ABS_Y , 2 }, // 0xbe
{ MOS65XX_INS_BBS , MOS65XX_AM_ZP_REL , 2 }, // 0xbf
{ MOS65XX_INS_CPY , MOS65XX_AM_IMM , 1 }, // 0xc0
{ MOS65XX_INS_CMP , MOS65XX_AM_ZP_X_IND , 1 }, // 0xc1
{ MOS65XX_INS_NOP , MOS65XX_AM_IMP , 1 }, // 0xc2
{ MOS65XX_INS_NOP , MOS65XX_AM_IMP , 0 }, // 0xc3
{ MOS65XX_INS_CPY , MOS65XX_AM_ZP , 1 }, // 0xc4
{ MOS65XX_INS_CMP , MOS65XX_AM_ZP , 1 }, // 0xc5
{ MOS65XX_INS_DEC , MOS65XX_AM_ZP , 1 }, // 0xc6
{ MOS65XX_INS_SMB , MOS65XX_AM_ZP , 1 }, // 0xc7
{ MOS65XX_INS_INY , MOS65XX_AM_IMP , 0 }, // 0xc8
{ MOS65XX_INS_CMP , MOS65XX_AM_IMM , 1 }, // 0xc9
{ MOS65XX_INS_DEX , MOS65XX_AM_IMP , 0 }, // 0xca
{ MOS65XX_INS_WAI , MOS65XX_AM_IMP , 0 }, // 0xcb
{ MOS65XX_INS_CPY , MOS65XX_AM_ABS , 2 }, // 0xcc
{ MOS65XX_INS_CMP , MOS65XX_AM_ABS , 2 }, // 0xcd
{ MOS65XX_INS_DEC , MOS65XX_AM_ABS , 2 }, // 0xce
{ MOS65XX_INS_BBS , MOS65XX_AM_ZP_REL , 2 }, // 0xcf
{ MOS65XX_INS_BNE , MOS65XX_AM_REL , 1 }, // 0xd0
{ MOS65XX_INS_CMP , MOS65XX_AM_ZP_IND_Y , 1 }, // 0xd1
{ MOS65XX_INS_CMP , MOS65XX_AM_ZP_IND , 1 }, // 0xd2
{ MOS65XX_INS_NOP , MOS65XX_AM_IMP , 0 }, // 0xd3
{ MOS65XX_INS_NOP , MOS65XX_AM_IMP , 1 }, // 0xd4
{ MOS65XX_INS_CMP , MOS65XX_AM_ZP_X , 1 }, // 0xd5
{ MOS65XX_INS_DEC , MOS65XX_AM_ZP_X , 1 }, // 0xd6
{ MOS65XX_INS_SMB , MOS65XX_AM_ZP , 1 }, // 0xd7
{ MOS65XX_INS_CLD , MOS65XX_AM_IMP , 0 }, // 0xd8
{ MOS65XX_INS_CMP , MOS65XX_AM_ABS_Y , 2 }, // 0xd9
{ MOS65XX_INS_PHX , MOS65XX_AM_IMP , 0 }, // 0xda
{ MOS65XX_INS_STP , MOS65XX_AM_IMP , 0 }, // 0xdb
{ MOS65XX_INS_NOP , MOS65XX_AM_IMP , 2 }, // 0xdc
{ MOS65XX_INS_CMP , MOS65XX_AM_ABS_X , 2 }, // 0xdd
{ MOS65XX_INS_DEC , MOS65XX_AM_ABS_X , 2 }, // 0xde
{ MOS65XX_INS_BBS , MOS65XX_AM_ZP_REL , 2 }, // 0xdf
{ MOS65XX_INS_CPX , MOS65XX_AM_IMM , 1 }, // 0xe0
{ MOS65XX_INS_SBC , MOS65XX_AM_ZP_X_IND , 1 }, // 0xe1
{ MOS65XX_INS_NOP , MOS65XX_AM_IMP , 1 }, // 0xe2
{ MOS65XX_INS_NOP , MOS65XX_AM_IMP , 0 }, // 0xe3
{ MOS65XX_INS_CPX , MOS65XX_AM_ZP , 1 }, // 0xe4
{ MOS65XX_INS_SBC , MOS65XX_AM_ZP , 1 }, // 0xe5
{ MOS65XX_INS_INC , MOS65XX_AM_ZP , 1 }, // 0xe6
{ MOS65XX_INS_SMB , MOS65XX_AM_ZP , 1 }, // 0xe7
{ MOS65XX_INS_INX , MOS65XX_AM_IMP , 0 }, // 0xe8
{ MOS65XX_INS_SBC , MOS65XX_AM_IMM , 1 }, // 0xe9
{ MOS65XX_INS_NOP , MOS65XX_AM_IMP , 0 }, // 0xea
{ MOS65XX_INS_NOP , MOS65XX_AM_IMP , 0 }, // 0xeb
{ MOS65XX_INS_CPX , MOS65XX_AM_ABS , 2 }, // 0xec
{ MOS65XX_INS_SBC , MOS65XX_AM_ABS , 2 }, // 0xed
{ MOS65XX_INS_INC , MOS65XX_AM_ABS , 2 }, // 0xee
{ MOS65XX_INS_BBS , MOS65XX_AM_ZP_REL , 2 }, // 0xef
{ MOS65XX_INS_BEQ , MOS65XX_AM_REL , 1 }, // 0xf0
{ MOS65XX_INS_SBC , MOS65XX_AM_ZP_IND_Y , 1 }, // 0xf1
{ MOS65XX_INS_SBC , MOS65XX_AM_ZP_IND , 1 }, // 0xf2
{ MOS65XX_INS_NOP , MOS65XX_AM_IMP , 0 }, // 0xf3
{ MOS65XX_INS_NOP , MOS65XX_AM_IMP , 1 }, // 0xf4
{ MOS65XX_INS_SBC , MOS65XX_AM_ZP_X , 1 }, // 0xf5
{ MOS65XX_INS_INC , MOS65XX_AM_ZP_X , 1 }, // 0xf6
{ MOS65XX_INS_SMB , MOS65XX_AM_ZP , 1 }, // 0xf7
{ MOS65XX_INS_SED , MOS65XX_AM_IMP , 0 }, // 0xf8
{ MOS65XX_INS_SBC , MOS65XX_AM_ABS_Y , 2 }, // 0xf9
{ MOS65XX_INS_PLX , MOS65XX_AM_IMP , 0 }, // 0xfa
{ MOS65XX_INS_NOP , MOS65XX_AM_IMP , 0 }, // 0xfb
{ MOS65XX_INS_NOP , MOS65XX_AM_IMP , 2 }, // 0xfc
{ MOS65XX_INS_SBC , MOS65XX_AM_ABS_X , 2 }, // 0xfd
{ MOS65XX_INS_INC , MOS65XX_AM_ABS_X , 2 }, // 0xfe
{ MOS65XX_INS_BBS , MOS65XX_AM_ZP_REL , 2 }, // 0xff

16
bindings/python/capstone/__init__.py
View File

@ -79,6 +79,13 @@ __all__ = [
'CS_MODE_BPF_EXTENDED',
'CS_MODE_RISCV32',
'CS_MODE_RISCV64',
'CS_MODE_MOS65XX_6502',
'CS_MODE_MOS65XX_65C02',
'CS_MODE_MOS65XX_W65C02',
'CS_MODE_MOS65XX_65816',
'CS_MODE_MOS65XX_65816_LONG_M',
'CS_MODE_MOS65XX_65816_LONG_X',
'CS_MODE_MOS65XX_65816_LONG_MX',
'CS_OPT_SYNTAX',
'CS_OPT_SYNTAX_DEFAULT',
@ -86,6 +93,7 @@ __all__ = [
'CS_OPT_SYNTAX_ATT',
'CS_OPT_SYNTAX_NOREGNAME',
'CS_OPT_SYNTAX_MASM',
'CS_OPT_SYNTAX_MOTOROLA',
'CS_OPT_DETAIL',
'CS_OPT_MODE',
@ -208,6 +216,13 @@ CS_MODE_BPF_EXTENDED = (1 << 0) # Extended BPF mode
CS_MODE_RISCV32 = (1 << 0) # RISCV32 mode
CS_MODE_RISCV64 = (1 << 1) # RISCV64 mode
CS_MODE_RISCVC = (1 << 2) # RISCV compressed mode
CS_MODE_MOS65XX_6502 = (1 << 1) # MOS65XXX MOS 6502
CS_MODE_MOS65XX_65C02 = (1 << 2) # MOS65XXX WDC 65c02
CS_MODE_MOS65XX_W65C02 = (1 << 3) # MOS65XXX WDC W65c02
CS_MODE_MOS65XX_65816 = (1 << 4) # MOS65XXX WDC 65816, 8-bit m/x
CS_MODE_MOS65XX_65816_LONG_M = (1 << 5) # MOS65XXX WDC 65816, 16-bit m, 8-bit x
CS_MODE_MOS65XX_65816_LONG_X = (1 << 6) # MOS65XXX WDC 65816, 8-bit m, 16-bit x
CS_MODE_MOS65XX_65816_LONG_MX = CS_MODE_MOS65XX_65816_LONG_M | CS_MODE_MOS65XX_65816_LONG_X
# Capstone option type
CS_OPT_SYNTAX = 1 # Intel X86 asm syntax (CS_ARCH_X86 arch)
@ -250,6 +265,7 @@ CS_OPT_SYNTAX_INTEL = 1 # Intel X86 asm syntax - default syntax on X86 (CS_OP
CS_OPT_SYNTAX_ATT = 2 # ATT asm syntax (CS_OPT_SYNTAX, CS_ARCH_X86)
CS_OPT_SYNTAX_NOREGNAME = 3 # Asm syntax prints register name with only number - (CS_OPT_SYNTAX, CS_ARCH_PPC, CS_ARCH_ARM)
CS_OPT_SYNTAX_MASM = 4 # MASM syntax (CS_OPT_SYNTAX, CS_ARCH_X86)
CS_OPT_SYNTAX_MOTOROLA = 5 # MOS65XX use $ as hex prefix
# Capstone error type
CS_ERR_OK = 0 # No error: everything was fine

188
bindings/python/capstone/mos65xx_const.py
View File

@ -6,86 +6,142 @@ MOS65XX_REG_X = 2
MOS65XX_REG_Y = 3
MOS65XX_REG_P = 4
MOS65XX_REG_SP = 5
MOS65XX_REG_ENDING = 6
MOS65XX_REG_DP = 6
MOS65XX_REG_B = 7
MOS65XX_REG_K = 8
MOS65XX_REG_ENDING = 9
MOS65XX_AM_NONE = 0
MOS65XX_AM_IMP = 1
MOS65XX_AM_ACC = 2
MOS65XX_AM_ABS = 3
MOS65XX_AM_ZP = 4
MOS65XX_AM_IMM = 5
MOS65XX_AM_ABSX = 6
MOS65XX_AM_ABSY = 7
MOS65XX_AM_INDX = 8
MOS65XX_AM_INDY = 9
MOS65XX_AM_ZPX = 10
MOS65XX_AM_ZPY = 11
MOS65XX_AM_REL = 12
MOS65XX_AM_IND = 13
MOS65XX_AM_IMM = 3
MOS65XX_AM_REL = 4
MOS65XX_AM_INT = 5
MOS65XX_AM_BLOCK = 6
MOS65XX_AM_ZP = 7
MOS65XX_AM_ZP_X = 8
MOS65XX_AM_ZP_Y = 9
MOS65XX_AM_ZP_REL = 10
MOS65XX_AM_ZP_IND = 11
MOS65XX_AM_ZP_X_IND = 12
MOS65XX_AM_ZP_IND_Y = 13
MOS65XX_AM_ZP_IND_LONG = 14
MOS65XX_AM_ZP_IND_LONG_Y = 15
MOS65XX_AM_ABS = 16
MOS65XX_AM_ABS_X = 17
MOS65XX_AM_ABS_Y = 18
MOS65XX_AM_ABS_IND = 19
MOS65XX_AM_ABS_X_IND = 20
MOS65XX_AM_ABS_IND_LONG = 21
MOS65XX_AM_ABS_LONG = 22
MOS65XX_AM_ABS_LONG_X = 23
MOS65XX_AM_SR = 24
MOS65XX_AM_SR_IND_Y = 25
MOS65XX_INS_INVALID = 0
MOS65XX_INS_ADC = 1
MOS65XX_INS_AND = 2
MOS65XX_INS_ASL = 3
MOS65XX_INS_BCC = 4
MOS65XX_INS_BCS = 5
MOS65XX_INS_BEQ = 6
MOS65XX_INS_BIT = 7
MOS65XX_INS_BMI = 8
MOS65XX_INS_BNE = 9
MOS65XX_INS_BPL = 10
MOS65XX_INS_BRK = 11
MOS65XX_INS_BVC = 12
MOS65XX_INS_BVS = 13
MOS65XX_INS_CLC = 14
MOS65XX_INS_CLD = 15
MOS65XX_INS_CLI = 16
MOS65XX_INS_CLV = 17
MOS65XX_INS_CMP = 18
MOS65XX_INS_CPX = 19
MOS65XX_INS_CPY = 20
MOS65XX_INS_DEC = 21
MOS65XX_INS_DEX = 22
MOS65XX_INS_DEY = 23
MOS65XX_INS_EOR = 24
MOS65XX_INS_INC = 25
MOS65XX_INS_INX = 26
MOS65XX_INS_INY = 27
MOS65XX_INS_JMP = 28
MOS65XX_INS_JSR = 29
MOS65XX_INS_LDA = 30
MOS65XX_INS_LDX = 31
MOS65XX_INS_LDY = 32
MOS65XX_INS_LSR = 33
MOS65XX_INS_NOP = 34
MOS65XX_INS_ORA = 35
MOS65XX_INS_PHA = 36
MOS65XX_INS_PLA = 37
MOS65XX_INS_PHP = 38
MOS65XX_INS_PLP = 39
MOS65XX_INS_ROL = 40
MOS65XX_INS_ROR = 41
MOS65XX_INS_RTI = 42
MOS65XX_INS_RTS = 43
MOS65XX_INS_SBC = 44
MOS65XX_INS_SEC = 45
MOS65XX_INS_SED = 46
MOS65XX_INS_SEI = 47
MOS65XX_INS_STA = 48
MOS65XX_INS_STX = 49
MOS65XX_INS_STY = 50
MOS65XX_INS_TAX = 51
MOS65XX_INS_TAY = 52
MOS65XX_INS_TSX = 53
MOS65XX_INS_TXA = 54
MOS65XX_INS_TXS = 55
MOS65XX_INS_TYA = 56
MOS65XX_INS_ENDING = 57
MOS65XX_INS_BBR = 4
MOS65XX_INS_BBS = 5
MOS65XX_INS_BCC = 6
MOS65XX_INS_BCS = 7
MOS65XX_INS_BEQ = 8
MOS65XX_INS_BIT = 9
MOS65XX_INS_BMI = 10
MOS65XX_INS_BNE = 11
MOS65XX_INS_BPL = 12
MOS65XX_INS_BRA = 13
MOS65XX_INS_BRK = 14
MOS65XX_INS_BRL = 15
MOS65XX_INS_BVC = 16
MOS65XX_INS_BVS = 17
MOS65XX_INS_CLC = 18
MOS65XX_INS_CLD = 19
MOS65XX_INS_CLI = 20
MOS65XX_INS_CLV = 21
MOS65XX_INS_CMP = 22
MOS65XX_INS_COP = 23
MOS65XX_INS_CPX = 24
MOS65XX_INS_CPY = 25
MOS65XX_INS_DEC = 26
MOS65XX_INS_DEX = 27
MOS65XX_INS_DEY = 28
MOS65XX_INS_EOR = 29
MOS65XX_INS_INC = 30
MOS65XX_INS_INX = 31
MOS65XX_INS_INY = 32
MOS65XX_INS_JML = 33
MOS65XX_INS_JMP = 34
MOS65XX_INS_JSL = 35
MOS65XX_INS_JSR = 36
MOS65XX_INS_LDA = 37
MOS65XX_INS_LDX = 38
MOS65XX_INS_LDY = 39
MOS65XX_INS_LSR = 40
MOS65XX_INS_MVN = 41
MOS65XX_INS_MVP = 42
MOS65XX_INS_NOP = 43
MOS65XX_INS_ORA = 44
MOS65XX_INS_PEA = 45
MOS65XX_INS_PEI = 46
MOS65XX_INS_PER = 47
MOS65XX_INS_PHA = 48
MOS65XX_INS_PHB = 49
MOS65XX_INS_PHD = 50
MOS65XX_INS_PHK = 51
MOS65XX_INS_PHP = 52
MOS65XX_INS_PHX = 53
MOS65XX_INS_PHY = 54
MOS65XX_INS_PLA = 55
MOS65XX_INS_PLB = 56
MOS65XX_INS_PLD = 57
MOS65XX_INS_PLP = 58
MOS65XX_INS_PLX = 59
MOS65XX_INS_PLY = 60
MOS65XX_INS_REP = 61
MOS65XX_INS_RMB = 62
MOS65XX_INS_ROL = 63
MOS65XX_INS_ROR = 64
MOS65XX_INS_RTI = 65
MOS65XX_INS_RTL = 66
MOS65XX_INS_RTS = 67
MOS65XX_INS_SBC = 68
MOS65XX_INS_SEC = 69
MOS65XX_INS_SED = 70
MOS65XX_INS_SEI = 71
MOS65XX_INS_SEP = 72
MOS65XX_INS_SMB = 73
MOS65XX_INS_STA = 74
MOS65XX_INS_STP = 75
MOS65XX_INS_STX = 76
MOS65XX_INS_STY = 77
MOS65XX_INS_STZ = 78
MOS65XX_INS_TAX = 79
MOS65XX_INS_TAY = 80
MOS65XX_INS_TCD = 81
MOS65XX_INS_TCS = 82
MOS65XX_INS_TDC = 83
MOS65XX_INS_TRB = 84
MOS65XX_INS_TSB = 85
MOS65XX_INS_TSC = 86
MOS65XX_INS_TSX = 87
MOS65XX_INS_TXA = 88
MOS65XX_INS_TXS = 89
MOS65XX_INS_TXY = 90
MOS65XX_INS_TYA = 91
MOS65XX_INS_TYX = 92
MOS65XX_INS_WAI = 93
MOS65XX_INS_WDM = 94
MOS65XX_INS_XBA = 95
MOS65XX_INS_XCE = 96
MOS65XX_INS_ENDING = 97
MOS65XX_GRP_INVALID = 0
MOS65XX_GRP_JUMP = 1
MOS65XX_GRP_CALL = 2
MOS65XX_GRP_RET = 3
MOS65XX_GRP_INT = 4
MOS65XX_GRP_IRET = 5
MOS65XX_GRP_BRANCH_RELATIVE = 6
MOS65XX_GRP_ENDING = 7

40
bindings/python/test_mos65xx.py
View File

@ -9,20 +9,32 @@ from xprint import to_hex, to_x
MOS65XX_CODE = b"\x0d\x34\x12\x00\x81\x65\x6c\x01\x00\x85\xFF\x10\x00\x19\x42\x42\x00\x49\x42"
address_modes=[
'No address mode',
'implied addressing (no addressing mode)',
'accumulator addressing',
'absolute addressing',
'zeropage addressing',
'8 Bit immediate value',
'indexed absolute addressing by the X index register',
'indexed absolute addressing by the Y index register',
'indexed indirect addressing by the X index register',
'indirect indexed addressing by the Y index register',
'indexed zeropage addressing by the X index register',
'indexed zeropage addressing by the Y index register',
'relative addressing used by branches',
'absolute indirect addressing'
"No address mode",
"implied",
"accumulator",
"immediate value",
"relative",
"interrupt signature",
"block move",
"zero page",
"zero page indexed with x",
"zero page indexed with y",
"relative bit branch",
"zero page indirect",
"zero page indexed with x indirect",
"zero page indirect indexed with y",
"zero page indirect long",
"zero page indirect long indexed with y",
"absolute",
"absolute indexed with x",
"absolute indexed with y",
"absolute indirect",
"absolute indexed with x indirect",
"absolute indirect long",
"absolute long",
"absolute long indexed with x",
"stack relative",
"stack relative indirect indexed with y",
];

3
cs.c
View File

@ -197,7 +197,8 @@ static struct {
{
MOS65XX_global_init,
MOS65XX_option,
~(CS_MODE_BIG_ENDIAN),
~(CS_MODE_LITTLE_ENDIAN | CS_MODE_MOS65XX_6502 | CS_MODE_MOS65XX_65C02
| CS_MODE_MOS65XX_W65C02 | CS_MODE_MOS65XX_65816_LONG_MX),
},
#else
{ NULL, NULL, 0 },

10
cstool/cstool.c
View File

@ -75,13 +75,16 @@ static struct {
{ "hcs08", CS_ARCH_M680X, CS_MODE_M680X_HCS08 },
{ "evm", CS_ARCH_EVM, 0 },
{ "wasm", CS_ARCH_WASM, 0 },
{ "mos65xx", CS_ARCH_MOS65XX, 0 },
{ "bpf", CS_ARCH_BPF, CS_MODE_LITTLE_ENDIAN | CS_MODE_BPF_CLASSIC },
{ "bpfbe", CS_ARCH_BPF, CS_MODE_BIG_ENDIAN | CS_MODE_BPF_CLASSIC },
{ "ebpf", CS_ARCH_BPF, CS_MODE_LITTLE_ENDIAN | CS_MODE_BPF_EXTENDED },
{ "ebpfbe", CS_ARCH_BPF, CS_MODE_BIG_ENDIAN | CS_MODE_BPF_EXTENDED },
{ "riscv32", CS_ARCH_RISCV, CS_MODE_RISCV32 },
{ "riscv64", CS_ARCH_RISCV, CS_MODE_RISCV64 },
{ "6502", CS_ARCH_MOS65XX, CS_MODE_MOS65XX_6502 },
{ "65c02", CS_ARCH_MOS65XX, CS_MODE_MOS65XX_65C02 },
{ "w65c02", CS_ARCH_MOS65XX, CS_MODE_MOS65XX_W65C02 },
{ "65816", CS_ARCH_MOS65XX, CS_MODE_MOS65XX_65816_LONG_MX },
{ NULL }
};
@ -249,7 +252,10 @@ static void usage(char *prog)
}
if (cs_support(CS_ARCH_MOS65XX)) {
printf(" mos65xx MOS65XX family\n");
printf(" 6502 MOS 6502\n");
printf(" 65c02 WDC 65c02\n");
printf(" w65c02 WDC w65c02\n");
printf(" 65816 WDC 65816 (long m/x)\n");
}
if (cs_support(CS_ARCH_WASM)) {

68
cstool/cstool_mos65xx.c
View File

@ -13,31 +13,55 @@ static const char *get_am_name(mos65xx_address_mode mode)
case MOS65XX_AM_NONE:
return "No address mode";
case MOS65XX_AM_IMP:
return "implied addressing (no addressing mode)";
return "implied";
case MOS65XX_AM_ACC:
return "accumulator addressing";
case MOS65XX_AM_ABS:
return "absolute addressing";
case MOS65XX_AM_ZP:
return "zeropage addressing";
return "accumulator";
case MOS65XX_AM_IMM:
return "8 Bit immediate value";
case MOS65XX_AM_ABSX:
return "indexed absolute addressing by the X index register";
case MOS65XX_AM_ABSY:
return "indexed absolute addressing by the Y index register";
case MOS65XX_AM_INDX:
return "indexed indirect addressing by the X index register";
case MOS65XX_AM_INDY:
return "indirect indexed addressing by the Y index register";
case MOS65XX_AM_ZPX:
return "indexed zeropage addressing by the X index register";
case MOS65XX_AM_ZPY:
return "indexed zeropage addressing by the Y index register";
return "immediate value";
case MOS65XX_AM_REL:
return "relative addressing used by branches";
case MOS65XX_AM_IND:
return "absolute indirect addressing";
return "relative";
case MOS65XX_AM_INT:
return "interrupt signature";
case MOS65XX_AM_BLOCK:
return "block move";
case MOS65XX_AM_ZP:
return "zero page";
case MOS65XX_AM_ZP_X:
return "zero page indexed with x";
case MOS65XX_AM_ZP_Y:
return "zero page indexed with y";
case MOS65XX_AM_ZP_REL:
return "relative bit branch";
case MOS65XX_AM_ZP_IND:
return "zero page indirect";
case MOS65XX_AM_ZP_X_IND:
return "zero page indexed with x indirect";
case MOS65XX_AM_ZP_IND_Y:
return "zero page indirect indexed with y";
case MOS65XX_AM_ZP_IND_LONG:
return "zero page indirect long";
case MOS65XX_AM_ZP_IND_LONG_Y:
return "zero page indirect long indexed with y";
case MOS65XX_AM_ABS:
return "absolute";
case MOS65XX_AM_ABS_X:
return "absolute indexed with x";
case MOS65XX_AM_ABS_Y:
return "absolute indexed with y";
case MOS65XX_AM_ABS_IND:
return "absolute indirect";
case MOS65XX_AM_ABS_X_IND:
return "absolute indexed with x indirect";
case MOS65XX_AM_ABS_IND_LONG:
return "absolute indirect long";
case MOS65XX_AM_ABS_LONG:
return "absolute long";
case MOS65XX_AM_ABS_LONG_X:
return "absolute long indexed with x";
case MOS65XX_AM_SR:
return "stack relative";
case MOS65XX_AM_SR_IND_Y:
return "stack relative indirect indexed with y";
}
}

8
include/capstone/capstone.h
View File

@ -145,6 +145,13 @@ typedef enum cs_mode {
CS_MODE_RISCV32 = 1 << 0, ///< RISCV RV32G
CS_MODE_RISCV64 = 1 << 1, ///< RISCV RV64G
CS_MODE_RISCVC = 1 << 2, ///< RISCV compressed instructure mode
CS_MODE_MOS65XX_6502 = 1 << 1, ///< MOS65XXX MOS 6502
CS_MODE_MOS65XX_65C02 = 1 << 2, ///< MOS65XXX WDC 65c02
CS_MODE_MOS65XX_W65C02 = 1 << 3, ///< MOS65XXX WDC W65c02
CS_MODE_MOS65XX_65816 = 1 << 4, ///< MOS65XXX WDC 65816, 8-bit m/x
CS_MODE_MOS65XX_65816_LONG_M = (1 << 5), ///< MOS65XXX WDC 65816, 16-bit m, 8-bit x
CS_MODE_MOS65XX_65816_LONG_X = (1 << 6), ///< MOS65XXX WDC 65816, 8-bit m, 16-bit x
CS_MODE_MOS65XX_65816_LONG_MX = CS_MODE_MOS65XX_65816_LONG_M | CS_MODE_MOS65XX_65816_LONG_X,
} cs_mode;
typedef void* (CAPSTONE_API *cs_malloc_t)(size_t size);
@ -197,6 +204,7 @@ typedef enum cs_opt_value {
CS_OPT_SYNTAX_ATT, ///< X86 ATT asm syntax (CS_OPT_SYNTAX).
CS_OPT_SYNTAX_NOREGNAME, ///< Prints register name with only number (CS_OPT_SYNTAX)
CS_OPT_SYNTAX_MASM, ///< X86 Intel Masm syntax (CS_OPT_SYNTAX).
CS_OPT_SYNTAX_MOTOROLA, ///< MOS65XX use $ as hex prefix
} cs_opt_value;
/// Common instruction operand types - to be consistent across all architectures.

82
include/capstone/mos65xx.h
View File

@ -18,6 +18,9 @@ typedef enum mos65xx_reg {
MOS65XX_REG_Y, ///< Y index register
MOS65XX_REG_P, ///< status register
MOS65XX_REG_SP, ///< stack pointer register
MOS65XX_REG_DP, ///< direct page register
MOS65XX_REG_B, ///< data bank register
MOS65XX_REG_K, ///< program bank register
MOS65XX_REG_ENDING, // <-- mark the end of the list of registers
} mos65xx_reg;
@ -26,17 +29,29 @@ typedef enum mos65xx_address_mode {
MOS65XX_AM_NONE = 0, ///< No address mode.
MOS65XX_AM_IMP, ///< implied addressing (no addressing mode)
MOS65XX_AM_ACC, ///< accumulator addressing
MOS65XX_AM_ABS, ///< absolute addressing
MOS65XX_AM_ZP, ///< zeropage addressing
MOS65XX_AM_IMM, ///< 8 Bit immediate value
MOS65XX_AM_ABSX, ///< indexed absolute addressing by the X index register
MOS65XX_AM_ABSY, ///< indexed absolute addressing by the Y index register
MOS65XX_AM_INDX, ///< indexed indirect addressing by the X index register
MOS65XX_AM_INDY, ///< indirect indexed addressing by the Y index register
MOS65XX_AM_ZPX, ///< indexed zeropage addressing by the X index register
MOS65XX_AM_ZPY, ///< indexed zeropage addressing by the Y index register
MOS65XX_AM_IMM, ///< 8/16 Bit immediate value
MOS65XX_AM_REL, ///< relative addressing used by branches
MOS65XX_AM_IND, ///< absolute indirect addressing
MOS65XX_AM_INT, ///< interrupt addressing
MOS65XX_AM_BLOCK, ///< memory block addressing
MOS65XX_AM_ZP, ///< zeropage addressing
MOS65XX_AM_ZP_X, ///< indexed zeropage addressing by the X index register
MOS65XX_AM_ZP_Y, ///< indexed zeropage addressing by the Y index register
MOS65XX_AM_ZP_REL, ///< zero page address, branch relative address
MOS65XX_AM_ZP_IND, ///< indirect zeropage addressing
MOS65XX_AM_ZP_X_IND, ///< indexed zeropage indirect addressing by the X index register
MOS65XX_AM_ZP_IND_Y, ///< indirect zeropage indexed addressing by the Y index register
MOS65XX_AM_ZP_IND_LONG, ///< zeropage indirect long addressing
MOS65XX_AM_ZP_IND_LONG_Y, ///< zeropage indirect long addressing indexed by Y register
MOS65XX_AM_ABS, ///< absolute addressing
MOS65XX_AM_ABS_X, ///< indexed absolute addressing by the X index register
MOS65XX_AM_ABS_Y, ///< indexed absolute addressing by the Y index register
MOS65XX_AM_ABS_IND, ///< absolute indirect addressing
MOS65XX_AM_ABS_X_IND, ///< indexed absolute indirect addressing by the X index register
MOS65XX_AM_ABS_IND_LONG, ///< absolute indirect long addressing
MOS65XX_AM_ABS_LONG, ///< absolute long address mode
MOS65XX_AM_ABS_LONG_X, ///< absolute long address mode, indexed by X register
MOS65XX_AM_SR, ///< stack relative addressing
MOS65XX_AM_SR_IND_Y, ///< indirect stack relative addressing indexed by the Y index register
} mos65xx_address_mode;
/// MOS65XX instruction
@ -45,6 +60,8 @@ typedef enum mos65xx_insn {
MOS65XX_INS_ADC,
MOS65XX_INS_AND,
MOS65XX_INS_ASL,
MOS65XX_INS_BBR,
MOS65XX_INS_BBS,
MOS65XX_INS_BCC,
MOS65XX_INS_BCS,
MOS65XX_INS_BEQ,
@ -52,7 +69,9 @@ typedef enum mos65xx_insn {
MOS65XX_INS_BMI,
MOS65XX_INS_BNE,
MOS65XX_INS_BPL,
MOS65XX_INS_BRA,
MOS65XX_INS_BRK,
MOS65XX_INS_BRL,
MOS65XX_INS_BVC,
MOS65XX_INS_BVS,
MOS65XX_INS_CLC,
@ -60,6 +79,7 @@ typedef enum mos65xx_insn {
MOS65XX_INS_CLI,
MOS65XX_INS_CLV,
MOS65XX_INS_CMP,
MOS65XX_INS_COP,
MOS65XX_INS_CPX,
MOS65XX_INS_CPY,
MOS65XX_INS_DEC,
@ -69,35 +89,70 @@ typedef enum mos65xx_insn {
MOS65XX_INS_INC,
MOS65XX_INS_INX,
MOS65XX_INS_INY,
MOS65XX_INS_JML,
MOS65XX_INS_JMP,
MOS65XX_INS_JSL,
MOS65XX_INS_JSR,
MOS65XX_INS_LDA,
MOS65XX_INS_LDX,
MOS65XX_INS_LDY,
MOS65XX_INS_LSR,
MOS65XX_INS_MVN,
MOS65XX_INS_MVP,
MOS65XX_INS_NOP,
MOS65XX_INS_ORA,
MOS65XX_INS_PEA,
MOS65XX_INS_PEI,
MOS65XX_INS_PER,
MOS65XX_INS_PHA,
MOS65XX_INS_PLA,
MOS65XX_INS_PHB,
MOS65XX_INS_PHD,
MOS65XX_INS_PHK,
MOS65XX_INS_PHP,
MOS65XX_INS_PHX,
MOS65XX_INS_PHY,
MOS65XX_INS_PLA,
MOS65XX_INS_PLB,
MOS65XX_INS_PLD,
MOS65XX_INS_PLP,
MOS65XX_INS_PLX,
MOS65XX_INS_PLY,
MOS65XX_INS_REP,
MOS65XX_INS_RMB,
MOS65XX_INS_ROL,
MOS65XX_INS_ROR,
MOS65XX_INS_RTI,
MOS65XX_INS_RTL,
MOS65XX_INS_RTS,
MOS65XX_INS_SBC,
MOS65XX_INS_SEC,
MOS65XX_INS_SED,
MOS65XX_INS_SEI,
MOS65XX_INS_SEP,
MOS65XX_INS_SMB,
MOS65XX_INS_STA,
MOS65XX_INS_STP,
MOS65XX_INS_STX,
MOS65XX_INS_STY,
MOS65XX_INS_STZ,
MOS65XX_INS_TAX,
MOS65XX_INS_TAY,
MOS65XX_INS_TCD,
MOS65XX_INS_TCS,
MOS65XX_INS_TDC,
MOS65XX_INS_TRB,
MOS65XX_INS_TSB,
MOS65XX_INS_TSC,
MOS65XX_INS_TSX,
MOS65XX_INS_TXA,
MOS65XX_INS_TXS,
MOS65XX_INS_TXY,
MOS65XX_INS_TYA,
MOS65XX_INS_TYX,
MOS65XX_INS_WAI,
MOS65XX_INS_WDM,
MOS65XX_INS_XBA,
MOS65XX_INS_XCE,
MOS65XX_INS_ENDING, // <-- mark the end of the list of instructions
} mos65xx_insn;
@ -107,6 +162,7 @@ typedef enum mos65xx_group_type {
MOS65XX_GRP_JUMP, ///< = CS_GRP_JUMP
MOS65XX_GRP_CALL, ///< = CS_GRP_RET
MOS65XX_GRP_RET, ///< = CS_GRP_RET
MOS65XX_GRP_INT, ///< = CS_GRP_INT
MOS65XX_GRP_IRET = 5, ///< = CS_GRP_IRET
MOS65XX_GRP_BRANCH_RELATIVE = 6, ///< = CS_GRP_BRANCH_RELATIVE
MOS65XX_GRP_ENDING,// <-- mark the end of the list of groups
@ -125,8 +181,8 @@ typedef struct cs_mos65xx_op {
mos65xx_op_type type; ///< operand type
union {
mos65xx_reg reg; ///< register value for REG operand
uint8_t imm; ///< immediate value for IMM operand
uint16_t mem; ///< base/index/scale/disp value for MEM operand
uint16_t imm; ///< immediate value for IMM operand
uint32_t mem; ///< base/index/scale/disp value for MEM operand
};
} cs_mos65xx_op;

68
suite/cstest/src/mos65xx_detail.c
View File

@ -11,31 +11,55 @@ static const char *get_am_name(mos65xx_address_mode mode)
case MOS65XX_AM_NONE:
return "No address mode";
case MOS65XX_AM_IMP:
return "implied addressing (no addressing mode)";
return "implied";
case MOS65XX_AM_ACC:
return "accumulator addressing";
case MOS65XX_AM_ABS:
return "absolute addressing";
case MOS65XX_AM_ZP:
return "zeropage addressing";
return "accumulator";
case MOS65XX_AM_IMM:
return "8 Bit immediate value";
case MOS65XX_AM_ABSX:
return "indexed absolute addressing by the X index register";
case MOS65XX_AM_ABSY:
return "indexed absolute addressing by the Y index register";
case MOS65XX_AM_INDX:
return "indexed indirect addressing by the X index register";
case MOS65XX_AM_INDY:
return "indirect indexed addressing by the Y index register";
case MOS65XX_AM_ZPX:
return "indexed zeropage addressing by the X index register";
case MOS65XX_AM_ZPY:
return "indexed zeropage addressing by the Y index register";
return "immediate value";
case MOS65XX_AM_REL:
return "relative addressing used by branches";
case MOS65XX_AM_IND:
return "absolute indirect addressing";
return "relative";
case MOS65XX_AM_INT:
return "interrupt signature";
case MOS65XX_AM_BLOCK:
return "block move";
case MOS65XX_AM_ZP:
return "zero page";
case MOS65XX_AM_ZP_X:
return "zero page indexed with x";
case MOS65XX_AM_ZP_Y:
return "zero page indexed with y";
case MOS65XX_AM_ZP_REL:
return "relative bit branch";
case MOS65XX_AM_ZP_IND:
return "zero page indirect";
case MOS65XX_AM_ZP_X_IND:
return "zero page indexed with x indirect";
case MOS65XX_AM_ZP_IND_Y:
return "zero page indirect indexed with y";
case MOS65XX_AM_ZP_IND_LONG:
return "zero page indirect long";
case MOS65XX_AM_ZP_IND_LONG_Y:
return "zero page indirect long indexed with y";
case MOS65XX_AM_ABS:
return "absolute";
case MOS65XX_AM_ABS_X:
return "absolute indexed with x";
case MOS65XX_AM_ABS_Y:
return "absolute indexed with y";
case MOS65XX_AM_ABS_IND:
return "absolute indirect";
case MOS65XX_AM_ABS_X_IND:
return "absolute indexed with x indirect";
case MOS65XX_AM_ABS_IND_LONG:
return "absolute indirect long";
case MOS65XX_AM_ABS_LONG:
return "absolute long";
case MOS65XX_AM_ABS_LONG_X:
return "absolute long indexed with x";
case MOS65XX_AM_SR:
return "stack relative";
case MOS65XX_AM_SR_IND_Y:
return "stack relative indirect indexed with y";
}
}

117
tests/test_mos65xx.c
View File

@ -36,31 +36,55 @@ static const char *get_am_name(mos65xx_address_mode mode)
case MOS65XX_AM_NONE:
return "No address mode";
case MOS65XX_AM_IMP:
return "implied addressing (no addressing mode)";
return "implied";
case MOS65XX_AM_ACC:
return "accumulator addressing";
case MOS65XX_AM_ABS:
return "absolute addressing";
case MOS65XX_AM_ZP:
return "zeropage addressing";
return "accumulator";
case MOS65XX_AM_IMM:
return "8 Bit immediate value";
case MOS65XX_AM_ABSX:
return "indexed absolute addressing by the X index register";
case MOS65XX_AM_ABSY:
return "indexed absolute addressing by the Y index register";
case MOS65XX_AM_INDX:
return "indexed indirect addressing by the X index register";
case MOS65XX_AM_INDY:
return "indirect indexed addressing by the Y index register";
case MOS65XX_AM_ZPX:
return "indexed zeropage addressing by the X index register";
case MOS65XX_AM_ZPY:
return "indexed zeropage addressing by the Y index register";
return "immediate value";
case MOS65XX_AM_REL:
return "relative addressing used by branches";
case MOS65XX_AM_IND:
return "absolute indirect addressing";
return "relative";
case MOS65XX_AM_INT:
return "interrupt signature";
case MOS65XX_AM_BLOCK:
return "block move";
case MOS65XX_AM_ZP:
return "zero page";
case MOS65XX_AM_ZP_X:
return "zero page indexed with x";
case MOS65XX_AM_ZP_Y:
return "zero page indexed with y";
case MOS65XX_AM_ZP_REL:
return "relative bit branch";
case MOS65XX_AM_ZP_IND:
return "zero page indirect";
case MOS65XX_AM_ZP_X_IND:
return "zero page indexed with x indirect";
case MOS65XX_AM_ZP_IND_Y:
return "zero page indirect indexed with y";
case MOS65XX_AM_ZP_IND_LONG:
return "zero page indirect long";
case MOS65XX_AM_ZP_IND_LONG_Y:
return "zero page indirect long indexed with y";
case MOS65XX_AM_ABS:
return "absolute";
case MOS65XX_AM_ABS_X:
return "absolute indexed with x";
case MOS65XX_AM_ABS_Y:
return "absolute indexed with y";
case MOS65XX_AM_ABS_IND:
return "absolute indirect";
case MOS65XX_AM_ABS_X_IND:
return "absolute indexed with x indirect";
case MOS65XX_AM_ABS_IND_LONG:
return "absolute indirect long";
case MOS65XX_AM_ABS_LONG:
return "absolute long";
case MOS65XX_AM_ABS_LONG_X:
return "absolute long indexed with x";
case MOS65XX_AM_SR:
return "stack relative";
case MOS65XX_AM_SR_IND_Y:
return "stack relative indirect indexed with y";
}
}
@ -103,15 +127,51 @@ static void print_insn_detail(cs_insn *ins)
static void test()
{
#define MOS65XX_CODE "\x0d\x34\x12\x00\x81\x87\x6c\x01\x00\x85\xFF\x10\x00\x19\x42\x42\x00\x49\x42"
#define M6502_CODE "\xa1\x12\xa5\x12\xa9\x12\xad\x34\x12\xb1\x12\xb5\x12\xb9\x34\x12\xbd\x34\x12" \
"\x0d\x34\x12\x00\x81\x87\x6c\x01\x00\x85\xFF\x10\x00\x19\x42\x42\x00\x49\x42"
#define M65C02_CODE "\x1a\x3a" \
"\x02\x12\x03\x5c\x34\x12"
#define MW65C02_CODE \
"\x07\x12\x27\x12\x47\x12\x67\x12\x87\x12\xa7\x12\xc7\x12\xe7\x12" \
"\x0f\x12\xfd\x4f\x12\xfd\x8f\x12\xfd\xcf\x12\xfd"
#define M65816_CODE \
"\xa9\x34\x12" "\xad\x34\x12" "\xbd\x34\x12" "\xb9\x34\x12" \
"\xaf\x56\x34\x12" "\xbf\x56\x34\x12" \
"\xa5\x12" "\xb5\x12" "\xb2\x12" "\xa1\x12" "\xb1\x12" "\xa7\x12" "\xb7\x12" \
"\xa3\x12" "\xb3\x12" \
"\xc2\x00" "\xe2\x00" "\x54\x34\x12" "\x44\x34\x12" "\x02\x12"
struct platform platforms[] = {
{
CS_ARCH_MOS65XX,
0,
(unsigned char *)MOS65XX_CODE,
sizeof(MOS65XX_CODE) - 1,
"MOS65XX"
(cs_mode)(CS_MODE_MOS65XX_6502),
(unsigned char *)M6502_CODE,
sizeof(M6502_CODE) - 1,
"MOS65XX_6502"
},
{
CS_ARCH_MOS65XX,
(cs_mode)(CS_MODE_MOS65XX_65C02),
(unsigned char *)M65C02_CODE,
sizeof(M65C02_CODE) - 1,
"MOS65XX_65C02"
},
{
CS_ARCH_MOS65XX,
(cs_mode)(CS_MODE_MOS65XX_W65C02),
(unsigned char *)MW65C02_CODE,
sizeof(MW65C02_CODE) - 1,
"MOS65XX_W65C02"
},
{
CS_ARCH_MOS65XX,
(cs_mode)(CS_MODE_MOS65XX_65816_LONG_MX),
(unsigned char *)M65816_CODE,
sizeof(M65816_CODE) - 1,
"MOS65XX_65816 (long m/x)"
},
};
@ -123,11 +183,12 @@ static void test()
for (i = 0; i < sizeof(platforms)/sizeof(platforms[0]); i++) {
cs_err err = cs_open(platforms[i].arch, platforms[i].mode, &handle);
if (err) {
printf("Failed on cs_open() with error returned: %u\n", err);
printf("Failed on cs_open() with error returned: %u (%s)\n", err, cs_strerror(err));
abort();
}
cs_option(handle, CS_OPT_DETAIL, CS_OPT_ON);
cs_option(handle, CS_OPT_SYNTAX, CS_OPT_SYNTAX_MOTOROLA);
count = cs_disasm(handle, platforms[i].code, platforms[i].size, address, 0, &insn);