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x86: bug fixes for some instructions, including AVX

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This commit is contained in:
Nguyen Anh Quynh 2014-02-25 14:43:30 +08:00
parent 1cbe4c66a3
commit 079e0430b6
2 changed files with 17 additions and 10 deletions
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19
arch/X86/X86DisassemblerDecoder.c
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@ -149,7 +149,7 @@ static InstrUID decode(OpcodeType type,
indextable = index_x86DisassemblerTwoByteOpcodes;
index = indextable[insnContext];
if (index)
dec = &TWOBYTE_SYM[indextable[insnContext]].modRMDecisions[opcode];
dec = &TWOBYTE_SYM[index - 1].modRMDecisions[opcode];
else
dec = &emptyTable.modRMDecisions[opcode];
break;
@ -157,7 +157,7 @@ static InstrUID decode(OpcodeType type,
indextable = index_x86DisassemblerThreeByte38Opcodes;
index = indextable[insnContext];
if (index)
dec = &THREEBYTE38_SYM[indextable[insnContext]].modRMDecisions[opcode];
dec = &THREEBYTE38_SYM[index - 1].modRMDecisions[opcode];
else
dec = &emptyTable.modRMDecisions[opcode];
break;
@ -165,7 +165,7 @@ static InstrUID decode(OpcodeType type,
indextable = index_x86DisassemblerThreeByte3AOpcodes;
index = indextable[insnContext];
if (index)
dec = &THREEBYTE3A_SYM[indextable[insnContext]].modRMDecisions[opcode];
dec = &THREEBYTE3A_SYM[index - 1].modRMDecisions[opcode];
else
dec = &emptyTable.modRMDecisions[opcode];
break;
@ -173,7 +173,7 @@ static InstrUID decode(OpcodeType type,
indextable = index_x86DisassemblerXOP8Opcodes;
index = indextable[insnContext];
if (index)
dec = &XOP8_MAP_SYM[indextable[insnContext]].modRMDecisions[opcode];
dec = &XOP8_MAP_SYM[index - 1].modRMDecisions[opcode];
else
dec = &emptyTable.modRMDecisions[opcode];
break;
@ -181,7 +181,7 @@ static InstrUID decode(OpcodeType type,
indextable = index_x86DisassemblerXOP9Opcodes;
index = indextable[insnContext];
if (index)
dec = &XOP9_MAP_SYM[indextable[insnContext]].modRMDecisions[opcode];
dec = &XOP9_MAP_SYM[index - 1].modRMDecisions[opcode];
else
dec = &emptyTable.modRMDecisions[opcode];
break;
@ -189,7 +189,7 @@ static InstrUID decode(OpcodeType type,
indextable = index_x86DisassemblerXOPAOpcodes;
index = indextable[insnContext];
if (index)
dec = &XOPA_MAP_SYM[indextable[insnContext]].modRMDecisions[opcode];
dec = &XOPA_MAP_SYM[index - 1].modRMDecisions[opcode];
else
dec = &emptyTable.modRMDecisions[opcode];
break;
@ -694,6 +694,11 @@ static int readPrefixes(struct InternalInstruction* insn)
insn->addressSize = (hasAdSize ? 4 : 8);
insn->displacementSize = 4;
insn->immediateSize = 4;
} else if (insn->rexPrefix) {
insn->registerSize = (hasOpSize ? 2 : 4);
insn->addressSize = (hasAdSize ? 4 : 8);
insn->displacementSize = (hasOpSize ? 2 : 4);
insn->immediateSize = (hasOpSize ? 2 : 4);
} else {
insn->registerSize = (hasOpSize ? 2 : 4);
insn->addressSize = (hasAdSize ? 4 : 8);
@ -1203,6 +1208,7 @@ static int readSIB(struct InternalInstruction* insn)
base = baseFromSIB(insn->sib) | (bFromREX(insn->rexPrefix) << 3);
switch (base) {
case 0x5:
case 0xd:
switch (modFromModRM(insn->modRM)) {
case 0x0:
@ -1392,6 +1398,7 @@ static int readModRM(struct InternalInstruction* insn)
insn->eaBase = (EABase)(insn->eaBaseBase + rm);
break;
}
break;
case 0x1:
insn->displacementSize = 1;

8
config.mk
View File

@ -4,16 +4,16 @@
CAPSTONE_ARCHS =
# Comment out the line below if you don't want to support ARM
#CAPSTONE_ARCHS += arm
CAPSTONE_ARCHS += arm
# Comment out the line below if you don't want to support ARM64
#CAPSTONE_ARCHS += aarch64
CAPSTONE_ARCHS += aarch64
# Comment out the line below if you don't want to support Mips
#CAPSTONE_ARCHS += mips
CAPSTONE_ARCHS += mips
# Comment out the line below if you don't want to support PowerPC
#CAPSTONE_ARCHS += powerpc
CAPSTONE_ARCHS += powerpc
# Comment out the line below if you don't want to support Intel (16/32/64-bit)
CAPSTONE_ARCHS += x86