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refactor: Improve TriCore instruction definitions in architecture file
- Refactor architecture specific code for TriCore - Update TriCore instruction information in [arch/TriCore/TriCoreInstrInfo.td] - Improve performance and readability of relevant functions
This commit is contained in:
billow
parent
07065c525b
commit
0b4546820e
@ -257,14 +257,6 @@ multiclass mISRC_a15a<bits<8> op1, bits<8> op2, bits<8> op3,
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def _src_15a : ISRC_D15dC<op3, asmstr>;
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}
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class ISRRS_AcAbD15N<bits<6> op1, string asmstr>
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: SRRS<op1, (outs RA:$d), (ins RA:$s2, u2imm:$n),
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asmstr # " $d, $s2, %d15, $n", []>;
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class ISRRS_AcDbN<bits<6> op1, string asmstr>
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: SRRS<op1, (outs RA:$d), (ins RD:$s2, u2imm:$n),
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asmstr # " $d, $s2, $n", []>;
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/// 32-Bit Opcode Formats
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/// RC
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@ -273,13 +265,10 @@ class IRC_C<bits<8> op1, bits<7> op2, string asmstr>
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: RC<op1, op2, (outs), (ins s9imm:$const9),
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asmstr # " $const9", []>;
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class IRC_RcDaC<bits<8> op1, bits<7> op2, string asmstr, RegisterClass rcd>
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: RC<op1, op2, (outs rcd:$d), (ins RD:$s1, s9imm:$const9),
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class IRC<bits<8> op1, bits<7> op2, string asmstr, RegisterClass RCd=RD, RegisterClass RC1=RD>
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: RC<op1, op2, (outs RCd:$d), (ins RC1:$s1, s9imm:$const9),
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asmstr # " $d, $s1, $const9", []>;
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class IRC_DcDaC<bits<8> op1, bits<7> op2, string asmstr>
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: IRC_RcDaC<op1, op2, asmstr, RD>;
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/// RR
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class IRR_Ra<bits<8> op1, bits<8> op2, string asmstr, RegisterClass rc=RD>
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@ -314,7 +303,7 @@ class IRR_dba<bits<8> op1, bits<8> op2, string asmstr,
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multiclass mIRR_RC<bits<8> rr1, bits<8> rr2, bits<8> rc1, bits<7> rc2, string asmstr> {
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def _rr : IRR_dab<rr1, rr2, asmstr>;
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def _rc : IRC_DcDaC<rc1, rc2, asmstr>;
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def _rc : IRC<rc1, rc2, asmstr>;
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}
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class IRLC<bits<8> op1, string asmstr>
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@ -471,8 +460,10 @@ multiclass mIH_HU_U<bits<8> h1, bits<8> h2,
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defm ADDS : mIRR_RC<0x0B, 0x02, 0x8B, 0x02, "adds">,
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mISRR_s<0x22, "adds">,
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mIH_HU_U<0x0B, 0x62, 0x0B, 0x63, 0x0B, 0x03, "adds">;
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def ADDS_U_rc : IRC_DcDaC<0x8B, 0x03, "adds.u">;
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def ADDSC_A_srrs : ISRRS_AcAbD15N<0x10, "addsc.a">, Requires<[HasV120_UP]>;
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def ADDS_U_rc : IRC<0x8B, 0x03, "adds.u">;
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def ADDSC_A_srrs: SRRS<0x10, (outs RA:$d), (ins RA:$s2, u2imm:$n),
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"addsc.a $d, $s2, %d15, $n", []>
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, Requires<[HasV120_UP]>;
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def ADDSC_A_rr : RR<0x01, 0x60, (outs RA:$d), (ins RD:$s1, RA:$s2, i32imm:$n),
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"addsc.a $d, $s2, $s1, $n", []>,
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Requires<[HasV120_UP]>;
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@ -482,7 +473,9 @@ def ADDSC_AT_rr : IRR_2<0x01, 0x62, "addsc.at %d, %s2, %s1", RA, RA, RD>
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let DecoderNamespace = "v110" in {
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def ADDS_B_rr_v110 : IRR_dab<0x0B, 0x42, "adds.b">, Requires<[HasV110]>;
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def ADDS_BU_rr_v110 : IRR_dab<0x0B, 0x43, "adds.bu">, Requires<[HasV110]>;
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def ADDSC_A_srrs_v110 : ISRRS_AcDbN<0x10, "addsc.a">, Requires<[HasV110]>;
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def ADDSC_A_srrs_v110 : SRRS<0x10, (outs RA:$d), (ins RD:$s2, u2imm:$n),
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"addsc.a $d, $s2, $n", []>
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, Requires<[HasV110]>;
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def ADDSC_A_rr_v110 : RR<0x01, 0x60, (outs RA:$d), (ins RD:$s1, RA:$s2, i32imm:$n),
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"addsc.a $d, $s1, $s2, $n", []>
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, Requires<[HasV110]>;
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@ -634,22 +627,20 @@ defm CACHEI_WI : mIBO_a<0x89, 0x2F,
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/// RRR Opcodes Formats
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// Dc Dd Da Db
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class IRRR_DcDdDaDb<bits<8>op1, bits<4> op2, string asmstr>
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: RRR<op1, op2, (outs RD:$d), (ins RD:$s1, RD:$s2, RD:$s3),
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class IRRR<bits<8>op1, bits<4> op2, string asmstr,
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RegisterClass RCd=RD, RegisterClass RC3=RD, RegisterClass RC1=RD, RegisterClass RC2=RD>
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: RRR<op1, op2, (outs RCd:$d), (ins RC1:$s1, RC2:$s2, RC3:$s3),
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asmstr # " $d, $s3, $s1, $s2", []>;
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// Dc Dd Da
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class IRRR_DcDdDa<bits<8>op1, bits<4> op2, string asmstr>
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: RRR<op1, op2, (outs RD:$d), (ins RD:$s1, RD:$s3),
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asmstr # " $d, $s3, $s1", []>;
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// Ec Ed Db
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class IRRR_EcEdEb<bits<8>op1, bits<4> op2, string asmstr>
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: RRR<op1, op2, (outs RE:$d), (ins RD:$s2, RE:$s3),
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class IRRR_d31<bits<8>op1, bits<4> op2, string asmstr,
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RegisterClass RCd=RD, RegisterClass RC3=RD, RegisterClass RC1=RD>
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: RRR<op1, op2, (outs RCd:$d), (ins RC1:$s1, RC3:$s3), asmstr # " $d, $s3, $s1", []>;
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class IRRR_d32<bits<8>op1, bits<4> op2, string asmstr,
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RegisterClass RCd=RD, RegisterClass RC3=RD, RegisterClass RC2=RD>
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: RRR<op1, op2, (outs RCd:$d), (ins RC2:$s2, RC3:$s3),
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asmstr # " $d, $s3, $s2", []>;
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// Dc Ed Da
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class IRRR_DcEdDa<bits<8>op1, bits<4> op2, string asmstr>
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: RRR<op1, op2, (outs RD:$d), (ins RD:$s1, RE:$s3),
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asmstr # " $d, $s3, $s1", []>;
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/// RCR Opcodes Formats
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class IRCR<bits<8> op1, bits<3> op2, string asmstr,
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@ -666,7 +657,7 @@ multiclass mIRCR<bits<8>op1, bits<3> op2, bits<8>op3, bits<3> op4, string asmstr
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def CADD_srr_v110 : ISRR_dD15b<0x0A, "cadd">, NsRequires<[HasV110]>;
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def CADD_rcr : IRCR<0xAB, 0x00, "cadd">;
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def CADD_rrr : IRRR_DcDdDaDb<0x2B, 0x00, "cadd">;
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def CADD_rrr : IRRR<0x2B, 0x00, "cadd">;
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def CADD_src : ISRC_dD15C<0x8A, "cadd", RA>;
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def CADD_A_rrr_v110 : RRR<0x21, 0x00, (outs RA:$d), (ins RD:$s1, RA:$s2, RA:$s3), "cadd.a $d $s3, $s1, $s2", []>
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@ -677,7 +668,7 @@ def CADDN_srr_v110 : ISRR_dD15b<0x4A, "caddn">
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, NsRequires<[HasV110]>;
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def CADDN_rcr : IRCR<0xAB, 0x01, "caddn">;
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def CADDN_rrr : IRRR_DcDdDaDb<0x2B, 0x01, "caddn">;
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def CADDN_rrr : IRRR<0x2B, 0x01, "caddn">;
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def CADDN_src : ISRC_dD15C<0xCA, "caddn", RA>;
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def CADDN_A_rrr_v110 : RRR<0x21, 0x01, (outs RA:$d), (ins RD:$s1, RA:$s2, RA:$s3), "caddn.a $d $s3, $s1, $s2", []>
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@ -774,10 +765,10 @@ defm CMPSWAP_W : mIBO_Ea<0x49, 0x23, 0x69, 0x03,
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def CRC32_B_rr : IRR_dba<0x4B, 0x06, "crc32.b">;
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def CRC32B_W_rr : IRR_dba<0x4B, 0x03, "crc32b.w">;
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def CRC32L_W_rr : IRR_dba<0x4B, 0x07, "crc32l.w">;
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def CRCN_rrr : IRRR_DcDdDaDb<0x6B, 0x01, "crcn">;
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def CRCN_rrr : IRRR<0x6B, 0x01, "crcn">;
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def CSUB_rrr : IRRR_DcDdDaDb<0x2B, 0x02, "csub">;
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def CSUBN_rrr : IRRR_DcDdDaDb<0x2B, 0x03, "csub">;
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def CSUB_rrr : IRRR<0x2B, 0x02, "csub">;
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def CSUBN_rrr : IRRR<0x2B, 0x03, "csub">;
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def CSUB_A_rrr_v110 : RRR<0x21, 0x02, (outs RA:$d), (ins RD:$s1, RA:$s2, RA:$s3), "csub.a $d, $s3, $s1, $s2", []>
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, NsRequires<[HasV110]>;
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@ -890,8 +881,8 @@ def DISABLE_sys_1 : ISYS_1<0x0D, 0x0F, "disable">, Requires<[HasV160_UP]>;
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def DSYNC_sys : ISYS_0<0x0D, 0x12, "dsync">;
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def DVADJ_srr_v110 : ISRR_db<0x72, "dvadj", RE, RD>, NsRequires<[HasV110]>;
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def DVADJ_rrr_v110 : IRRR_EcEdEb<0x2B, 0x08, "dvadj">, NsRequires<[HasV110]>;
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def DVADJ_rrr : IRRR_EcEdEb<0x6B, 0x0D, "dvadj">, Requires<[HasV160_UP]>;
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def DVADJ_rrr_v110 : IRRR_d32<0x2B, 0x08, "dvadj", RE, RE, RE>, NsRequires<[HasV110]>;
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def DVADJ_rrr : IRRR_d32<0x6B, 0x0D, "dvadj", RE, RE, RE>, Requires<[HasV160_UP]>;
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multiclass mI_U_RR_Eab<bits<8> op1, bits<8> op2, bits<8> op3, bits<8> op4,
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string asmstr, string posfix = ""> {
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@ -922,8 +913,8 @@ defm DVINIT : mI_DVINIT_<0x4B, 0x1A, 0x0A, 0x5A, 0x4A, 0x3A, 0x2A, "dvinit">, Re
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multiclass mI_U_RRR_EEdb<bits<8> op1, bits<4> op2, bits<8> op3, bits<4> op4,
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string asmstr, string posfix = ""> {
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def _rrr # posfix : IRRR_EcEdEb<op1, op2, asmstr>;
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def _U_rrr # posfix: IRRR_EcEdEb<op3, op4, asmstr # ".u">;
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def _rrr # posfix : IRRR_d32<op1, op2, asmstr, RE, RE, RE>;
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def _U_rrr # posfix: IRRR_d32<op3, op4, asmstr # ".u", RE, RE, RE>;
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}
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multiclass mI_U_SRR_sds2<bits<8> op1, bits<8> op2, string asmstr,
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@ -1507,26 +1498,24 @@ class IRLC_CR<bits<8> op1, string asmstr, RegisterClass rc=RD>
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def MTCR_rlc : IRLC_CR<0xCD, "mtcr">;
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def MFCR_rlc : IRLC_1 <0x4D, "mfcr">;
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class IRR2<bits<8> op1, bits<12> op2, string asmstr, RegisterClass rcd, RegisterClass rca, RegisterClass rcb>
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class IRR2<bits<8> op1, bits<12> op2, string asmstr,
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RegisterClass rcd=RD, RegisterClass rca=RD, RegisterClass rcb=RD>
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: RR2<op1, op2, (outs rcd:$d), (ins rca:$s1, rcb:$s2), asmstr # " $d, $s1, $s2", []>;
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class IRR2_RcDaDb<bits<8> op1, bits<12> op2, string asmstr, RegisterClass rcd>
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: IRR2<op1, op2, asmstr, rcd, RD, RD>;
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def MUL_rc : RC<0x53, 0x01, (outs RD:$d), (ins RD:$s1, s9imm:$const9),
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"mul $d, $s1, $const9", []>;
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def MUL_rc_e : RC<0x53, 0x03, (outs RE:$d), (ins RD:$s1, s9imm:$const9),
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"mul $d, $s1, $const9", []>;
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def MUL_rr2 : IRR2_RcDaDb<0x73, 0x0A, "mul", RD>;
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def MUL_rr2_e : IRR2_RcDaDb<0x73, 0x6A, "mul", RE>;
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def MUL_rr2 : IRR2<0x73, 0x0A, "mul", RD>;
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def MUL_rr2_e : IRR2<0x73, 0x6A, "mul", RE>;
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def MUL_srr : ISRR_db<0xE2, "mul">;
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multiclass mIRC_RR2_RcDaDb<bits<8> rc1, bits<7> rc2, bits<8> op1, bits<12> op2, string asmstr, RegisterClass rcd>{
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def _rc : IRC_RcDaC<rc1, rc2, asmstr, rcd>;
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def _rr2 : IRR2_RcDaDb<op1, op2, asmstr, rcd>;
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multiclass mI_MUL_<bits<8> rc1, bits<7> rc2, bits<8> op1, bits<12> op2, string asmstr, RegisterClass rcd>{
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def _rc : IRC<rc1, rc2, asmstr, rcd>;
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def _rr2 : IRR2<op1, op2, asmstr, rcd>;
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}
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defm MULS : mIRC_RR2_RcDaDb<0x53, 0x05, 0x73, 0x8A, "muls", RD>;
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defm MULS : mI_MUL_<0x53, 0x05, 0x73, 0x8A, "muls", RD>;
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class IRR1<bits<8> op1, bits<10> op2, string asmstr,
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RegisterClass rcd, string labela, string labelb>
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@ -1542,7 +1531,7 @@ multiclass mIRR1_LU2e<bits<8> op1, bits<10> op2, bits<10> op3, bits<10> op4, bit
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defm MUL_H : mIRR1_LU2e<0xB3, 0x1A, 0x19, 0x18, 0x1B, "mul.h">;
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multiclass mIRR1_mulq<bits<8> op, bits<10> op1, bits<10> op2, bits<10> op3, bits<10> op4,
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multiclass mI_MULQ_<bits<8> op, bits<10> op1, bits<10> op2, bits<10> op3, bits<10> op4,
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bits<10> op5, bits<10> op6, bits<10> op7, bits<10> op8, string asmstr>{
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def _rr1_2__ : IRR1<op, op1, asmstr, RD, "", "">;
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def _rr1_2__e : IRR1<op, op2, asmstr, RE, "", "">;
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@ -1556,10 +1545,10 @@ multiclass mIRR1_mulq<bits<8> op, bits<10> op1, bits<10> op2, bits<10> op3, bits
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def _rr1_2UU : IRR1<op, op8, asmstr, RD, "U", "U">;
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}
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defm MUL_Q : mIRR1_mulq<0x93, 0x02, 0x1B, 0x01, 0x19, 0x00, 0x18, 0x05, 0x04, "mul.q">;
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defm MUL_Q : mI_MULQ_<0x93, 0x02, 0x1B, 0x01, 0x19, 0x00, 0x18, 0x05, 0x04, "mul.q">;
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defm MUL_U : mIRC_RR2_RcDaDb<0x53, 0x02, 0x73, 0x68, "mul.u", RE>;
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defm MULS_U : mIRC_RR2_RcDaDb<0x53, 0x04, 0x73, 0x88, "muls.u", RE>;
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defm MUL_U : mI_MUL_<0x53, 0x02, 0x73, 0x68, "mul.u", RE>;
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defm MULS_U : mI_MUL_<0x53, 0x04, 0x73, 0x88, "muls.u", RE>;
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defm MULM_H : mIRR1_LU2e<0xB3, 0x1E, 0x1D, 0x1C, 0x1F, "mulm.h">;
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defm MULR_H : mIRR1_LU2e<0xB3, 0x0E, 0x0D, 0x0C, 0x0F, "mulr.h">;
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@ -1604,7 +1593,7 @@ defm ORN : mIRR_RC<0x0F, 0x0F, 0x8F, 0x0F, "orn">;
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def ORN_T : IBIT<0x07, 0x01, "orn.t">;
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def PACK_rrr : IRRR_DcEdDa<0x6B, 0x00, "pack">;
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def PACK_rrr : IRRR_d31<0x6B, 0x00, "pack", RD, RE>;
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def PARITY_rr : IRR_a<0x4B, 0x02, "parity">;
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@ -1624,11 +1613,11 @@ def RSLCX_sys : ISYS_0<0x0D, 0x09, "relck">;
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def RSTV_sys : ISYS_0<0x2F, 0x00, "restore">;
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def RSUB_rc : IRC_DcDaC<0x8B, 0x08, "rsub">;
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def RSUB_rc : IRC<0x8B, 0x08, "rsub">;
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def RSUB_sr : ISR_1<0x32, 0x05, "rsub">;
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def RSUBS_rc : IRC_DcDaC<0x8B, 0x0A, "rsubs">;
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def RSUBS_U_rc : IRC_DcDaC<0x8B, 0x0B, "rsubs.u">;
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def RSUBS_rc : IRC<0x8B, 0x0A, "rsubs">;
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def RSUBS_U_rc : IRC<0x8B, 0x0B, "rsubs.u">;
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multiclass mIRR_SR<bits<8> r1, bits<8> r2, bits<8> s1, bits<4> s2, string asmstr>{
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def _rr : IRR_a<r1, r2, asmstr>;
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@ -1641,10 +1630,10 @@ defm SAT_H : mIRR_SR<0x0B, 0x7E, 0x32, 0x02, "sat.h">;
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defm SAT_HU : mIRR_SR<0x0B, 0x7F, 0x32, 0x03, "sat.hu">;
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def SEL_rcr : IRCR<0xAB, 0x04, "sel">;
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def SEL_rrr : IRRR_DcDdDaDb<0x2B, 0x04, "sel">;
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def SEL_rrr : IRRR<0x2B, 0x04, "sel">;
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def SELN_rcr : IRCR<0xAB, 0x05, "seln">;
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def SELN_rrr : IRRR_DcDdDaDb<0x2B, 0x05, "seln">;
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def SELN_rrr : IRRR<0x2B, 0x05, "seln">;
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def SH_src : ISRC_1<0x06, "sh", RD>;
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defm SH : mIRR_RC<0x0F, 0x00, 0x8F, 0x00, "sh">;
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@ -1672,7 +1661,7 @@ defm SHA : mIRR_RC<0x0F, 0x01, 0x8F, 0x01, "sha">;
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defm SHA_H : mIRR_RC<0x0F, 0x41, 0x8F, 0x41, "sha.h">;
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defm SHAS : mIRR_RC<0x0F, 0x02, 0x8F, 0x02, "shas">;
|
||||
|
||||
def SHUFFLE_rc : IRC_DcDaC<0x8F, 0x07, "shuffle">;
|
||||
def SHUFFLE_rc : IRC<0x8F, 0x07, "shuffle">;
|
||||
|
||||
// A[b], off10, A[a] (BO)(Base + Short Offset Addressing Mode)
|
||||
class IBO_bso_st<bits<8> op1, bits<6> op2, string asmstr, RegisterClass rc>
|
||||
@ -1770,15 +1759,15 @@ defm SUB : mISRR_a15a<0xA2, 0x52, 0x5A, "sub">
|
||||
def SUB_A_rr : IRR_2<0x01, 0x02, "sub.a", RA, RA, RA>;
|
||||
def SUB_A_sc : ISC_A10C<0x20, "sub.a">;
|
||||
|
||||
def SUBC_rr : IRR2_RcDaDb<0x0B, 0x0D, "subc", RD>;
|
||||
def SUBC_rr : IRR2<0x0B, 0x0D, "subc">;
|
||||
|
||||
def SUBS_rr : IRR2_RcDaDb<0x0B, 0x0A, "subs", RD>;
|
||||
def SUBS_rr : IRR2<0x0B, 0x0A, "subs">;
|
||||
def SUBS_srr : ISRR_db<0x62, "subs">;
|
||||
|
||||
def SUBS_U_rr : IRR2_RcDaDb<0x0B, 0x0B, "subs.u", RD>;
|
||||
def SUBS_H_rr : IRR2_RcDaDb<0x0B, 0x6A, "subs.h", RD>;
|
||||
def SUBS_HU_rr : IRR2_RcDaDb<0x0B, 0x6B, "subs.hu", RD>;
|
||||
def SUBX_rr : IRR2_RcDaDb<0x0B, 0x0C, "subx", RD>;
|
||||
def SUBS_U_rr : IRR2<0x0B, 0x0B, "subs.u">;
|
||||
def SUBS_H_rr : IRR2<0x0B, 0x6A, "subs.h">;
|
||||
def SUBS_HU_rr : IRR2<0x0B, 0x6B, "subs.hu">;
|
||||
def SUBX_rr : IRR2<0x0B, 0x0C, "subx">;
|
||||
|
||||
def SVLCX_sys : ISYS_0<0x0D, 0x08, "svlcx">;
|
||||
|
||||
@ -1812,10 +1801,10 @@ defm XOR_LT_U : mIRR_RC<0x0B, 0x32, 0x8B, 0x32, "xor.lt.u">;
|
||||
|
||||
/// FPU Instructions
|
||||
|
||||
def MADD_F_rrr : IRRR_DcDdDaDb<0x6B, 0x06, "madd.f">, Requires<[HasV130_UP]>;
|
||||
def MSUB_F_rrr : IRRR_DcDdDaDb<0x6B, 0x07, "msub.f">, Requires<[HasV130_UP]>;
|
||||
def ADD_F_rrr : IRRR_DcDdDa<0x6B, 0x02, "add.f">;
|
||||
def SUB_F_rrr : IRRR_DcDdDa<0x6B, 0x03, "sub.f">;
|
||||
def MADD_F_rrr : IRRR<0x6B, 0x06, "madd.f">, Requires<[HasV130_UP]>;
|
||||
def MSUB_F_rrr : IRRR<0x6B, 0x07, "msub.f">, Requires<[HasV130_UP]>;
|
||||
def ADD_F_rrr : IRRR_d31<0x6B, 0x02, "add.f">;
|
||||
def SUB_F_rrr : IRRR_d31<0x6B, 0x03, "sub.f">;
|
||||
def MUL_F_rrr : IRR_dab<0x4B, 0x04, "mul.f">;
|
||||
def DIV_F_rr : IRR_dab<0x4B, 0x05, "div.f">, Requires<[HasV160_UP]>;
|
||||
|
||||
|
||||
Loading…
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Reference in New Issue
Block a user