mips: update core. this added bunch of new instructions & groups. updated Python & Java bindings accordingly

arch/Mips/MipsDisassembler.c

@@ -61,15 +61,15 @@ static DecodeStatus DecodeFGR64RegisterClass(MCInst *Inst,
 static DecodeStatus DecodeFGR32RegisterClass(MCInst *Inst,
 		unsigned RegNo, uint64_t Address, MCRegisterInfo *Decoder);
 
-static DecodeStatus DecodeFGRH32RegisterClass(MCInst *Inst,
-		unsigned RegNo, uint64_t Address, MCRegisterInfo *Decoder);
-
 static DecodeStatus DecodeCCRRegisterClass(MCInst *Inst,
 		unsigned RegNo, uint64_t Address, MCRegisterInfo *Decoder);
 
 static DecodeStatus DecodeFCCRegisterClass(MCInst *Inst,
 		unsigned RegNo, uint64_t Address, MCRegisterInfo *Decoder);
 
+static DecodeStatus DecodeFGRCCRegisterClass(MCInst *Inst,
+		unsigned RegNo, uint64_t Address, MCRegisterInfo *Decoder);
+
 static DecodeStatus DecodeHWRegsRegisterClass(MCInst *Inst,
 		unsigned Insn, uint64_t Address, MCRegisterInfo *Decoder);
 
@@ -100,12 +100,21 @@ static DecodeStatus DecodeMSA128DRegisterClass(MCInst *Inst,
 static DecodeStatus DecodeMSACtrlRegisterClass(MCInst *Inst,
 		unsigned RegNo, uint64_t Address, MCRegisterInfo *Decoder);
 
+static DecodeStatus DecodeCOP2RegisterClass(MCInst *Inst,
+		unsigned RegNo, uint64_t Address, MCRegisterInfo *Decoder);
+
 static DecodeStatus DecodeBranchTarget(MCInst *Inst,
 		unsigned Offset, uint64_t Address, MCRegisterInfo *Decoder);
 
 static DecodeStatus DecodeJumpTarget(MCInst *Inst,
 		unsigned Insn, uint64_t Address, MCRegisterInfo *Decoder);
 
+static DecodeStatus DecodeBranchTarget21(MCInst *Inst,
+		unsigned Offset, uint64_t Address, MCRegisterInfo *Decoder);
+
+static DecodeStatus DecodeBranchTarget26(MCInst *Inst,
+		unsigned Offset, uint64_t Address, MCRegisterInfo *Decoder);
+
 // DecodeBranchTargetMM - Decode microMIPS branch offset, which is
 // shifted left by 1 bit.
 static DecodeStatus DecodeBranchTargetMM(MCInst *Inst,
@@ -131,6 +140,9 @@ static DecodeStatus DecodeMemMMImm16(MCInst *Inst,
 static DecodeStatus DecodeFMem(MCInst *Inst, unsigned Insn,
 		uint64_t Address, MCRegisterInfo *Decoder);
 
+static DecodeStatus DecodeSpecial3LlSc(MCInst *Inst,
+		unsigned Insn, uint64_t Address, MCRegisterInfo *Decoder);
+
 static DecodeStatus DecodeSimm16(MCInst *Inst,
 		unsigned Insn, uint64_t Address, MCRegisterInfo *Decoder);
 
@@ -145,6 +157,36 @@ static DecodeStatus DecodeInsSize(MCInst *Inst,
 static DecodeStatus DecodeExtSize(MCInst *Inst,
 		unsigned Insn, uint64_t Address, MCRegisterInfo *Decoder);
 
+static DecodeStatus DecodeSimm19Lsl2(MCInst *Inst,
+		unsigned Insn, uint64_t Address, MCRegisterInfo *Decoder);
+
+static DecodeStatus DecodeSimm18Lsl3(MCInst *Inst,
+		unsigned Insn, uint64_t Address, MCRegisterInfo *Decoder);
+
+/// INSVE_[BHWD] have an implicit operand that the generated decoder doesn't
+/// handle.
+static DecodeStatus DecodeINSVE_DF_4(MCInst *MI,
+		uint32_t insn, uint64_t Address, MCRegisterInfo *Decoder);
+
+static DecodeStatus DecodeAddiGroupBranch_4(MCInst *MI,
+		uint32_t insn, uint64_t Address, MCRegisterInfo *Decoder);
+
+static DecodeStatus DecodeDaddiGroupBranch_4(MCInst *MI,
+		uint32_t insn, uint64_t Address, MCRegisterInfo *Decoder);
+
+static DecodeStatus DecodeBlezlGroupBranch_4(MCInst *MI,
+		uint32_t insn, uint64_t Address, MCRegisterInfo *Decoder);
+
+static DecodeStatus DecodeBgtzlGroupBranch_4(MCInst *MI,
+		uint32_t insn, uint64_t Address, MCRegisterInfo *Decoder);
+
+static DecodeStatus DecodeBgtzGroupBranch_4(MCInst *MI,
+		uint32_t insn, uint64_t Address, MCRegisterInfo *Decoder);
+
+static DecodeStatus DecodeBlezGroupBranch_4(MCInst *MI,
+		uint32_t insn, uint64_t Address, MCRegisterInfo *Decoder);
+
+
 #define GET_SUBTARGETINFO_ENUM
 #include "MipsGenSubtargetInfo.inc"
 
@@ -156,25 +198,32 @@ static uint64_t getFeatureBits(int mode)
 	// ref: MipsGenDisassemblerTables.inc::checkDecoderPredicate()
 	// some features are mutually execlusive
 	if (mode & CS_MODE_16) {
-		Bits &= ~Mips_FeatureMips32r2;
+		//Bits &= ~Mips_FeatureMips32r2;
-		Bits &= ~Mips_FeatureMips32;
+		//Bits &= ~Mips_FeatureMips32;
-		Bits &= ~Mips_FeatureFPIdx;
+		//Bits &= ~Mips_FeatureFPIdx;
-		Bits &= ~Mips_FeatureBitCount;
+		//Bits &= ~Mips_FeatureBitCount;
-		Bits &= ~Mips_FeatureSwap;
+		//Bits &= ~Mips_FeatureSwap;
-		Bits &= ~Mips_FeatureSEInReg;
+		//Bits &= ~Mips_FeatureSEInReg;
-		Bits &= ~Mips_FeatureMips64r2;
+		//Bits &= ~Mips_FeatureMips64r2;
-		Bits &= ~Mips_FeatureFP64Bit;
+		//Bits &= ~Mips_FeatureFP64Bit;
 	} else if (mode & CS_MODE_32) {
 		Bits &= ~Mips_FeatureMips16;
 		Bits &= ~Mips_FeatureFP64Bit;
+		Bits &= ~Mips_FeatureMips32r6;
+		Bits &= ~Mips_FeatureMips64r6;
 	} else if (mode & CS_MODE_64) {
 		Bits &= ~Mips_FeatureMips16;
+		Bits &= ~Mips_FeatureMips64r6;
+		Bits &= ~Mips_FeatureMips64r6;
 	}
 
-	if (mode & CS_MODE_MICRO)
+	if (mode & CS_MODE_MICRO) {
 		Bits |= Mips_FeatureMicroMips;
-	else
+		Bits &= ~Mips_FeatureMips4_32r2;
+		Bits &= ~Mips_FeatureMips2;
+	} else {
 		Bits &= ~Mips_FeatureMicroMips;
+	}
 
 	return Bits;
 }
@@ -200,9 +249,19 @@ void Mips_init(MCRegisterInfo *MRI)
 	// MipsRegStrings,
 	// MipsSubRegIdxLists, 12,
 	// MipsSubRegIdxRanges,   MipsRegEncodingTable);
-	MCRegisterInfo_InitMCRegisterInfo(MRI, MipsRegDesc, 317,
+
+	// InitMCRegisterInfo(MipsRegDesc, 386,
+	//		RA, PC,
+	//		MipsMCRegisterClasses, 47,
+	//		MipsRegUnitRoots, 265,
+	//		MipsRegDiffLists,
+	//		MipsRegStrings,
+	//		MipsSubRegIdxLists, 12,
+	//		MipsSubRegIdxRanges, MipsRegEncodingTable);
+
+	MCRegisterInfo_InitMCRegisterInfo(MRI, MipsRegDesc, 386,
 			0, 0, 
-			MipsMCRegisterClasses, 34,
+			MipsMCRegisterClasses, 47,
 			0, 0, 
 			MipsRegDiffLists,
 			0, 
@@ -272,6 +331,35 @@ static DecodeStatus MipsDisassembler_getInstruction(int mode, MCInst *instr,
 		return MCDisassembler_Fail;
 	}
 
+	if (((mode & CS_MODE_32) == 0) && ((mode & CS_MODE_MIPS3) == 0)) {	// COP3
+		// DEBUG(dbgs() << "Trying COP3_ table (32-bit opcodes):\n");
+		Result = decodeInstruction(DecoderTableCOP3_32, instr, Insn, Address, MRI, mode);
+		if (Result != MCDisassembler_Fail) {
+			*Size = 4;
+			return Result;
+		}
+	}
+
+	if (((mode & CS_MODE_MIPS32R6) != 0) && ((mode & CS_MODE_MIPSGP64) != 0)) {
+		// DEBUG(dbgs() << "Trying Mips32r6_64r6 (GPR64) table (32-bit opcodes):\n");
+		Result = decodeInstruction(DecoderTableMips32r6_64r6_GP6432, instr, Insn,
+				Address, MRI, mode);
+		if (Result != MCDisassembler_Fail) {
+			*Size = 4;
+			return Result;
+		}
+	}
+
+	if ((mode & CS_MODE_MIPS32R6) != 0) {
+		// DEBUG(dbgs() << "Trying Mips32r6_64r6 table (32-bit opcodes):\n");
+		Result = decodeInstruction(DecoderTableMips32r6_64r632, instr, Insn,
+				Address, MRI, mode);
+		if (Result != MCDisassembler_Fail) {
+			*Size = 4;
+			return Result;
+		}
+	}
+
 	// Calling the auto-generated decoder function.
 	Result = decodeInstruction(DecoderTableMips32, instr, Insn, Address, MRI, mode);
 	if (Result != MCDisassembler_Fail) {
@@ -346,6 +434,291 @@ static unsigned getReg(MCRegisterInfo *MRI, unsigned RC, unsigned RegNo)
 	return rc->RegsBegin[RegNo];
 }
 
+#define nullptr NULL
+
+static DecodeStatus DecodeINSVE_DF_4(MCInst *MI, uint32_t insn,
+		uint64_t Address, MCRegisterInfo *Decoder)
+{
+	typedef DecodeStatus (*DecodeFN)(MCInst *, unsigned, uint64_t, MCRegisterInfo *);
+	// The size of the n field depends on the element size
+	// The register class also depends on this.
+	uint32_t tmp = fieldFromInstruction(insn, 17, 5);
+	unsigned NSize = 0;
+	DecodeFN RegDecoder = nullptr;
+	if ((tmp & 0x18) == 0x00) { // INSVE_B
+		NSize = 4;
+		RegDecoder = DecodeMSA128BRegisterClass;
+	} else if ((tmp & 0x1c) == 0x10) { // INSVE_H
+		NSize = 3;
+		RegDecoder = DecodeMSA128HRegisterClass;
+	} else if ((tmp & 0x1e) == 0x18) { // INSVE_W
+		NSize = 2;
+		RegDecoder = DecodeMSA128WRegisterClass;
+	} else if ((tmp & 0x1f) == 0x1c) { // INSVE_D
+		NSize = 1;
+		RegDecoder = DecodeMSA128DRegisterClass;
+	} //else llvm_unreachable("Invalid encoding");
+
+	//assert(NSize != 0 && RegDecoder != nullptr);
+
+	// $wd
+	tmp = fieldFromInstruction(insn, 6, 5);
+	if (RegDecoder(MI, tmp, Address, Decoder) == MCDisassembler_Fail)
+		return MCDisassembler_Fail;
+	// $wd_in
+	if (RegDecoder(MI, tmp, Address, Decoder) == MCDisassembler_Fail)
+		return MCDisassembler_Fail;
+	// $n
+	tmp = fieldFromInstruction(insn, 16, NSize);
+	MCOperand_CreateImm0(MI, tmp);
+	// $ws
+	tmp = fieldFromInstruction(insn, 11, 5);
+	if (RegDecoder(MI, tmp, Address, Decoder) == MCDisassembler_Fail)
+		return MCDisassembler_Fail;
+	// $n2
+	MCOperand_CreateImm0(MI, 0);
+
+	return MCDisassembler_Success;
+}
+
+static DecodeStatus DecodeAddiGroupBranch_4(MCInst *MI, uint32_t insn,
+		uint64_t Address, MCRegisterInfo *Decoder)
+{
+	// If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled
+	// (otherwise we would have matched the ADDI instruction from the earlier
+	// ISA's instead).
+	//
+	// We have:
+	//    0b001000 sssss ttttt iiiiiiiiiiiiiiii
+	//      BOVC if rs >= rt
+	//      BEQZALC if rs == 0 && rt != 0
+	//      BEQC if rs < rt && rs != 0
+
+	uint32_t Rs = fieldFromInstruction(insn, 21, 5);
+	uint32_t Rt = fieldFromInstruction(insn, 16, 5);
+	uint32_t Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) << 2;
+	bool HasRs = false;
+
+	if (Rs >= Rt) {
+		MCInst_setOpcode(MI, Mips_BOVC);
+		HasRs = true;
+	} else if (Rs != 0 && Rs < Rt) {
+		MCInst_setOpcode(MI, Mips_BEQC);
+		HasRs = true;
+	} else
+		MCInst_setOpcode(MI, Mips_BEQZALC);
+
+	if (HasRs)
+		MCOperand_CreateReg0(MI, getReg(Decoder, Mips_GPR32RegClassID, Rs));
+
+	MCOperand_CreateReg0(MI, getReg(Decoder, Mips_GPR32RegClassID, Rt));
+	MCOperand_CreateImm0(MI, Imm);
+
+	return MCDisassembler_Success;
+}
+
+static DecodeStatus DecodeDaddiGroupBranch_4(MCInst *MI, uint32_t insn,
+		uint64_t Address, MCRegisterInfo *Decoder)
+{
+	// If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled
+	// (otherwise we would have matched the ADDI instruction from the earlier
+	// ISA's instead).
+	//
+	// We have:
+	//    0b011000 sssss ttttt iiiiiiiiiiiiiiii
+	//      BNVC if rs >= rt
+	//      BNEZALC if rs == 0 && rt != 0
+	//      BNEC if rs < rt && rs != 0
+
+	uint32_t Rs = fieldFromInstruction(insn, 21, 5);
+	uint32_t Rt = fieldFromInstruction(insn, 16, 5);
+	uint32_t Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) << 2;
+	bool HasRs = false;
+
+	if (Rs >= Rt) {
+		MCInst_setOpcode(MI, Mips_BNVC);
+		HasRs = true;
+	} else if (Rs != 0 && Rs < Rt) {
+		MCInst_setOpcode(MI, Mips_BNEC);
+		HasRs = true;
+	} else
+		MCInst_setOpcode(MI, Mips_BNEZALC);
+
+	if (HasRs)
+		MCOperand_CreateReg0(MI, getReg(Decoder, Mips_GPR32RegClassID, Rs));
+
+	MCOperand_CreateReg0(MI, getReg(Decoder, Mips_GPR32RegClassID, Rt));
+	MCOperand_CreateImm0(MI, Imm);
+
+	return MCDisassembler_Success;
+}
+
+static DecodeStatus DecodeBlezlGroupBranch_4(MCInst *MI, uint32_t insn,
+		uint64_t Address, MCRegisterInfo *Decoder)
+{
+	// If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled
+	// (otherwise we would have matched the BLEZL instruction from the earlier
+	// ISA's instead).
+	//
+	// We have:
+	//    0b010110 sssss ttttt iiiiiiiiiiiiiiii
+	//      Invalid if rs == 0
+	//      BLEZC   if rs == 0  && rt != 0
+	//      BGEZC   if rs == rt && rt != 0
+	//      BGEC    if rs != rt && rs != 0  && rt != 0
+
+	uint32_t Rs = fieldFromInstruction(insn, 21, 5);
+	uint32_t Rt = fieldFromInstruction(insn, 16, 5);
+	uint32_t Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) << 2;
+	bool HasRs = false;
+
+	if (Rt == 0)
+		return MCDisassembler_Fail;
+	else if (Rs == 0)
+		MCInst_setOpcode(MI, Mips_BLEZC);
+	else if (Rs == Rt)
+		MCInst_setOpcode(MI, Mips_BGEZC);
+	else {
+		HasRs = true;
+		MCInst_setOpcode(MI, Mips_BGEC);
+	}
+
+	if (HasRs)
+		MCOperand_CreateReg0(MI, getReg(Decoder, Mips_GPR32RegClassID, Rs));
+
+	MCOperand_CreateReg0(MI, getReg(Decoder, Mips_GPR32RegClassID, Rt));
+
+	MCOperand_CreateImm0(MI, Imm);
+
+	return MCDisassembler_Success;
+}
+
+static DecodeStatus DecodeBgtzlGroupBranch_4(MCInst *MI, uint32_t insn,
+		uint64_t Address, MCRegisterInfo *Decoder)
+{
+	// If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled
+	// (otherwise we would have matched the BGTZL instruction from the earlier
+	// ISA's instead).
+	//
+	// We have:
+	//    0b010111 sssss ttttt iiiiiiiiiiiiiiii
+	//      Invalid if rs == 0
+	//      BGTZC   if rs == 0  && rt != 0
+	//      BLTZC   if rs == rt && rt != 0
+	//      BLTC    if rs != rt && rs != 0  && rt != 0
+
+	bool HasRs = false;
+
+	uint32_t Rs = fieldFromInstruction(insn, 21, 5);
+	uint32_t Rt = fieldFromInstruction(insn, 16, 5);
+	uint32_t Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) << 2;
+
+	if (Rt == 0)
+		return MCDisassembler_Fail;
+	else if (Rs == 0)
+		MCInst_setOpcode(MI, Mips_BGTZC);
+	else if (Rs == Rt)
+		MCInst_setOpcode(MI, Mips_BLTZC);
+	else {
+		MCInst_setOpcode(MI, Mips_BLTC);
+		HasRs = true;
+	}
+
+	if (HasRs)
+		MCOperand_CreateReg0(MI, getReg(Decoder, Mips_GPR32RegClassID, Rs));
+
+	MCOperand_CreateReg0(MI, getReg(Decoder, Mips_GPR32RegClassID, Rt));
+	MCOperand_CreateImm0(MI, Imm);
+
+	return MCDisassembler_Success;
+}
+
+static DecodeStatus DecodeBgtzGroupBranch_4(MCInst *MI, uint32_t insn,
+		uint64_t Address, MCRegisterInfo *Decoder)
+{
+	// If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled
+	// (otherwise we would have matched the BGTZ instruction from the earlier
+	// ISA's instead).
+	//
+	// We have:
+	//    0b000111 sssss ttttt iiiiiiiiiiiiiiii
+	//      BGTZ    if rt == 0
+	//      BGTZALC if rs == 0 && rt != 0
+	//      BLTZALC if rs != 0 && rs == rt
+	//      BLTUC   if rs != 0 && rs != rt
+
+	uint32_t Rs = fieldFromInstruction(insn, 21, 5);
+	uint32_t Rt = fieldFromInstruction(insn, 16, 5);
+	uint32_t Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) << 2;
+	bool HasRs = false;
+	bool HasRt = false;
+
+	if (Rt == 0) {
+		MCInst_setOpcode(MI, Mips_BGTZ);
+		HasRs = true;
+	} else if (Rs == 0) {
+		MCInst_setOpcode(MI, Mips_BGTZALC);
+		HasRt = true;
+	} else if (Rs == Rt) {
+		MCInst_setOpcode(MI, Mips_BLTZALC);
+		HasRs = true;
+	} else {
+		MCInst_setOpcode(MI, Mips_BLTUC);
+		HasRs = true;
+		HasRt = true;
+	}
+
+	if (HasRs)
+		MCOperand_CreateReg0(MI, getReg(Decoder, Mips_GPR32RegClassID, Rs));
+
+	if (HasRt)
+		MCOperand_CreateReg0(MI, getReg(Decoder, Mips_GPR32RegClassID, Rt));
+
+	MCOperand_CreateImm0(MI, Imm);
+
+	return MCDisassembler_Success;
+}
+
+static DecodeStatus DecodeBlezGroupBranch_4(MCInst *MI, uint32_t insn,
+		uint64_t Address, MCRegisterInfo *Decoder)
+{
+	// If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled
+	// (otherwise we would have matched the BLEZL instruction from the earlier
+	// ISA's instead).
+	//
+	// We have:
+	//    0b000110 sssss ttttt iiiiiiiiiiiiiiii
+	//      Invalid   if rs == 0
+	//      BLEZALC   if rs == 0  && rt != 0
+	//      BGEZALC   if rs == rt && rt != 0
+	//      BGEUC     if rs != rt && rs != 0  && rt != 0
+
+	uint32_t Rs = fieldFromInstruction(insn, 21, 5);
+	uint32_t Rt = fieldFromInstruction(insn, 16, 5);
+	uint32_t Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) << 2;
+	bool HasRs = false;
+
+	if (Rt == 0)
+		return MCDisassembler_Fail;
+	else if (Rs == 0)
+		MCInst_setOpcode(MI, Mips_BLEZALC);
+	else if (Rs == Rt)
+		MCInst_setOpcode(MI, Mips_BGEZALC);
+	else {
+		HasRs = true;
+		MCInst_setOpcode(MI, Mips_BGEUC);
+	}
+
+	if (HasRs)
+		MCOperand_CreateReg0(MI, getReg(Decoder, Mips_GPR32RegClassID, Rs));
+
+	MCOperand_CreateReg0(MI, getReg(Decoder, Mips_GPR32RegClassID, Rt));
+
+	MCOperand_CreateImm0(MI, Imm);
+
+	return MCDisassembler_Success;
+}
+
 static DecodeStatus DecodeCPU16RegsRegisterClass(MCInst *Inst,
 		unsigned RegNo, uint64_t Address, MCRegisterInfo *Decoder)
 {
@@ -419,19 +792,6 @@ static DecodeStatus DecodeFGR32RegisterClass(MCInst *Inst,
 	return MCDisassembler_Success;
 }
 
-static DecodeStatus DecodeFGRH32RegisterClass(MCInst *Inst,
-		unsigned RegNo, uint64_t Address, MCRegisterInfo *Decoder)
-{
-	unsigned Reg;
-
-	if (RegNo > 31)
-		return MCDisassembler_Fail;
-
-	Reg = getReg(Decoder, Mips_FGRH32RegClassID, RegNo);
-	MCOperand_CreateReg0(Inst, Reg);
-	return MCDisassembler_Success;
-}
-
 static DecodeStatus DecodeCCRRegisterClass(MCInst *Inst,
 		unsigned RegNo, uint64_t Address, MCRegisterInfo *Decoder)
 {
@@ -458,6 +818,19 @@ static DecodeStatus DecodeFCCRegisterClass(MCInst *Inst,
 	return MCDisassembler_Success;
 }
 
+static DecodeStatus DecodeFGRCCRegisterClass(MCInst *Inst,
+		unsigned RegNo, uint64_t Address, MCRegisterInfo *Decoder)
+{
+	unsigned Reg;
+
+	if (RegNo > 31)
+		return MCDisassembler_Fail;
+
+	Reg = getReg(Decoder, Mips_FGRCCRegClassID, RegNo);
+	MCOperand_CreateReg0(Inst, Reg);
+	return MCDisassembler_Success;
+}
+
 static DecodeStatus DecodeMem(MCInst *Inst,
 		unsigned Insn, uint64_t Address, MCRegisterInfo *Decoder)
 {
@@ -468,7 +841,7 @@ static DecodeStatus DecodeMem(MCInst *Inst,
 	Reg = getReg(Decoder, Mips_GPR32RegClassID, Reg);
 	Base = getReg(Decoder, Mips_GPR32RegClassID, Base);
 
-	if(MCInst_getOpcode(Inst) == Mips_SC){
+	if (MCInst_getOpcode(Inst) == Mips_SC){
 		MCOperand_CreateReg0(Inst, Reg);
 	}
 
@@ -500,8 +873,7 @@ static DecodeStatus DecodeMSA128Mem(MCInst *Inst, unsigned Insn,
 	// .h - 2 bytes
 	// .w - 4 bytes
 	// .d - 8 bytes
-	switch(MCInst_getOpcode(Inst))
+	switch(MCInst_getOpcode(Inst)) {
-	{
 		default:
 			//assert (0 && "Unexpected instruction");
 			return MCDisassembler_Fail;
@@ -537,6 +909,9 @@ static DecodeStatus DecodeMemMMImm12(MCInst *Inst,
 	Reg = getReg(Decoder, Mips_GPR32RegClassID, Reg);
 	Base = getReg(Decoder, Mips_GPR32RegClassID, Base);
 
+	if (MCInst_getOpcode(Inst) == Mips_SC_MM)
+		MCOperand_CreateReg0(Inst, Reg);
+
 	MCOperand_CreateReg0(Inst, Reg);
 	MCOperand_CreateReg0(Inst, Base);
 	MCOperand_CreateImm0(Inst, Offset);
@@ -578,13 +953,37 @@ static DecodeStatus DecodeFMem(MCInst *Inst,
 	return MCDisassembler_Success;
 }
 
+static DecodeStatus DecodeSpecial3LlSc(MCInst *Inst,
+		unsigned Insn, uint64_t Address, MCRegisterInfo *Decoder)
+{
+	int64_t Offset = SignExtend64((Insn >> 7) & 0x1ff, 9);
+	unsigned Rt = fieldFromInstruction(Insn, 16, 5);
+	unsigned Base = fieldFromInstruction(Insn, 21, 5);
+
+	Rt = getReg(Decoder, Mips_GPR32RegClassID, Rt);
+	Base = getReg(Decoder, Mips_GPR32RegClassID, Base);
+
+	if (MCInst_getOpcode(Inst) == Mips_SC_R6 ||
+			MCInst_getOpcode(Inst) == Mips_SCD_R6) {
+		MCOperand_CreateReg0(Inst, Rt);
+	}
+
+	MCOperand_CreateReg0(Inst, Rt);
+	MCOperand_CreateReg0(Inst, Base);
+	MCOperand_CreateImm0(Inst, Offset);
+
+	return MCDisassembler_Success;
+}
+
 static DecodeStatus DecodeHWRegsRegisterClass(MCInst *Inst,
 		unsigned RegNo, uint64_t Address, MCRegisterInfo *Decoder)
 {
 	// Currently only hardware register 29 is supported.
 	if (RegNo != 29)
 		return  MCDisassembler_Fail;
+
 	MCOperand_CreateReg0(Inst, Mips_HWR29);
+
 	return MCDisassembler_Success;
 }
 
@@ -598,6 +997,7 @@ static DecodeStatus DecodeAFGR64RegisterClass(MCInst *Inst,
 
 	Reg = getReg(Decoder, Mips_AFGR64RegClassID, RegNo /2);
 	MCOperand_CreateReg0(Inst, Reg);
+
 	return MCDisassembler_Success;
 }
 
@@ -624,6 +1024,7 @@ static DecodeStatus DecodeHI32DSPRegisterClass(MCInst *Inst,
 
 	Reg = getReg(Decoder, Mips_HI32DSPRegClassID, RegNo);
 	MCOperand_CreateReg0(Inst, Reg);
+
 	return MCDisassembler_Success;
 }
 
@@ -637,6 +1038,7 @@ static DecodeStatus DecodeLO32DSPRegisterClass(MCInst *Inst,
 
 	Reg = getReg(Decoder, Mips_LO32DSPRegClassID, RegNo);
 	MCOperand_CreateReg0(Inst, Reg);
+
 	return MCDisassembler_Success;
 }
 
@@ -710,12 +1112,26 @@ static DecodeStatus DecodeMSACtrlRegisterClass(MCInst *Inst,
 	return MCDisassembler_Success;
 }
 
+static DecodeStatus DecodeCOP2RegisterClass(MCInst *Inst,
+		unsigned RegNo, uint64_t Address, MCRegisterInfo *Decoder)
+{
+	unsigned Reg;
+
+	if (RegNo > 31)
+		return MCDisassembler_Fail;
+
+	Reg = getReg(Decoder, Mips_COP2RegClassID, RegNo);
+	MCOperand_CreateReg0(Inst, Reg);
+
+	return MCDisassembler_Success;
+}
+
 static DecodeStatus DecodeBranchTarget(MCInst *Inst,
 		unsigned Offset, uint64_t Address, MCRegisterInfo *Decoder)
 {
-	unsigned BranchOffset = Offset & 0xffff;
+	int32_t BranchOffset = (SignExtend32(Offset, 16) << 2) + 4;
-	BranchOffset = SignExtend32(BranchOffset << 2, 18) + 4;
 	MCOperand_CreateImm0(Inst, BranchOffset);
+
 	return MCDisassembler_Success;
 }
 
@@ -724,15 +1140,35 @@ static DecodeStatus DecodeJumpTarget(MCInst *Inst,
 {
 	unsigned JumpOffset = fieldFromInstruction(Insn, 0, 26) << 2;
 	MCOperand_CreateImm0(Inst, JumpOffset);
+
+	return MCDisassembler_Success;
+}
+
+static DecodeStatus DecodeBranchTarget21(MCInst *Inst,
+		unsigned Offset, uint64_t Address, MCRegisterInfo *Decoder)
+{
+	int32_t BranchOffset = SignExtend32(Offset, 21) << 2;
+
+	MCOperand_CreateImm0(Inst, BranchOffset);
+
+	return MCDisassembler_Success;
+}
+
+static DecodeStatus DecodeBranchTarget26(MCInst *Inst,
+		unsigned Offset, uint64_t Address, MCRegisterInfo *Decoder)
+{
+	int32_t BranchOffset = SignExtend32(Offset, 26) << 2;
+
+	MCOperand_CreateImm0(Inst, BranchOffset);
 	return MCDisassembler_Success;
 }
 
 static DecodeStatus DecodeBranchTargetMM(MCInst *Inst,
 		unsigned Offset, uint64_t Address, MCRegisterInfo *Decoder)
 {
-	unsigned BranchOffset = Offset & 0xffff;
+	int32_t BranchOffset = SignExtend32(Offset, 16) << 1;
-	BranchOffset = SignExtend32(BranchOffset << 1, 18);
 	MCOperand_CreateImm0(Inst, BranchOffset);
+
 	return MCDisassembler_Success;
 }
 
@@ -741,6 +1177,7 @@ static DecodeStatus DecodeJumpTargetMM(MCInst *Inst,
 {
 	unsigned JumpOffset = fieldFromInstruction(Insn, 0, 26) << 1;
 	MCOperand_CreateImm0(Inst, JumpOffset);
+
 	return MCDisassembler_Success;
 }
 
@@ -777,4 +1214,18 @@ static DecodeStatus DecodeExtSize(MCInst *Inst,
 	return MCDisassembler_Success;
 }
 
+static DecodeStatus DecodeSimm19Lsl2(MCInst *Inst,
+		unsigned Insn, uint64_t Address, MCRegisterInfo *Decoder)
+{
+	MCOperand_CreateImm0(Inst, SignExtend32(Insn, 19) << 2);
+	return MCDisassembler_Success;
+}
+
+static DecodeStatus DecodeSimm18Lsl3(MCInst *Inst,
+		unsigned Insn, uint64_t Address, MCRegisterInfo *Decoder)
+{
+	MCOperand_CreateImm0(Inst, SignExtend32(Insn, 18) << 3);
+	return MCDisassembler_Success;
+}
+
 #endif

arch/Mips/MipsGenSubtargetInfo.inc

@@ -7,36 +7,46 @@
 \*===----------------------------------------------------------------------===*/
 
 /* Capstone Disassembly Engine, http://www.capstone-engine.org */
-/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013> */
+/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2014 */
 
 
 #ifdef GET_SUBTARGETINFO_ENUM
 #undef GET_SUBTARGETINFO_ENUM
 
-enum {
+#define Mips_FeatureCnMips (1ULL << 0)
-  Mips_FeatureBitCount =  1ULL << 0,
+#define Mips_FeatureDSP (1ULL << 1)
-  Mips_FeatureCondMov =  1ULL << 1,
+#define Mips_FeatureDSPR2 (1ULL << 2)
-  Mips_FeatureDSP =  1ULL << 2,
+#define Mips_FeatureEABI (1ULL << 3)
-  Mips_FeatureDSPR2 =  1ULL << 3,
+#define Mips_FeatureFP64Bit (1ULL << 4)
-  Mips_FeatureEABI =  1ULL << 4,
+#define Mips_FeatureFPXX (1ULL << 5)
-  Mips_FeatureFP64Bit =  1ULL << 5,
+#define Mips_FeatureGP64Bit (1ULL << 6)
-  Mips_FeatureFPIdx =  1ULL << 6,
+#define Mips_FeatureMSA (1ULL << 7)
-  Mips_FeatureGP64Bit =  1ULL << 7,
+#define Mips_FeatureMicroMips (1ULL << 8)
-  Mips_FeatureMSA =  1ULL << 8,
+#define Mips_FeatureMips1 (1ULL << 9)
-  Mips_FeatureMicroMips =  1ULL << 9,
+#define Mips_FeatureMips2 (1ULL << 10)
-  Mips_FeatureMips16 =  1ULL << 10,
+#define Mips_FeatureMips3 (1ULL << 11)
-  Mips_FeatureMips32 =  1ULL << 11,
+#define Mips_FeatureMips3_32 (1ULL << 12)
-  Mips_FeatureMips32r2 =  1ULL << 12,
+#define Mips_FeatureMips3_32r2 (1ULL << 13)
-  Mips_FeatureMips64 =  1ULL << 13,
+#define Mips_FeatureMips4 (1ULL << 14)
-  Mips_FeatureMips64r2 =  1ULL << 14,
+#define Mips_FeatureMips4_32 (1ULL << 15)
-  Mips_FeatureN32 =  1ULL << 15,
+#define Mips_FeatureMips4_32r2 (1ULL << 16)
-  Mips_FeatureN64 =  1ULL << 16,
+#define Mips_FeatureMips5 (1ULL << 17)
-  Mips_FeatureO32 =  1ULL << 17,
+#define Mips_FeatureMips5_32r2 (1ULL << 18)
-  Mips_FeatureSEInReg =  1ULL << 18,
+#define Mips_FeatureMips16 (1ULL << 19)
-  Mips_FeatureSingleFloat =  1ULL << 19,
+#define Mips_FeatureMips32 (1ULL << 20)
-  Mips_FeatureSwap =  1ULL << 20,
+#define Mips_FeatureMips32r2 (1ULL << 21)
-  Mips_FeatureVFPU =  1ULL << 21
+#define Mips_FeatureMips32r6 (1ULL << 22)
-};
+#define Mips_FeatureMips64 (1ULL << 23)
+#define Mips_FeatureMips64r2 (1ULL << 24)
+#define Mips_FeatureMips64r6 (1ULL << 25)
+#define Mips_FeatureN32 (1ULL << 26)
+#define Mips_FeatureN64 (1ULL << 27)
+#define Mips_FeatureNaN2008 (1ULL << 28)
+#define Mips_FeatureNoABICalls (1ULL << 29)
+#define Mips_FeatureNoOddSPReg (1ULL << 30)
+#define Mips_FeatureO32 (1ULL << 31)
+#define Mips_FeatureSingleFloat (1ULL << 32)
+#define Mips_FeatureVFPU (1ULL << 33)
 
 #endif // GET_SUBTARGETINFO_ENUM
 

bindings/java/capstone/Capstone.java

@@ -287,6 +287,9 @@ public class Capstone {
   public static final int CS_MODE_MCLASS = 1 << 5;	  // ARM's Cortex-M series
   public static final int CS_MODE_MICRO = 1 << 4;	  // MicroMips mode (Mips arch)
   public static final int CS_MODE_N64 = 1 << 5;	      // Nintendo-64 mode (Mips arch)
+  public static final int CS_MODE_MIPS3 = 1 << 6;     // Mips III ISA
+  public static final int CS_MODE_MIPS32R6 = 1 << 7;  // Mips32r6 ISA
+  public static final int CS_MODE_MIPSGP64 = 1 << 8;  // General Purpose Registers are 64-bit wide (MIPS arch)
   public static final int CS_MODE_BIG_ENDIAN = 1 << 31;
   public static final int CS_MODE_V9 = 1 << 4;	      // SparcV9 mode (Sparc arch)
 

bindings/python/capstone/__init__.py

@@ -39,6 +39,9 @@ __all__ = [
     'CS_MODE_MCLASS',
     'CS_MODE_MICRO',
     'CS_MODE_N64',
+    'CS_MODE_MIPS3',
+    'CS_MODE_MIPS32R6',
+    'CS_MODE_MIPSGP64',
     'CS_MODE_V9',
 
     'CS_OPT_SYNTAX',
@@ -100,6 +103,9 @@ CS_MODE_THUMB = (1 << 4)       # ARM's Thumb mode, including Thumb-2
 CS_MODE_MCLASS = (1 << 5)      # ARM's Cortex-M series
 CS_MODE_MICRO = (1 << 4)       # MicroMips mode (MIPS architecture)
 CS_MODE_N64 = (1 << 5)         # Nintendo-64 mode (MIPS architecture)
+CS_MODE_MIPS3 = 1 << 6         # Mips III ISA
+CS_MODE_MIPS32R6 = 1 << 7      # Mips32r6 ISA
+CS_MODE_MIPSGP64 = 1 << 8      # General Purpose Registers are 64-bit wide (MIPS arch)
 CS_MODE_V9 = (1 << 4)          # Nintendo-64 mode (MIPS architecture)
 CS_MODE_BIG_ENDIAN = (1 << 31) # big-endian mode
 

include/capstone.h

@@ -73,6 +73,9 @@ typedef enum cs_mode {
 	CS_MODE_MCLASS = 1 << 5,	// ARM's Cortex-M series
 	CS_MODE_MICRO = 1 << 4, // MicroMips mode (MIPS architecture)
 	CS_MODE_N64 = 1 << 5, // Nintendo-64 mode (MIPS architecture)
+	CS_MODE_MIPS3 = 1 << 6, // Mips III ISA
+	CS_MODE_MIPS32R6 = 1 << 7, // Mips32r6 ISA
+	CS_MODE_MIPSGP64 = 1 << 8, // General Purpose Registers are 64-bit wide (MIPS arch)
 	CS_MODE_V9 = 1 << 4, // SparcV9 mode (Sparc architecture)
 	CS_MODE_BIG_ENDIAN = 1 << 31	// big endian mode
 } cs_mode;

include/mips.h

@@ -189,6 +189,14 @@ typedef enum mips_reg {
 	MIPS_REG_LO,
 	MIPS_REG_PC,
 
+	MIPS_REG_P0,
+	MIPS_REG_P1,
+	MIPS_REG_P2,
+
+	MIPS_REG_MPL0,
+	MIPS_REG_MPL1,
+	MIPS_REG_MPL2,
+
 	MIPS_REG_MAX,	// <-- mark the end of the list or registers
 
 	// alias registers
@@ -242,6 +250,7 @@ typedef enum mips_insn {
 
 	MIPS_INS_ABSQ_S,
 	MIPS_INS_ADD,
+	MIPS_INS_ADDIUPC,
 	MIPS_INS_ADDQH,
 	MIPS_INS_ADDQH_R,
 	MIPS_INS_ADDQ,
@@ -260,40 +269,73 @@ typedef enum mips_insn {
 	MIPS_INS_ADD_A,
 	MIPS_INS_ADDI,
 	MIPS_INS_ADDIU,
+	MIPS_INS_ALIGN,
+	MIPS_INS_ALUIPC,
 	MIPS_INS_AND,
 	MIPS_INS_ANDI,
 	MIPS_INS_APPEND,
 	MIPS_INS_ASUB_S,
 	MIPS_INS_ASUB_U,
+	MIPS_INS_AUI,
+	MIPS_INS_AUIPC,
 	MIPS_INS_AVER_S,
 	MIPS_INS_AVER_U,
 	MIPS_INS_AVE_S,
 	MIPS_INS_AVE_U,
+	MIPS_INS_BADDU,
+	MIPS_INS_BAL,
+	MIPS_INS_BALC,
 	MIPS_INS_BALIGN,
+	MIPS_INS_BC,
+	MIPS_INS_BC1EQZ,
 	MIPS_INS_BC1F,
+	MIPS_INS_BC1NEZ,
 	MIPS_INS_BC1T,
+	MIPS_INS_BC2EQZ,
+	MIPS_INS_BC2NEZ,
 	MIPS_INS_BCLRI,
 	MIPS_INS_BCLR,
 	MIPS_INS_BEQ,
+	MIPS_INS_BEQC,
+	MIPS_INS_BEQZALC,
+	MIPS_INS_BEQZC,
+	MIPS_INS_BGEC,
+	MIPS_INS_BGEUC,
 	MIPS_INS_BGEZ,
 	MIPS_INS_BGEZAL,
+	MIPS_INS_BGEZALC,
+	MIPS_INS_BGEZC,
 	MIPS_INS_BGTZ,
+	MIPS_INS_BGTZALC,
+	MIPS_INS_BGTZC,
 	MIPS_INS_BINSLI,
 	MIPS_INS_BINSL,
 	MIPS_INS_BINSRI,
 	MIPS_INS_BINSR,
 	MIPS_INS_BITREV,
+	MIPS_INS_BITSWAP,
 	MIPS_INS_BLEZ,
+	MIPS_INS_BLEZALC,
+	MIPS_INS_BLEZC,
+	MIPS_INS_BLTC,
+	MIPS_INS_BLTUC,
 	MIPS_INS_BLTZ,
 	MIPS_INS_BLTZAL,
+	MIPS_INS_BLTZALC,
+	MIPS_INS_BLTZC,
 	MIPS_INS_BMNZI,
 	MIPS_INS_BMNZ,
 	MIPS_INS_BMZI,
 	MIPS_INS_BMZ,
 	MIPS_INS_BNE,
+	MIPS_INS_BNEC,
 	MIPS_INS_BNEGI,
 	MIPS_INS_BNEG,
+	MIPS_INS_BNEZALC,
+	MIPS_INS_BNEZC,
+	MIPS_INS_BNVC,
 	MIPS_INS_BNZ,
+	MIPS_INS_BOVC,
 	MIPS_INS_BPOSGE32,
 	MIPS_INS_BREAK,
 	MIPS_INS_BSELI,
@@ -306,11 +348,15 @@ typedef enum mips_insn {
 	MIPS_INS_BNEZ,
 	MIPS_INS_BTEQZ,
 	MIPS_INS_BTNEZ,
+	MIPS_INS_CACHE,
 	MIPS_INS_CEIL,
 	MIPS_INS_CEQI,
 	MIPS_INS_CEQ,
 	MIPS_INS_CFC1,
 	MIPS_INS_CFCMSA,
+	MIPS_INS_CINS,
+	MIPS_INS_CINS32,
+	MIPS_INS_CLASS,
 	MIPS_INS_CLEI_S,
 	MIPS_INS_CLEI_U,
 	MIPS_INS_CLE_S,
@@ -336,8 +382,15 @@ typedef enum mips_insn {
 	MIPS_INS_DADDI,
 	MIPS_INS_DADDIU,
 	MIPS_INS_DADDU,
+	MIPS_INS_DAHI,
+	MIPS_INS_DALIGN,
+	MIPS_INS_DATI,
+	MIPS_INS_DAUI,
+	MIPS_INS_DBITSWAP,
 	MIPS_INS_DCLO,
 	MIPS_INS_DCLZ,
+	MIPS_INS_DDIV,
+	MIPS_INS_DDIVU,
 	MIPS_INS_DERET,
 	MIPS_INS_DEXT,
 	MIPS_INS_DEXTM,
@@ -346,17 +399,25 @@ typedef enum mips_insn {
 	MIPS_INS_DINS,
 	MIPS_INS_DINSM,
 	MIPS_INS_DINSU,
+	MIPS_INS_DIV,
+	MIPS_INS_DIVU,
 	MIPS_INS_DIV_S,
 	MIPS_INS_DIV_U,
 	MIPS_INS_DLSA,
 	MIPS_INS_DMFC0,
 	MIPS_INS_DMFC1,
 	MIPS_INS_DMFC2,
+	MIPS_INS_DMOD,
+	MIPS_INS_DMODU,
 	MIPS_INS_DMTC0,
 	MIPS_INS_DMTC1,
 	MIPS_INS_DMTC2,
+	MIPS_INS_DMUH,
+	MIPS_INS_DMUHU,
+	MIPS_INS_DMUL,
 	MIPS_INS_DMULT,
 	MIPS_INS_DMULTU,
+	MIPS_INS_DMULU,
 	MIPS_INS_DOTP_S,
 	MIPS_INS_DOTP_U,
 	MIPS_INS_DPADD_S,
@@ -368,6 +429,7 @@ typedef enum mips_insn {
 	MIPS_INS_DPAU,
 	MIPS_INS_DPAX,
 	MIPS_INS_DPA,
+	MIPS_INS_DPOP,
 	MIPS_INS_DPSQX_SA,
 	MIPS_INS_DPSQX_S,
 	MIPS_INS_DPSQ_SA,
@@ -381,7 +443,6 @@ typedef enum mips_insn {
 	MIPS_INS_DROTR32,
 	MIPS_INS_DROTRV,
 	MIPS_INS_DSBH,
-	MIPS_INS_DDIV,
 	MIPS_INS_DSHD,
 	MIPS_INS_DSLL,
 	MIPS_INS_DSLL32,
@@ -392,10 +453,9 @@ typedef enum mips_insn {
 	MIPS_INS_DSRL,
 	MIPS_INS_DSRL32,
 	MIPS_INS_DSRLV,
+	MIPS_INS_DSUB,
 	MIPS_INS_DSUBU,
-	MIPS_INS_DDIVU,
+	MIPS_INS_EHB,
-	MIPS_INS_DIV,
-	MIPS_INS_DIVU,
 	MIPS_INS_EI,
 	MIPS_INS_ERET,
 	MIPS_INS_EXT,
@@ -411,6 +471,8 @@ typedef enum mips_insn {
 	MIPS_INS_EXTR_R,
 	MIPS_INS_EXTR_S,
 	MIPS_INS_EXTR,
+	MIPS_INS_EXTS,
+	MIPS_INS_EXTS32,
 	MIPS_INS_ABS,
 	MIPS_INS_FADD,
 	MIPS_INS_FCAF,
@@ -485,6 +547,9 @@ typedef enum mips_insn {
 	MIPS_INS_J,
 	MIPS_INS_JAL,
 	MIPS_INS_JALR,
+	MIPS_INS_JALX,
+	MIPS_INS_JIALC,
+	MIPS_INS_JIC,
 	MIPS_INS_JR,
 	MIPS_INS_JRC,
 	MIPS_INS_JALRC,
@@ -494,8 +559,10 @@ typedef enum mips_insn {
 	MIPS_INS_LD,
 	MIPS_INS_LDC1,
 	MIPS_INS_LDC2,
+	MIPS_INS_LDC3,
 	MIPS_INS_LDI,
 	MIPS_INS_LDL,
+	MIPS_INS_LDPC,
 	MIPS_INS_LDR,
 	MIPS_INS_LDXC1,
 	MIPS_INS_LH,
@@ -509,22 +576,28 @@ typedef enum mips_insn {
 	MIPS_INS_LW,
 	MIPS_INS_LWC1,
 	MIPS_INS_LWC2,
+	MIPS_INS_LWC3,
 	MIPS_INS_LWL,
+	MIPS_INS_LWPC,
 	MIPS_INS_LWR,
+	MIPS_INS_LWUPC,
 	MIPS_INS_LWU,
 	MIPS_INS_LWX,
 	MIPS_INS_LWXC1,
 	MIPS_INS_LI,
 	MIPS_INS_MADD,
+	MIPS_INS_MADDF,
 	MIPS_INS_MADDR_Q,
 	MIPS_INS_MADDU,
 	MIPS_INS_MADDV,
 	MIPS_INS_MADD_Q,
 	MIPS_INS_MAQ_SA,
 	MIPS_INS_MAQ_S,
+	MIPS_INS_MAXA,
 	MIPS_INS_MAXI_S,
 	MIPS_INS_MAXI_U,
 	MIPS_INS_MAX_A,
+	MIPS_INS_MAX,
 	MIPS_INS_MAX_S,
 	MIPS_INS_MAX_U,
 	MIPS_INS_MFC0,
@@ -533,12 +606,16 @@ typedef enum mips_insn {
 	MIPS_INS_MFHC1,
 	MIPS_INS_MFHI,
 	MIPS_INS_MFLO,
+	MIPS_INS_MINA,
 	MIPS_INS_MINI_S,
 	MIPS_INS_MINI_U,
 	MIPS_INS_MIN_A,
+	MIPS_INS_MIN,
 	MIPS_INS_MIN_S,
 	MIPS_INS_MIN_U,
+	MIPS_INS_MOD,
 	MIPS_INS_MODSUB,
+	MIPS_INS_MODU,
 	MIPS_INS_MOD_S,
 	MIPS_INS_MOD_U,
 	MIPS_INS_MOVE,
@@ -547,6 +624,7 @@ typedef enum mips_insn {
 	MIPS_INS_MOVT,
 	MIPS_INS_MOVZ,
 	MIPS_INS_MSUB,
+	MIPS_INS_MSUBF,
 	MIPS_INS_MSUBR_Q,
 	MIPS_INS_MSUBU,
 	MIPS_INS_MSUBV,
@@ -558,6 +636,14 @@ typedef enum mips_insn {
 	MIPS_INS_MTHI,
 	MIPS_INS_MTHLIP,
 	MIPS_INS_MTLO,
+	MIPS_INS_MTM0,
+	MIPS_INS_MTM1,
+	MIPS_INS_MTM2,
+	MIPS_INS_MTP0,
+	MIPS_INS_MTP1,
+	MIPS_INS_MTP2,
+	MIPS_INS_MUH,
+	MIPS_INS_MUHU,
 	MIPS_INS_MULEQ_S,
 	MIPS_INS_MULEU_S,
 	MIPS_INS_MULQ_RS,
@@ -567,6 +653,7 @@ typedef enum mips_insn {
 	MIPS_INS_MULSA,
 	MIPS_INS_MULT,
 	MIPS_INS_MULTU,
+	MIPS_INS_MULU,
 	MIPS_INS_MULV,
 	MIPS_INS_MUL_Q,
 	MIPS_INS_MUL_S,
@@ -580,10 +667,12 @@ typedef enum mips_insn {
 	MIPS_INS_OR,
 	MIPS_INS_ORI,
 	MIPS_INS_PACKRL,
+	MIPS_INS_PAUSE,
 	MIPS_INS_PCKEV,
 	MIPS_INS_PCKOD,
 	MIPS_INS_PCNT,
 	MIPS_INS_PICK,
+	MIPS_INS_POP,
 	MIPS_INS_PRECEQU,
 	MIPS_INS_PRECEQ,
 	MIPS_INS_PRECEU,
@@ -593,12 +682,14 @@ typedef enum mips_insn {
 	MIPS_INS_PRECR,
 	MIPS_INS_PRECR_SRA,
 	MIPS_INS_PRECR_SRA_R,
+	MIPS_INS_PREF,
 	MIPS_INS_PREPEND,
 	MIPS_INS_RADDU,
 	MIPS_INS_RDDSP,
 	MIPS_INS_RDHWR,
 	MIPS_INS_REPLV,
 	MIPS_INS_REPL,
+	MIPS_INS_RINT,
 	MIPS_INS_ROTR,
 	MIPS_INS_ROTRV,
 	MIPS_INS_ROUND,
@@ -608,13 +699,20 @@ typedef enum mips_insn {
 	MIPS_INS_SC,
 	MIPS_INS_SCD,
 	MIPS_INS_SD,
+	MIPS_INS_SDBBP,
 	MIPS_INS_SDC1,
 	MIPS_INS_SDC2,
+	MIPS_INS_SDC3,
 	MIPS_INS_SDL,
 	MIPS_INS_SDR,
 	MIPS_INS_SDXC1,
 	MIPS_INS_SEB,
 	MIPS_INS_SEH,
+	MIPS_INS_SELEQZ,
+	MIPS_INS_SELNEZ,
+	MIPS_INS_SEL,
+	MIPS_INS_SEQ,
+	MIPS_INS_SEQI,
 	MIPS_INS_SH,
 	MIPS_INS_SHF,
 	MIPS_INS_SHILO,
@@ -638,6 +736,8 @@ typedef enum mips_insn {
 	MIPS_INS_SLTI,
 	MIPS_INS_SLTIU,
 	MIPS_INS_SLTU,
+	MIPS_INS_SNE,
+	MIPS_INS_SNEI,
 	MIPS_INS_SPLATI,
 	MIPS_INS_SPLAT,
 	MIPS_INS_SRA,
@@ -650,6 +750,7 @@ typedef enum mips_insn {
 	MIPS_INS_SRLRI,
 	MIPS_INS_SRLR,
 	MIPS_INS_SRLV,
+	MIPS_INS_SSNOP,
 	MIPS_INS_ST,
 	MIPS_INS_SUBQH,
 	MIPS_INS_SUBQH_R,
@@ -669,6 +770,7 @@ typedef enum mips_insn {
 	MIPS_INS_SW,
 	MIPS_INS_SWC1,
 	MIPS_INS_SWC2,
+	MIPS_INS_SWC3,
 	MIPS_INS_SWL,
 	MIPS_INS_SWR,
 	MIPS_INS_SWXC1,
@@ -680,6 +782,10 @@ typedef enum mips_insn {
 	MIPS_INS_TGEI,
 	MIPS_INS_TGEIU,
 	MIPS_INS_TGEU,
+	MIPS_INS_TLBP,
+	MIPS_INS_TLBR,
+	MIPS_INS_TLBWI,
+	MIPS_INS_TLBWR,
 	MIPS_INS_TLT,
 	MIPS_INS_TLTI,
 	MIPS_INS_TLTIU,
@@ -687,6 +793,9 @@ typedef enum mips_insn {
 	MIPS_INS_TNE,
 	MIPS_INS_TNEI,
 	MIPS_INS_TRUNC,
+	MIPS_INS_V3MULU,
+	MIPS_INS_VMM0,
+	MIPS_INS_VMULU,
 	MIPS_INS_VSHF,
 	MIPS_INS_WAIT,
 	MIPS_INS_WRDSP,
@@ -698,7 +807,7 @@ typedef enum mips_insn {
 	MIPS_INS_NOP,
 	MIPS_INS_NEGU,
 
-	MIPS_INS_MAX,
+	MIPS_INS_MAXIMUM,
 } mips_insn;
 
 //> Group of MIPS instructions
@@ -723,6 +832,21 @@ typedef enum mips_insn_group {
 	MIPS_GRP_NOTFP64BIT,
 	MIPS_GRP_NOTINMICROMIPS,
 	MIPS_GRP_NOTNACL,
+	MIPS_GRP_NOTMIPS32R6,
+	MIPS_GRP_NOTMIPS64R6,
+	MIPS_GRP_CNMIPS,
+	MIPS_GRP_MIPS32,
+	MIPS_GRP_MIPS32R6,
+	MIPS_GRP_MIPS64R6,
+	MIPS_GRP_MIPS2,
+	MIPS_GRP_MIPS3,
+	MIPS_GRP_MIPS3_32,
+	MIPS_GRP_MIPS3_32R2,
+	MIPS_GRP_MIPS4_32,
+	MIPS_GRP_MIPS4_32R2,
+	MIPS_GRP_MIPS5_32R2,
+	MIPS_GRP_GP32BIT,
+	MIPS_GRP_GP64BIT,
 
 	MIPS_GRP_JUMP,	// all jump instructions (conditional+direct+indirect jumps)