Fix disassemble of xor

- update generate file using 78180b63f8

MCInstrDesc.h

@@ -25,11 +25,21 @@
 // Machine Operand Flags and Description
 //===----------------------------------------------------------------------===//
 
-// Operand constraints
-enum MCOI_OperandConstraint {
-	MCOI_TIED_TO = 0,    // Must be allocated the same register as.
+/// Operand constraints. These are encoded in 16 bits with one of the
+/// low-order 3 bits specifying that a constraint is present and the
+/// corresponding high-order hex digit specifying the constraint value.
+/// This allows for a maximum of 3 constraints.
+typedef enum {
+	MCOI_TIED_TO = 0,    // Operand tied to another operand.
 	MCOI_EARLY_CLOBBER   // Operand is an early clobber register operand
-};
+} MCOI_OperandConstraint;
+
+// Define a macro to produce each constraint value.
+#define CONSTRAINT_MCOI_TIED_TO(op) \
+  ((1 << MCOI_TIED_TO) | ((op) << (4 + MCOI_TIED_TO * 4)))
+
+#define CONSTRAINT_MCOI_EARLY_CLOBBER \
+  (1 << MCOI_EARLY_CLOBBER)
 
 /// OperandFlags - These are flags set on operands, but should be considered
 /// private, all access should go through the MCOperandInfo accessors.

arch/TriCore/TriCoreGenAsmWriter.inc

@@ -16,7 +16,7 @@
 
 /// getMnemonic - This method is automatically generated by tablegen
 /// from the instruction set description.
-MnemonicBitsInfo getMnemonic(MCInst *MI, SStream *O) {
+static MnemonicBitsInfo getMnemonic(MCInst *MI, SStream *O) {
 #ifndef CAPSTONE_DIET
   static const char AsmStrs[] = {
   /* 0 */ "sub %d15, \0"
@@ -3682,7 +3682,7 @@ const char *getRegisterName(unsigned RegNo) {
 #ifdef PRINT_ALIAS_INSTR
 #undef PRINT_ALIAS_INSTR
 
-bool printAliasInstr(MCInst *MI, uint64_t Address, SStream *OS) {
+static bool printAliasInstr(MCInst *MI, uint64_t Address, SStream *OS) {
 #ifndef CAPSTONE_DIET
   return false;
 #endif // CAPSTONE_DIET

arch/TriCore/TriCoreGenCSMappingInsnName.inc

@@ -11,7 +11,7 @@
 /* Capstone's LLVM TableGen Backends: */
 /* https://github.com/capstone-engine/llvm-capstone */
 
-  "xor.t", // TRICORE_INS_XOR_T
+  "invalid", // TRICORE_INS_INVALID
   "absdifs.b", // TRICORE_INS_ABSDIFS_B
   "absdifs.h", // TRICORE_INS_ABSDIFS_H
   "absdifs", // TRICORE_INS_ABSDIFS
@@ -400,4 +400,5 @@
   "xor.lt.u", // TRICORE_INS_XOR_LT_U
   "xor.lt", // TRICORE_INS_XOR_LT
   "xor.ne", // TRICORE_INS_XOR_NE
+  "xor.t", // TRICORE_INS_XOR_T
   "xor", // TRICORE_INS_XOR

arch/TriCore/TriCoreInstPrinter.c

@@ -483,9 +483,6 @@ static void set_mem_access(MCInst *MI, unsigned int access)
 	// TODO: TriCore
 }
 
-MnemonicBitsInfo getMnemonic(MCInst *MI, SStream *O);
-bool printAliasInstr(MCInst *MI, uint64_t Address, SStream *OS);
-
 #define PRINT_ALIAS_INSTR
 
 #include "TriCoreGenAsmWriter.inc"

suite/MC/TriCore/handwrite.s.cs

@@ -0,0 +1,2 @@
+# CS_ARCH_TRICORE, CS_MODE_TRICORE_162, None
+0x8f,0xff,0x83,0x81 = xor %d8, %d15, 0x3f